October 2023 - U-Boot

[PATCH 00/11] Introduce basic support for TI's AM62Px SoC family
by Bryan Brattlof 16 Oct '23

16 Oct '23

Hello Everyone! The AM62Px is an extension of the existing Sitara AM62x low-cost family of application processors built for Automotive and Linux Application development. Scalable Arm Cortex-A53 performance and embedded features, such as: multi high-definition display support, 3D-graphics acceleration, 4K video acceleration, and extensive peripherals make the AM62Px well-suited for a broad range of automation and industrial application, including automotive digital instrumentation, automotive displays, industrial HMI, and more. Some highlights of AM62P SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single core variants are provided in the same package to allow HW compatible designs. * One Device manager Cortex-R5F for system power and resource management, and one Cortex-R5F for Functional Safety or general-purpose usage. * One 3D GPU up to 50 GLFOPS * H.264/H.265 Video Encode/Decode. * Display support: 3x display support over OLDI/LVDS (1x OLDI-DL, 1x or 2x OLDI-SL), DSI, or DPI. Up to 3840x1080 @ 60fps resolution * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3xMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, 1xCSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized Hardware Security Module with support for secure boot, debug security and crypto acceleration and trusted execution environment. * One 32-bit DDR Subsystem that supports LPDDR4, DDR4 memory types. * Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, enabling battery powered system design. For those interested, more details about this SoC can be found in the Technical Reference Manual here: https://www.ti.com/lit/pdf/spruj83 Proof-of-Life: https://paste.sr.ht/~bryanb/af2ac108a9362549aa326f182e87918d52bf2d71 Currently, while more peripherals are being added in Linux[0], this series will only support UART boot. Thanks for reviewing! ~Bryan [0] https://lore.kernel.org/lkml/20231010035903.520635-4-bb@ti.com/ Bryan Brattlof (10): soc: add info to identify the am62p SoC family arm: mach-k3: am62px: introduce clock and device files for wkup spl ram: k3-ddrss: enable the am62ax's DDR controller for am62px arm: mach-k3: invert logic for split DM firmware config arch: mach-k3: introduce basic files to support the am62px SoC family board: ti: introduce basic board files for the am62px family arm: dts: add am62p5 dtbs from linux arm: dts: introduce am62p5 uboot dts files configs: introduce configs needed for the am62px doc: board: ti: introduce am62px documentation Hari Nagalla (1): firmware: ti_sci_static_data: add static DMA channel data arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi | 2798 +++++++++++++++++ arch/arm/dts/k3-am62p-main.dtsi | 136 + arch/arm/dts/k3-am62p-mcu.dtsi | 15 + arch/arm/dts/k3-am62p-sk-binman.dtsi | 425 +++ arch/arm/dts/k3-am62p-wakeup.dtsi | 32 + arch/arm/dts/k3-am62p.dtsi | 122 + arch/arm/dts/k3-am62p5-r5-sk.dts | 88 + arch/arm/dts/k3-am62p5-sk-u-boot.dtsi | 14 + arch/arm/dts/k3-am62p5-sk.dts | 116 + arch/arm/dts/k3-am62p5.dtsi | 107 + arch/arm/mach-k3/Kconfig | 9 +- arch/arm/mach-k3/Makefile | 2 + arch/arm/mach-k3/am62p5_init.c | 261 ++ arch/arm/mach-k3/am62px/Makefile | 6 + arch/arm/mach-k3/am62px/clk-data.c | 325 ++ arch/arm/mach-k3/am62px/dev-data.c | 71 + arch/arm/mach-k3/arm64-mmu.c | 5 +- .../arm/mach-k3/include/mach/am62p_hardware.h | 83 + arch/arm/mach-k3/include/mach/am62p_spl.h | 49 + arch/arm/mach-k3/include/mach/hardware.h | 6 + arch/arm/mach-k3/include/mach/spl.h | 4 + board/ti/am62px/Kconfig | 52 + board/ti/am62px/MAINTAINERS | 9 + board/ti/am62px/Makefile | 7 + board/ti/am62px/am62px.env | 18 + board/ti/am62px/board-cfg.yaml | 37 + board/ti/am62px/evm.c | 30 + board/ti/am62px/pm-cfg.yaml | 12 + board/ti/am62px/rm-cfg.yaml | 1150 +++++++ board/ti/am62px/sec-cfg.yaml | 378 +++ board/ti/am62px/tifs-rm-cfg.yaml | 1010 ++++++ configs/am62px_evm_a53_defconfig | 176 ++ configs/am62px_evm_r5_defconfig | 137 + doc/board/ti/am62px_sk.rst | 289 ++ doc/board/ti/k3.rst | 1 + drivers/clk/ti/clk-k3.c | 6 + drivers/firmware/ti_sci_static_data.h | 5 +- drivers/power/domain/ti-power-domain.c | 6 + drivers/ram/Kconfig | 2 +- drivers/soc/soc_ti_k3.c | 3 + include/configs/am62px_evm.h | 18 + include/k3-clk.h | 1 + include/k3-dev.h | 1 + 43 files changed, 8015 insertions(+), 7 deletions(-) create mode 100644 arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi create mode 100644 arch/arm/dts/k3-am62p-main.dtsi create mode 100644 arch/arm/dts/k3-am62p-mcu.dtsi create mode 100644 arch/arm/dts/k3-am62p-sk-binman.dtsi create mode 100644 arch/arm/dts/k3-am62p-wakeup.dtsi create mode 100644 arch/arm/dts/k3-am62p.dtsi create mode 100644 arch/arm/dts/k3-am62p5-r5-sk.dts create mode 100644 arch/arm/dts/k3-am62p5-sk-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am62p5-sk.dts create mode 100644 arch/arm/dts/k3-am62p5.dtsi create mode 100644 arch/arm/mach-k3/am62p5_init.c create mode 100644 arch/arm/mach-k3/am62px/Makefile create mode 100644 arch/arm/mach-k3/am62px/clk-data.c create mode 100644 arch/arm/mach-k3/am62px/dev-data.c create mode 100644 arch/arm/mach-k3/include/mach/am62p_hardware.h create mode 100644 arch/arm/mach-k3/include/mach/am62p_spl.h create mode 100644 board/ti/am62px/Kconfig create mode 100644 board/ti/am62px/MAINTAINERS create mode 100644 board/ti/am62px/Makefile create mode 100644 board/ti/am62px/am62px.env create mode 100644 board/ti/am62px/board-cfg.yaml create mode 100644 board/ti/am62px/evm.c create mode 100644 board/ti/am62px/pm-cfg.yaml create mode 100644 board/ti/am62px/rm-cfg.yaml create mode 100644 board/ti/am62px/sec-cfg.yaml create mode 100644 board/ti/am62px/tifs-rm-cfg.yaml create mode 100644 configs/am62px_evm_a53_defconfig create mode 100644 configs/am62px_evm_r5_defconfig create mode 100644 doc/board/ti/am62px_sk.rst create mode 100644 include/configs/am62px_evm.h base-commit: 86700279645921fb2c28c41711deb7d7ed75bc29 -- 2.42.0

3 16

[PATCH] arm: mvebu: AC5/AC5X: Disable SMBIOS
by Chris Packham 16 Oct '23

16 Oct '23

The RD-AC5X doesn't make use of EFI or SMBIOS. Recently we started seeing boot failures such as WARNING: SMBIOS table_address overflow 27f60f020 Failed to write SMBIOS table initcall failed at event 10/(unknown) (err=-22) ### ERROR ### Please RESET the board ### The error is because the physical address of the RAM on the AC5X SoC is above the 32GiB boundary. As we don't need SMBIOS or EFI this can be safely disabled. Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- This probably should have been part of the series I sent as https://lore.kernel.org/u-boot/20231003035800.2626121-1-judge.packham@gmail… but I didn't have the RD-AC5X board at the time. There is another issue that's stopping the RD-AC5X board from booting with current master but with the suspect commit reverted you can see the same SMBIOS issue I was seeing on the x240. configs/mvebu_ac5_rd_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mvebu_ac5_rd_defconfig b/configs/mvebu_ac5_rd_defconfig index dbf1e3136cdf..e8fa22b648be 100644 --- a/configs/mvebu_ac5_rd_defconfig +++ b/configs/mvebu_ac5_rd_defconfig @@ -85,3 +85,4 @@ CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y +# CONFIG_SMBIOS is not set -- 2.42.0

2 2

[PATCH 0/2] arm: mvebu: clearfog: support additional ddr
by Josua Mayer 16 Oct '23

16 Oct '23

This series adds support for additional memory configuration that were been produced in the past - most notably a dual-channel configuration with two 512MB modules. Josua Mayer (2): arm: mvebu: clearfog: read number of ddr channels from tlv data arm: mvebu: clearfog: support 512MB memory size from tlv eeprom board/solidrun/clearfog/clearfog.c | 17 ++++++++++++++++- board/solidrun/common/tlv_data.c | 7 ++++++- board/solidrun/common/tlv_data.h | 1 + 3 files changed, 23 insertions(+), 2 deletions(-) -- 2.35.3

2 6

[PATCH] arm: mvebu: Enable bootstd for Thecus N2350 board
by Tony Dinh 16 Oct '23

16 Oct '23

Enable bootstd for Thecus N2350 board, and remove distroboot. Signed-off-by: Tony Dinh <mibodhi(a)gmail.com> --- configs/n2350_defconfig | 3 ++- include/configs/n2350.h | 12 +----------- 2 files changed, 3 insertions(+), 12 deletions(-) diff --git a/configs/n2350_defconfig b/configs/n2350_defconfig index 109f0e10e9..07135742d3 100644 --- a/configs/n2350_defconfig +++ b/configs/n2350_defconfig @@ -29,7 +29,8 @@ CONFIG_ENV_ADDR=0x100000 CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y CONFIG_BOOTDELAY=10 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/include/configs/n2350.h b/include/configs/n2350.h index 92b2270236..d8a9814d3e 100644 --- a/include/configs/n2350.h +++ b/include/configs/n2350.h @@ -20,15 +20,8 @@ */ #include "mv-common.h" -/* Include the common distro boot environment */ #ifndef CONFIG_SPL_BUILD -#define BOOT_TARGET_DEVICES(func) \ - func(SCSI, scsi, 0) \ - func(USB, usb, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - #define KERNEL_ADDR_R __stringify(0x1000000) #define FDT_ADDR_R __stringify(0x2000000) #define RAMDISK_ADDR_R __stringify(0x2200000) @@ -42,14 +35,11 @@ "scriptaddr=" SCRIPT_ADDR_R "\0" \ "pxefile_addr_r=" PXEFILE_ADDR_R "\0" -#include <config_distro_bootcmd.h> - #define CFG_EXTRA_ENV_SETTINGS \ RELOCATION_LIMITS_ENV_SETTINGS \ LOAD_ADDRESS_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ - "console=ttyS0,115200\0" \ - BOOTENV + "console=ttyS0,115200\0" #endif /* CONFIG_SPL_BUILD */ -- 2.39.2

2 2

[PATCH] arm: mvebu: Enable bootstd for Synology DS116 board
by Tony Dinh 16 Oct '23

16 Oct '23

Enable bootstd for Synology DS116 board, and remove distroboot. Signed-off-by: Tony Dinh <mibodhi(a)gmail.com> --- configs/ds116_defconfig | 3 ++- include/configs/ds116.h | 12 +----------- 2 files changed, 3 insertions(+), 12 deletions(-) diff --git a/configs/ds116_defconfig b/configs/ds116_defconfig index 0cd546c223..2437be73cd 100644 --- a/configs/ds116_defconfig +++ b/configs/ds116_defconfig @@ -28,7 +28,8 @@ CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_PCI=y CONFIG_DEBUG_UART=y CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y CONFIG_BOOTDELAY=10 CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/include/configs/ds116.h b/include/configs/ds116.h index 031f4f6afc..0883ec4d53 100644 --- a/include/configs/ds116.h +++ b/include/configs/ds116.h @@ -20,15 +20,8 @@ */ #include "mv-common.h" -/* Include the common distro boot environment */ #ifndef CONFIG_SPL_BUILD -#define BOOT_TARGET_DEVICES(func) \ - func(USB, usb, 0) \ - func(SCSI, scsi, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - #define KERNEL_ADDR_R __stringify(0x1000000) #define FDT_ADDR_R __stringify(0x2000000) #define RAMDISK_ADDR_R __stringify(0x2200000) @@ -42,14 +35,11 @@ "scriptaddr=" SCRIPT_ADDR_R "\0" \ "pxefile_addr_r=" PXEFILE_ADDR_R "\0" -#include <config_distro_bootcmd.h> - #define CFG_EXTRA_ENV_SETTINGS \ RELOCATION_LIMITS_ENV_SETTINGS \ LOAD_ADDRESS_ENV_SETTINGS \ "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ - "console=ttyS0,115200\0" \ - BOOTENV + "console=ttyS0,115200\0" #endif /* CONFIG_SPL_BUILD */ -- 2.39.2

2 2

[PATCH 1/2] arm: mvebu: x240: Disable SMBIOS
by Chris Packham 16 Oct '23

16 Oct '23

The x240 doesn't make use of EFI or SMBIOS. Recently we started seeing boot failures such as WARNING: SMBIOS table_address overflow 23f60c020 Failed to write SMBIOS table initcall failed at event 10/(unknown) (err=-22) ### ERROR ### Please RESET the board ### The error is because the physical address of the RAM on the AC5X SoC is above the 32GiB boundary. As we don't need SMBIOS or EFI this can be safely disabled. Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- configs/x240_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/x240_defconfig b/configs/x240_defconfig index 7d2b8603e6f4..0d5a19df25aa 100644 --- a/configs/x240_defconfig +++ b/configs/x240_defconfig @@ -84,3 +84,4 @@ CONFIG_USB_ETHER_MCS7830=y CONFIG_USB_ETHER_RTL8152=y CONFIG_USB_ETHER_SMSC95XX=y # CONFIG_FAT_WRITE is not set +# CONFIG_SMBIOS is not set -- 2.42.0

2 5

[PATCH] arm: mvebu: sata_mv: Add bootstd hook to enable sata_bootdev
by Tony Dinh 16 Oct '23

16 Oct '23

Add hook in sata_mv probe to enable bootstd bootdev. Note: bootdev_setup_for_sibling_blk() invocation is a noop if bootsd is not enabled for ahci sata yet. Signed-off-by: Tony Dinh <mibodhi(a)gmail.com> --- drivers/ata/sata_mv.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index 18c7a66db1..55a5365b5a 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c @@ -34,6 +34,7 @@ #include <common.h> #include <ahci.h> #include <blk.h> +#include <bootdev.h> #include <cpu_func.h> #include <dm.h> #include <log.h> @@ -1104,6 +1105,12 @@ static int sata_mv_probe(struct udevice *dev) /* TODO: undo create */ continue; + ret = bootdev_setup_for_sibling_blk(blk, "sata_bootdev"); + if (ret) { + printf("%s: Failed to create bootdev\n", __func__); + continue; + } + /* If we got here, the current SATA port was probed * successfully, so set the probe status to successful. */ @@ -1116,7 +1123,6 @@ static int sata_mv_probe(struct udevice *dev) static int sata_mv_scan(struct udevice *dev) { /* Nothing to do here */ - return 0; } -- 2.39.2

3 6

[PATCH] arm: kirkwood: Add support for ZyXEL NSA325 board
by Tony Dinh 16 Oct '23

16 Oct '23

ZyXEL NSA325 specifications: Marvell Kirkwood 88F6282 SoC 1.6 GHz CPU 1x GBE LAN port (Marvell MV88E1318) 512 MB RAM 128 MB Eon NAND, SLC I2C 1x USB 3.0 (on PCIe bus) 2x USB 2.0 2x SATA (hot swap slots) Serial console Signed-off-by: Tony Dinh <mibodhi(a)gmail.com> --- arch/arm/dts/Makefile | 1 + arch/arm/dts/kirkwood-6282.dtsi | 161 ++++++++++++++++ arch/arm/dts/kirkwood-nsa325.dts | 231 +++++++++++++++++++++++ arch/arm/dts/kirkwood-nsa3x0-common.dtsi | 157 +++++++++++++++ arch/arm/mach-kirkwood/Kconfig | 7 + board/zyxel/nsa325/Kconfig | 12 ++ board/zyxel/nsa325/MAINTAINERS | 9 + board/zyxel/nsa325/Makefile | 11 ++ board/zyxel/nsa325/kwbimage.cfg | 55 ++++++ board/zyxel/nsa325/nsa325.c | 196 +++++++++++++++++++ configs/nsa325_defconfig | 81 ++++++++ include/configs/nsa325.h | 37 ++++ 12 files changed, 958 insertions(+) create mode 100644 arch/arm/dts/kirkwood-6282.dtsi create mode 100644 arch/arm/dts/kirkwood-nsa325.dts create mode 100644 arch/arm/dts/kirkwood-nsa3x0-common.dtsi create mode 100644 board/zyxel/nsa325/Kconfig create mode 100644 board/zyxel/nsa325/MAINTAINERS create mode 100644 board/zyxel/nsa325/Makefile create mode 100644 board/zyxel/nsa325/kwbimage.cfg create mode 100644 board/zyxel/nsa325/nsa325.c create mode 100644 configs/nsa325_defconfig create mode 100644 include/configs/nsa325.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 85fd5b1157..b9fc46544f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -66,6 +66,7 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += \ kirkwood-ns2max.dtb \ kirkwood-ns2mini.dtb \ kirkwood-nsa310s.dtb \ + kirkwood-nsa325.dtb \ kirkwood-openrd-base.dtb \ kirkwood-openrd-client.dtb \ kirkwood-openrd-ultimate.dtb \ diff --git a/arch/arm/dts/kirkwood-6282.dtsi b/arch/arm/dts/kirkwood-6282.dtsi new file mode 100644 index 0000000000..e732c501ea --- /dev/null +++ b/arch/arm/dts/kirkwood-6282.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0 +/ { + mbus@f1000000 { + pciec: pcie@82000000 { + compatible = "marvell,kirkwood-pcie"; + status = "disabled"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + + bus-range = <0x00 0xff>; + + ranges = + <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 + 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 + 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 + 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ + 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ + 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */ + 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>; + + pcie0: pcie@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 + 0x81000000 0 0 0x81000000 0x1 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-names = "intx", "error"; + interrupts = <9>, <44>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + marvell,pcie-port = <0>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 2>; + status = "disabled"; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + pcie1: pcie@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>; + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 + 0x81000000 0 0 0x81000000 0x2 0 1 0>; + bus-range = <0x00 0xff>; + interrupt-names = "intx", "error"; + interrupts = <10>, <45>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie1_intc 0>, + <0 0 0 2 &pcie1_intc 1>, + <0 0 0 3 &pcie1_intc 2>, + <0 0 0 4 &pcie1_intc 3>; + marvell,pcie-port = <1>; + marvell,pcie-lane = <0>; + clocks = <&gate_clk 18>; + status = "disabled"; + + pcie1_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + }; + }; + ocp@f1000000 { + + pinctrl: pin-controller@10000 { + compatible = "marvell,88f6282-pinctrl"; + + pmx_sata0: pmx-sata0 { + marvell,pins = "mpp5", "mpp21", "mpp23"; + marvell,function = "sata0"; + }; + pmx_sata1: pmx-sata1 { + marvell,pins = "mpp4", "mpp20", "mpp22"; + marvell,function = "sata1"; + }; + + /* + * Default I2C1 pinctrl setting on mpp36/mpp37, + * overwrite marvell,pins on board level if required. + */ + pmx_twsi1: pmx-twsi1 { + marvell,pins = "mpp36", "mpp37"; + marvell,function = "twsi1"; + }; + + pmx_sdio: pmx-sdio { + marvell,pins = "mpp12", "mpp13", "mpp14", + "mpp15", "mpp16", "mpp17"; + marvell,function = "sdio"; + }; + }; + + thermal: thermal@10078 { + compatible = "marvell,kirkwood-thermal"; + reg = <0x10078 0x4>; + status = "okay"; + }; + + rtc: rtc@10300 { + compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = <53>; + clocks = <&gate_clk 7>; + }; + + i2c1: i2c@11100 { + compatible = "marvell,mv64xxx-i2c"; + reg = <0x11100 0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <32>; + clock-frequency = <100000>; + clocks = <&gate_clk 7>; + pinctrl-0 = <&pmx_twsi1>; + pinctrl-names = "default"; + status = "disabled"; + }; + + sata: sata@80000 { + compatible = "marvell,orion-sata"; + reg = <0x80000 0x5000>; + interrupts = <21>; + clocks = <&gate_clk 14>, <&gate_clk 15>; + clock-names = "0", "1"; + phys = <&sata_phy0>, <&sata_phy1>; + phy-names = "port0", "port1"; + status = "disabled"; + }; + + sdio: mvsdio@90000 { + compatible = "marvell,orion-sdio"; + reg = <0x90000 0x200>; + interrupts = <28>; + clocks = <&gate_clk 4>; + pinctrl-0 = <&pmx_sdio>; + pinctrl-names = "default"; + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + cap-mmc-highspeed; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/dts/kirkwood-nsa325.dts b/arch/arm/dts/kirkwood-nsa325.dts new file mode 100644 index 0000000000..efc57cfa41 --- /dev/null +++ b/arch/arm/dts/kirkwood-nsa325.dts @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Device tree file for the Zyxel NSA 325 NAS box. + * + * Copyright (c) 2015, Hans Ulli Kroll <ulli.kroll(a)googlemail.com> + * + * + * Based upon the board setup file created by Peter Schildmann + */ + +/dts-v1/; + +#include "kirkwood-nsa3x0-common.dtsi" + +/ { + model = "ZyXEL NSA325"; + compatible = "zyxel,nsa325", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &uart0; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-names = "default"; + + pmx_led_hdd2_green: pmx-led-hdd2-green { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + + pmx_led_hdd2_red: pmx-led-hdd2-red { + marvell,pins = "mpp13"; + marvell,function = "gpio"; + }; + + pmx_mcu_data: pmx-mcu-data { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + pmx_led_usb_green: pmx-led-usb-green { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + pmx_mcu_clk: pmx-mcu-clk { + marvell,pins = "mpp16"; + marvell,function = "gpio"; + }; + + pmx_mcu_act: pmx-mcu-act { + marvell,pins = "mpp17"; + marvell,function = "gpio"; + }; + + pmx_led_sys_green: pmx-led-sys-green { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + pmx_led_sys_orange: pmx-led-sys-orange { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + pmx_led_hdd1_green: pmx-led-hdd1-green { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + pmx_led_hdd1_red: pmx-led-hdd1-red { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + pmx_htp: pmx-htp { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + + /* + * Buzzer needs to be switched at around 1kHz so is + * not compatible with the gpio-beeper driver. + */ + pmx_buzzer: pmx-buzzer { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + pmx_vid_b1: pmx-vid-b1 { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + pmx_power_resume_data: pmx-power-resume-data { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + pmx_power_resume_clk: pmx-power-resume-clk { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + + pmx_pwr_sata1: pmx-pwr-sata1 { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + }; + + /* This board uses the pcf8563 RTC instead of the SoC RTC */ + rtc@10300 { + status = "disabled"; + }; + + i2c@11000 { + status = "okay"; + + pcf8563: pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_pwr_sata1>; + pinctrl-names = "default"; + + usb0_power: regulator@1 { + enable-active-high; + }; + + sata1_power: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red + &pmx_led_usb_green + &pmx_led_sys_green &pmx_led_sys_orange + &pmx_led_copy_green &pmx_led_copy_red + &pmx_led_hdd1_green &pmx_led_hdd1_red>; + pinctrl-names = "default"; + + green-sys { + label = "nsa325:green:sys"; + gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; + }; + orange-sys { + label = "nsa325:orange:sys"; + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; + }; + green-hdd1 { + label = "nsa325:green:hdd1"; + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + }; + red-hdd1 { + label = "nsa325:red:hdd1"; + gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + green-hdd2 { + label = "nsa325:green:hdd2"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + red-hdd2 { + label = "nsa325:red:hdd2"; + gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; + green-usb { + label = "nsa325:green:usb"; + gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + }; + green-copy { + label = "nsa325:green:copy"; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; + red-copy { + label = "nsa325:red:copy"; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + }; + + /* The following pins are currently not assigned to a driver, + some of them should be configured as inputs. + pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act + &pmx_htp &pmx_vid_b1 + &pmx_power_resume_data &pmx_power_resume_clk>; */ + }; + +}; + +&mdio { + status = "okay"; + ethphy0: ethernet-phy@1 { + reg = <1>; + }; +}; + +&eth0 { + status = "okay"; + ethernet0-port@0 { + phy-handle = <&ethphy0>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/dts/kirkwood-nsa3x0-common.dtsi b/arch/arm/dts/kirkwood-nsa3x0-common.dtsi new file mode 100644 index 0000000000..a21c50d44a --- /dev/null +++ b/arch/arm/dts/kirkwood-nsa3x0-common.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "ZyXEL NSA310"; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + + pmx_usb_power: pmx-usb-power { + marvell,pins = "mpp21"; + marvell,function = "gpio"; + }; + + pmx_pwr_off: pmx-pwr-off { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + + pmx_btn_reset: pmx-btn-reset { + marvell,pins = "mpp36"; + marvell,function = "gpio"; + }; + + pmx_btn_copy: pmx-btn-copy { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + + pmx_btn_power: pmx-btn-power { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + pmx_led_copy_green: pmx-led-copy-green { + marvell,pins = "mpp39"; + marvell,function = "gpio"; + }; + + pmx_led_copy_red: pmx-led-copy-red { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + }; + + serial@12000 { + status = "okay"; + }; + + sata@80000 { + status = "okay"; + nr-ports = <2>; + }; + }; + + gpio_poweroff { + compatible = "gpio-poweroff"; + pinctrl-0 = <&pmx_pwr_off>; + pinctrl-names = "default"; + gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; + pinctrl-names = "default"; + + power { + label = "Power Button"; + linux,code = <KEY_POWER>; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + copy { + label = "Copy Button"; + linux,code = <KEY_COPY>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; + reset { + label = "Reset Button"; + linux,code = <KEY_RESTART>; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; + }; + + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pmx_usb_power>; + pinctrl-names = "default"; + + usb0_power: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&nand { + status = "okay"; + chip-delay = <35>; + + partition@0 { + label = "uboot"; + reg = <0x0000000 0x0100000>; + }; + partition@100000 { + label = "uboot_env"; + reg = <0x0100000 0x0080000>; + }; + partition@180000 { + label = "key_store"; + reg = <0x0180000 0x0080000>; + }; + partition@200000 { + label = "info"; + reg = <0x0200000 0x0080000>; + }; + partition@280000 { + label = "etc"; + reg = <0x0280000 0x0a00000>; + }; + partition@c80000 { + label = "kernel_1"; + reg = <0x0c80000 0x0a00000>; + }; + partition@1680000 { + label = "rootfs1"; + reg = <0x1680000 0x2fc0000>; + }; + partition@4640000 { + label = "kernel_2"; + reg = <0x4640000 0x0a00000>; + }; + partition@5040000 { + label = "rootfs2"; + reg = <0x5040000 0x2fc0000>; + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 54027ccb0e..c2fff84a68 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -133,6 +133,12 @@ config TARGET_NSA310S select KW88F6192 select KIRKWOOD_COMMON +config TARGET_NSA325 + bool "ZyXEL NSA325" + select FEROCEON_88FR131 + select KW88F6281 + select KIRKWOOD_COMMON + config TARGET_SBx81LIFKW bool "Allied Telesis SBx81GS24/SBx81GT40/SBx81XS6/SBx81XS16" select FEROCEON_88FR131 @@ -177,6 +183,7 @@ source "board/Seagate/dockstar/Kconfig" source "board/Seagate/goflexhome/Kconfig" source "board/Seagate/nas220/Kconfig" source "board/zyxel/nsa310s/Kconfig" +source "board/zyxel/nsa325/Kconfig" source "board/alliedtelesis/SBx81LIFKW/Kconfig" source "board/alliedtelesis/SBx81LIFXCAT/Kconfig" diff --git a/board/zyxel/nsa325/Kconfig b/board/zyxel/nsa325/Kconfig new file mode 100644 index 0000000000..1fe5ead76e --- /dev/null +++ b/board/zyxel/nsa325/Kconfig @@ -0,0 +1,12 @@ +if TARGET_NSA325 + +config SYS_BOARD + default "nsa325" + +config SYS_VENDOR + default "zyxel" + +config SYS_CONFIG_NAME + default "nsa325" + +endif diff --git a/board/zyxel/nsa325/MAINTAINERS b/board/zyxel/nsa325/MAINTAINERS new file mode 100644 index 0000000000..013cb84b99 --- /dev/null +++ b/board/zyxel/nsa325/MAINTAINERS @@ -0,0 +1,9 @@ +NSA325 BOARD +M: Tony Dinh <mibodhi(a)gmail.com> +S: Maintained +F: arch/arm/dts/kirkwood-6282.dtsi +F: arch/arm/dts/kirkwood-nsa325.dts +F: arch/arm/dts/kirkwood-nsa3x0-common.dtsi +F: board/zyxel/nsa325/ +F: include/configs/nsa325.h +F: configs/nsa325_defconfig diff --git a/board/zyxel/nsa325/Makefile b/board/zyxel/nsa325/Makefile new file mode 100644 index 0000000000..2887ba2d13 --- /dev/null +++ b/board/zyxel/nsa325/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2015-2023 Tony Dinh <mibodhi(a)gmail.com> +# +# Based on +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# + +obj-y := nsa325.o diff --git a/board/zyxel/nsa325/kwbimage.cfg b/board/zyxel/nsa325/kwbimage.cfg new file mode 100644 index 0000000000..a497300873 --- /dev/null +++ b/board/zyxel/nsa325/kwbimage.cfg @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015-2023 Tony Dinh <mibodhi(a)gmail.com> +# +# Extracted from Zyxel GPL source for u-boot-1.1.4_NSA325v2 +# +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization +DATA 0xFFD01400 0x4301503E # DDR Configuration register +DATA 0xFFD01404 0xB9843000 # DDR Controller Control Low +DATA 0xFFD01408 0x33137777 # DDR Timing (Low) +DATA 0xFFD0140C 0x16000C55 # DDR Timing (High) +DATA 0xFFD01410 0x04000000 # DDR Address Control +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +DATA 0xFFD01418 0x00000000 # DDR Operation +DATA 0xFFD0141C 0x00000672 # DDR Mode +DATA 0xFFD01420 0x00000004 # DDR Extended Mode +DATA 0xFFD01424 0x0000F14F # DDR Controller Control High +DATA 0xFFD01428 0x000D6720 # DDR3 ODT Read Timing +DATA 0xFFD0147C 0x0000B571 # DDR2 ODT Write Timing +DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size +DATA 0xFFD01508 0x20000000 # CS[1]n Base address to 512Mb +DATA 0xFFD0150C 0x1FFFFFF4 # CS[1]n Size 512Mb Window enabled for CS1 +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled +DATA 0xFFD01494 0x00120000 # DDR ODT Control (Low) +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +DATA 0xFFD0149C 0x0000E803 # CPU ODT Control + +DATA 0xFFD015D0 0x00000630 +DATA 0xFFD015D4 0x00000046 +DATA 0xFFD015D8 0x00000008 +DATA 0xFFD015DC 0x00000000 +DATA 0xFFD015E0 0x00000023 +DATA 0xFFD015E4 0x00203C18 +DATA 0xFFD01620 0x00384800 +DATA 0xFFD01480 0x00000001 +DATA 0xFFD20134 0x66666666 +DATA 0xFFD20138 0x00066666 + +DATA 0xFFD10100 0x00004000 # stop the watchdog +DATA 0xFFD10104 0xFFFFBFFF + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/zyxel/nsa325/nsa325.c b/board/zyxel/nsa325/nsa325.c new file mode 100644 index 0000000000..f5f63ee5d3 --- /dev/null +++ b/board/zyxel/nsa325/nsa325.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2014-2023 Tony Dinh <mibodhi(a)gmail.com> + * + * Based on + * Copyright (C) 2014 Jason Plum <jplum(a)archlinuxarm.org> + * + * Based on nsa320.c originall written by + * Copyright (C) 2012 Peter Schildmann <linux(a)schildmann.info> + * + * Based on guruplug.c originally written by + * Siddarth Gore <gores(a)marvell.com> + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + */ + +#include <common.h> +#include <asm/arch/soc.h> +#include <asm/arch/mpp.h> +#include <netdev.h> +#include <asm/arch/cpu.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/gpio.h> +#include <asm/mach-types.h> +#include <bootstage.h> +#include <command.h> +#include <init.h> +#include <linux/bitops.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* low GPIO's */ +#define HDD2_GREEN_LED BIT(12) +#define HDD2_RED_LED BIT(13) +#define USB_GREEN_LED BIT(15) +#define USB_POWER BIT(21) +#define SYS_GREEN_LED BIT(28) +#define SYS_ORANGE_LED BIT(29) + +#define PIN_USB_GREEN_LED 15 +#define PIN_USB_POWER 21 + +#define NSA325_OE_LOW (~(HDD2_GREEN_LED | HDD2_RED_LED | \ + USB_GREEN_LED | USB_POWER | \ + SYS_GREEN_LED | SYS_ORANGE_LED)) +#define NSA325_VAL_LOW (SYS_GREEN_LED | USB_POWER) + +/* high GPIO's */ +#define COPY_GREEN_LED BIT(7) +#define COPY_RED_LED BIT(8) +#define HDD1_GREEN_LED BIT(9) +#define HDD1_RED_LED BIT(10) +#define HDD2_POWER BIT(15) +#define WATCHDOG_SIGNAL BIT(14) + +#define NSA325_OE_HIGH (~(COPY_GREEN_LED | COPY_RED_LED | \ + HDD1_GREEN_LED | HDD1_RED_LED | HDD2_POWER | WATCHDOG_SIGNAL)) +#define NSA325_VAL_HIGH (WATCHDOG_SIGNAL | HDD2_POWER) + +#define BTN_POWER 46 +#define BTN_RESET 36 +#define BTN_COPY 37 + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + mvebu_config_gpio(NSA325_VAL_LOW, NSA325_VAL_HIGH, + NSA325_OE_LOW, NSA325_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + /* (all LEDs & power off active high) */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, /* PCF8563 RTC chip */ + MPP9_TW_SCK, /* connected to TWSI */ + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_GPO, /* HDD2 LED (green) */ + MPP13_GPIO, /* HDD2 LED (red) */ + MPP14_GPIO, /* MCU DATA pin (in) */ + MPP15_GPIO, /* USB LED (green) */ + MPP16_GPIO, /* MCU CLK pin (out) */ + MPP17_GPIO, /* MCU ACT pin (out) */ + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GPIO, + MPP21_GPIO, /* USB power */ + MPP22_GPIO, + MPP23_GPIO, + MPP24_GPIO, + MPP25_GPIO, + MPP26_GPIO, + MPP27_GPIO, + MPP28_GPIO, /* SYS LED (green) */ + MPP29_GPIO, /* SYS LED (orange) */ + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, /* reset button */ + MPP37_GPIO, /* copy button */ + MPP38_GPIO, /* VID B0 */ + MPP39_GPIO, /* COPY LED (green) */ + MPP40_GPIO, /* COPY LED (red) */ + MPP41_GPIO, /* HDD1 LED (green) */ + MPP42_GPIO, /* HDD1 LED (red) */ + MPP43_GPIO, /* HTP pin */ + MPP44_GPIO, /* buzzer */ + MPP45_GPIO, /* VID B1 */ + MPP46_GPIO, /* power button */ + MPP47_GPIO, /* HDD2 power */ + MPP48_GPIO, /* power off */ + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + return 0; +} + +int board_eth_init(struct bd_info *bis) +{ + return cpu_eth_init(bis); +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +int board_late_init(void) +{ + /* Do late init to ensure successful enumeration of XHCI devices */ + pci_init(); + return 0; +} + +#if defined(CONFIG_SHOW_BOOT_PROGRESS) +void show_boot_progress(int val) +{ + struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE; + u32 dout0 = readl(&gpio0->dout); + u32 blen0 = readl(&gpio0->blink_en); + + struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE; + u32 dout1 = readl(&gpio1->dout); + u32 blen1 = readl(&gpio1->blink_en); + + switch (val) { + case BOOTSTAGE_ID_DECOMP_IMAGE: + writel(blen0 & ~(SYS_GREEN_LED | SYS_ORANGE_LED), &gpio0->blink_en); + writel((dout0 & ~SYS_GREEN_LED) | SYS_ORANGE_LED, &gpio0->dout); + break; + case BOOTSTAGE_ID_RUN_OS: + writel(dout0 & ~SYS_ORANGE_LED, &gpio0->dout); + writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en); + break; + case BOOTSTAGE_ID_NET_START: + writel(dout1 & ~COPY_RED_LED, &gpio1->dout); + writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en); + break; + case BOOTSTAGE_ID_NET_LOADED: + writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en); + writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout); + break; + case -BOOTSTAGE_ID_NET_NETLOOP_OK: + case -BOOTSTAGE_ID_NET_LOADED: + writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout); + writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en); + break; + default: + if (val < 0) { + /* error */ + printf("Error occurred, error code = %d\n", -val); + writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout); + writel(blen0 | SYS_ORANGE_LED, &gpio0->blink_en); + } + break; + } +} +#endif /* CONFIG_SHOW_BOOT_PROGRESS */ diff --git a/configs/nsa325_defconfig b/configs/nsa325_defconfig new file mode 100644 index 0000000000..d5fe9ca099 --- /dev/null +++ b/configs/nsa325_defconfig @@ -0,0 +1,81 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_DCACHE_OFF=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_SYS_THUMB_BUILD=y +CONFIG_ARCH_KIRKWOOD=y +CONFIG_SUPPORT_PASSING_ATAGS=y +CONFIG_CMDLINE_TAG=y +CONFIG_INITRD_TAG=y +CONFIG_SYS_KWD_CONFIG="board/zyxel/nsa325/kwbimage.cfg" +CONFIG_TEXT_BASE=0x600000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_NSA325=y +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0xC0000 +CONFIG_DEFAULT_DEVICE_TREE="kirkwood-nsa325" +CONFIG_SYS_PROMPT="NSA325> " +CONFIG_IDENT_STRING="\nZyXEL NSA325 2-Bay Power Media Server" +CONFIG_SYS_LOAD_ADDR=0x800000 +CONFIG_PCI=y +CONFIG_LTO=y +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTSTD_BOOTCOMMAND=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTSTAGE=y +CONFIG_SHOW_BOOT_PROGRESS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_PREBOOT=y +CONFIG_BOARD_LATE_INIT=y +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SATA=y +CONFIG_CMD_USB=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_DNS=y +# CONFIG_CMD_BLOCK_CACHE is not set +CONFIG_CMD_JFFS2=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" +CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x100000(uboot),0x80000(stock_uboot_env),0x80000(key_store),0x80000(info),0xA00000(etc),0xA00000(kernel_1),0x2FC0000(rootfs1),0xA00000(kernel_2),0x2FC0000(rootfs2)" +CONFIG_CMD_UBI=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_VERSION_VARIABLE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y +# CONFIG_DM_WARN is not set +CONFIG_SATA_MV=y +CONFIG_SYS_SATA_MAX_DEVICE=2 +CONFIG_LBA48=y +CONFIG_SYS_64BIT_LBA=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_PHY_MARVELL=y +CONFIG_MVGBE=y +CONFIG_MII=y +CONFIG_PCI_MVEBU=y +CONFIG_DM_RTC=y +CONFIG_RTC_PCF8563=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_NAND=y +CONFIG_UBIFS_SILENCE_MSG=y diff --git a/include/configs/nsa325.h b/include/configs/nsa325.h new file mode 100644 index 0000000000..00a148c6ae --- /dev/null +++ b/include/configs/nsa325.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2016-2023 Tony Dinh <mibodhi(a)gmail.com> + * (C) Copyright 2014 Jason Plum <jplum(a)archlinuxarm.org> + * + * Based on + * Copyright (C) 2012 Peter Schildmann <linux(a)schildmann.info> + * + * Based on guruplug.h originally written by + * Siddarth Gore <gores(a)marvell.com> + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + */ + +#ifndef _CONFIG_NSA325_H +#define _CONFIG_NSA325_H + +#include "mv-common.h" + +#define KERNEL_ADDR_R __stringify(0x800000) +#define FDT_ADDR_R __stringify(0x2c00000) +#define RAMDISK_ADDR_R __stringify(0x01100000) +#define SCRIPT_ADDR_R __stringify(0x200000) + +#define LOAD_ADDRESS_ENV_SETTINGS \ + "kernel_addr_r=" KERNEL_ADDR_R "\0" \ + "fdt_addr_r=" FDT_ADDR_R "\0" \ + "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ + "scriptaddr=" SCRIPT_ADDR_R "\0" + +#define CFG_EXTRA_ENV_SETTINGS \ + LOAD_ADDRESS_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "console=ttyS0,115200\0" + +#endif /* _CONFIG_NSA325_H */ -- 2.39.2

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[PATCH 1/2] ARM64: dts: marvell: cn9310: Use appropriate label for spi1 pins
by Chris Packham 16 Oct '23

16 Oct '23

The CN9130-DB uses the SPI1 interface but had the pinctrl node labelled as "cp0_spi0_pins". Use the label "cp0_spi1_pins" and update the node name to "cp0-spi-pins-1" to avoid confusion with the pinctrl options for SPI0. Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- arch/arm/dts/cn9130-db.dtsi | 2 +- arch/arm/dts/cn9130.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/cn9130-db.dtsi b/arch/arm/dts/cn9130-db.dtsi index 1b28732ee752..4b21ff46d507 100644 --- a/arch/arm/dts/cn9130-db.dtsi +++ b/arch/arm/dts/cn9130-db.dtsi @@ -183,7 +183,7 @@ /* U55 */ &cp0_spi1 { pinctrl-names = "default"; - pinctrl-0 = <&cp0_spi0_pins>; + pinctrl-0 = <&cp0_spi1_pins>; reg = <0x700680 0x50>, /* control */ <0x2000000 0x1000000>, /* CS0 */ <0 0xffffffff>, /* CS1 */ diff --git a/arch/arm/dts/cn9130.dtsi b/arch/arm/dts/cn9130.dtsi index 68b767a70639..efcb2e906b91 100644 --- a/arch/arm/dts/cn9130.dtsi +++ b/arch/arm/dts/cn9130.dtsi @@ -66,7 +66,7 @@ marvell,pins = < 56 57 58 59 60 61 >; marvell,function = <14>; }; - cp0_spi0_pins: cp0-spi-pins-0 { + cp0_spi1_pins: cp0-spi-pins-1 { marvell,pins = < 13 14 15 16 >; marvell,function = <3>; }; -- 2.41.0

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[PATCH] kirkwood: dns325: Enable 2nd harddrive
by Stefan Roese 16 Oct '23

16 Oct '23

The 2nd HD is not enabled in U-Boot on the D-Link DNS325. This patch sets the responsible GPIO to high, enabling the drive. Suggested-by: Peter Granilla Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Tom Rini <trini(a)konsulko.com> --- board/d-link/dns325/dns325.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/d-link/dns325/dns325.c b/board/d-link/dns325/dns325.c index 055783f63ada..8ebfe4c60189 100644 --- a/board/d-link/dns325/dns325.c +++ b/board/d-link/dns325/dns325.c @@ -89,6 +89,7 @@ int board_early_init_f(void) kw_gpio_set_blink(DNS325_GPIO_LED_POWER , 1); kw_gpio_set_value(DNS325_GPIO_SATA0_EN , 1); + kw_gpio_set_value(DNS325_GPIO_SATA1_EN , 1); return 0; } -- 2.41.0

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