September 2022 - U-Boot

[PATCH 0/3] sunxi: FEL boot fixes
by Andre Przywara 08 Jan '23

08 Jan '23

While investigating a FEL boot failure on the OrangePi Zero 2 board (with an H616 SoC), I stared at our FEL code and found some issues, which this series fixes. Unfortunately those didn't fix the H616 problem, but they are worth having anyway. For the records on the FEL failure: with certain H616 DRAM parameters, newer GCCs (starting with GCC 11, GCC 10 is fine) generate an SPL binary that doesn't properly return to the BootROM after the SPL code has finished. This does not occur on other H616 boards using different DRAM parameters. Staring at the disassemblies from the different compiler versions for a while didn't show anything obvious, the best theory so far is that it's due to a subtle timing issue in the DRAM initialisation code. Inserting a "udelay(0);" at the beginning of mctl_phy_read_calibration() seems to avoid the problem, but is obviously not a proper fix. I will keep looking. However the issues addressed in this series should be fixed, regardless. Cheers, Andre Andre Przywara (3): sunxi: armv8: fel: load only 32-bit values sunxi: h616: lower SPL stack address to avoid BROM data sunxi: fel: drop redundant "control register" save/restore arch/arm/cpu/armv7/sunxi/fel_utils.S | 4 ---- arch/arm/cpu/armv8/fel_utils.S | 8 ++++---- arch/arm/mach-sunxi/board.c | 1 - include/configs/sunxi-common.h | 2 +- 4 files changed, 5 insertions(+), 10 deletions(-) -- 2.25.1

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linksys wrt1900acs v2 boot problem
by Dilyan Lazarov 07 Jan '23

07 Jan '23

Hi, I have a problem with my linksys wrt1900acs. My main question is this a hardware problem or software problem? Is it possible to address? I have started researching and have tried with "kwboot" under Windows VM - Ubuntu 20 - Linux but I have a problem with usb serial connection. I have tried several things but I understand that it isn't possible to start USB to Serial on a Windows VM. I will expect your response. Thank you in advance. All the best Dilyan I see the following Log from U-Boot with PuTTy under Windows 10: BootROM - 1.73 Booting from NAND flash General initialization - Version: 1.0.0 Detected Device ID 6820 High speed PHY - Version: 2.0 Init RD NAS topology Serdes Lane 3 is USB3 Serdes Lane 4 is SGMII board SerDes lanes topology details: | Lane # | Speed | Type | -------------------------------- | 0 | 06 | SATA0 | | 1 | 05 | PCIe0 | | 2 | 06 | SATA1 | | 3 | 05 | USB3 HOST1 | | 4 | 05 | PCIe1 | | 5 | 00 | SGMII2 | -------------------------------- :** Link is Gen1, check the EP capability PCIe, Idx 0: Link upgraded to Gen2 based on client cpabilities :** Link is Gen1, check the EP capability PCIe, Idx 1: remains Gen1 High speed PHY - Ended Successfully DDR3 Training Sequence - Ver TIP-1.26.0 mvSysEnvGetTopologyUpdateInfo: TWSI Read failed WL Supp: IF 0 busId 1 Failed ! WL Supp: IF 0 failed ddr3TipDynamicWriteLevelingSupp failure ******** DRAM initialization Failed (res 0x1) ******** DDR3 run algorithm - FAILED 0x1 DDR3 Training Sequence - FAILED ********** DRAM initialization failed! ******** -- Dilyan

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kwboot : bug when board stops acking
by SC 06 Jan '23

06 Jan '23

Hi list, I think there's a bug in kwboot. I have a faulty board that stops acking xmodem frames after a certain number of packets and kwboot instead of exiting continues to send frames up to 100%. With the one second retry timer it's very long! More than 2 hours :-( The bug is in the kwboot_xm_sendblock() fonction : https://gitlab.denx.de/u-boot/u-boot/blob/master/tools/kwboot.c#L375 kwboot_tty_recv detects the timeout but the return value is based on the last character received (line 403) The variable c is not initialized so if it keeps the previous value which is ACK => rc=0 => infinite loop There are several ways to fix the bug: * Surround the "switch(c)" with a test: if ( !((rc == -1) && (errno == ETIMEDOUT)) ) { rc = -1; switch (c) { case ACK: rc = 0; break; case NAK: errno = EBADMSG; break; case CAN: errno = ECANCELED; break; default: errno = EPROTO; break; } } return rc; * In the case of a TIMEOUT set c to a specific value and add the case in the switch Do you agree with my diagnosis? What is the best solution to fix this bug? Should I provide a patch? Thank you, Stephane

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Netgear RN102 U-Boot Nand Driver Modification
by Abdus Rainey 06 Jan '23

06 Jan '23

I have recently modded a Netgear RN102 NAND flash from 128 MB to 4096 MB (Samsung k9gbg08u0a) but i have a problem with NAND initialization. I can boot with kwboot which is unique for Armada CPU's. Here is my log from kwboot with my stock mtd0: root@whitepawnxeon:/home/jigsaw/Downloads# kwboot -t -B 115200 /dev/ttyUSB0 -b mtd0stockuboot.img -p Sending boot message. Please reboot the target...- Sending boot image... 0 % [......................................................................] 0 % [......................................................................] 1 % [......................................................................] 1 % [......................................................................] 2 % [......................................................................] 2 % [......................................................................] 3 % [......................................................................] 3 % [......................................................................] 4 % [......................................................................] 5 % [......... General initialization - Version: 1.0.0 High speed PHY - Version: 2.1.4 (COM-PHY-V20) Update PEX Device ID 0x6710 High speed PHY - Ended Successfully 0000 DDR3 Training Sequence - Ver 5.7.1 DDR3 Training Sequence - Run without PBS. DDR3 Training Sequence - Ended Successfully .............................................................] 5 % [......................................................................] 6 % [......................................................................] 6 % [......................................................................] 7 % [......................................................................] 7 % [......................................................................] 8 % [......................................................................] 9 % [......................................................................] 9 % [......................................................................] 10 % [......................................................................] 10 % [......................................................................] 11 % [......................................................................] 11 % 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| __ ) ___ ___ | |_ | | | |___| _ \ / _ \ / _ \| __| | |_| |___| |_) | (_) | (_) | |_ \___/ |____/ \___/ \___/ \__| ** LOADER ** U-Boot 2011.12-gec25d27-dirty (Oct 26 2015 - 16:53:05) Marvell version: v2011.12 2014_T2.0p1 06/23/2015 ReadyNAS-102 V2.0 Board: DB-88F6710-BP SoC: MV6710 A1 CPU: Marvell PJ4B v7 UP (Rev 1) LE CPU @ 1200 [MHz] L2 @ 600 [MHz] TClock @ 200 [MHz] DDR @ 600 [MHz] DDR 16Bit Width, FastPath Memory Access DRAM: 512 MiB Map: Code: 0x1feef000:0x1ff9ef34 BSS: 0x1ffef0a0 Stack: 0x1f9eeef8 Heap: 0x1f9ef000:0x1feef000 NAND: (ID 0xd7ec) nand_get_flash_type: second ID read did not match ac,d7 against ec,52 No NAND device found!!! 0 MiB MMC: MRVL_MMC: 0 *** Warning - readenv() failed, using default environment Initialize and scan all PCI interfaces PEX unit.port(active IF[-first bus]): ------------------------------------------ PEX 0: Root Complex Interface, Detected Link X1, GEN 2.0 PEX 1: Root Complex Interface, Detected Link X1, GEN 2.0 FPU not initialized USB 0: Host Mode USB 1: Host Mode Shutting down unused interfaces: GBE0 SDIO AUDIO TDM Modules/Interfaces Detected: RGMII1 Phy PEX0 (Lane 0) PEX1 (Lane 1) SATA0 (Lane 2) SATA1 (Lane 3) Net: , egiga1 [PRIME] Detect MVT/MP board... Saving Environment to NAND... Erasing Nand... Attempt to erase non page aligned data Power On! Updating env to v3... Saving Environment to NAND... Erasing Nand... Attempt to erase non page aligned data raise: Signal # 8 caught raise: Signal # 8 caught __ __ _ _ | \/ | __ _ _ ____ _____| | | | |\/| |/ _` | '__\ \ / / _ \ | | | | | | (_| | | \ V / __/ | | |_| |_|\__,_|_| \_/ \___|_|_| _ _ ____ _ | | | | | __ ) ___ ___ | |_ | | | |___| _ \ / _ \ / _ \| __| | |_| |___| |_) | (_) | (_) | |_ \___/ |____/ \___/ \___/ \__| ** LOADER ** U-Boot 2011.12-gec25d27-dirty (Oct 26 2015 - 16:53:05) Marvell version: v2011.12 2014_T2.0p1 06/23/2015 ReadyNAS-102 V2.0 Board: DB-88F6710-BP SoC: MV6710 A1 CPU: Marvell PJ4B v7 UP (Rev 1) LE CPU @ 1200 [MHz] L2 @ 600 [MHz] TClock @ 200 [MHz] DDR @ 600 [MHz] DDR 16Bit Width, FastPath Memory Access DRAM: 512 MiB Map: Code: 0x1feef000:0x1ff9ef34 BSS: 0x1ffef0a0 Stack: 0x1f9eeef8 Heap: 0x1f9ef000:0x1feef000 NAND: (ID 0xd7ec) nand_get_flash_type: second ID read did not match ac,d7 against ec,53 No NAND device found!!! 0 MiB MMC: MRVL_MMC: 0 *** Warning - readenv() failed, using default environment Initialize and scan all PCI interfaces PEX unit.port(active IF[-first bus]): ------------------------------------------ PEX 0: Root Complex Interface, Detected Link X1, GEN 2.0 PEX 1: Root Complex Interface, Detected Link X1, GEN 2.0 FPU not initialized USB 0: Host Mode USB 1: Host Mode Shutting down unused interfaces: GBE0 SDIO AUDIO TDM Modules/Interfaces Detected: RGMII1 Phy PEX0 (Lane 0) PEX1 (Lane 1) SATA0 (Lane 2) SATA1 (Lane 3) Net: , egiga1 [PRIME] Detect MVT/MP board... Saving Environment to NAND... Erasing Nand... Attempt to erase non page aligned data Power On! Updating env to v3... Saving Environment to NAND... Erasing Nand... Attempt to erase non page aligned data raise: Signal # 8 caught raise: Signal # 8 caught __ __ _ _ | \/ | __ _ _ ____ _____| | | | |\/| |/ _` | '__\ \ / / _ \ | | | | | | (_| | | \ V / __/ | | |_| |_|\__,_|_| \_/ \___|_|_| _ _ ____ _ | | | | | __ ) ___ ___ | |_ | | | |___| _ \ / _ \ / _ \| __| | |_| |___| |_) | (_) | (_) | |_ \___/ |____/ \___/ \___/ \__| ** LOADER ** U-Boot 2011.12-gec25d27-dirty (Oct 26 2015 - 16:53:05) Marvell version: v2011.12 2014_T2.0p1 06/23/2015 ReadyNAS-102 V2.0 Board: DB-88F6710-BP SoC: MV6710 A1 CPU: Marvell PJ4B v7 UP (Rev 1) LE CPU @ 1200 [MHz] L2 @ 600 [MHz] TClock @ 200 [MHz] DDR @ 600 [MHz] DDR 16Bit Width, FastPath Memory Access DRAM: 512 MiB Map: Code: 0x1feef000:0x1ff9ef34 BSS: 0x1ffef0a0 Stack: 0x1f9eeef8 Heap: 0x1f9ef000:0x1feef000 NAND: (ID 0xd7ec) nand_get_flash_type: second ID read did not match ac,d7 against ec,53 No NAND device found!!! 0 MiB MMC: MRVL_MMC: 0 *** Warning - readenv() failed, using default environment Initialize and scan all PCI interfaces PEX unit.port(active IF[-first bus]): ------------------------------------------ PEX 0: Root Complex Interface, Detected Link X1, GEN 2.0 PEX 1: Root Complex Interface, Detected Link X1, GEN 2.0 FPU not initialized USB 0: Host Mode USB 1: Host Mode Shutting down unused interfaces: GBE0 SDIO AUDIO TDM Modules/Interfaces Detected: RGMII1 Phy PEX0 (Lane 0) PEX1 (Lane 1) SATA0 (Lane 2) SATA1 (Lane 3) Net: , egiga1 [PRIME] As you can see u-boot sees device id and manufacturer id but cannot recognize it.My stock u-boot is very old and i get u-boot source code from Netgear GPL.(ReadyNASOS_V6.6.0_WW_src.zip) In here https://forum.doozan.com/read.php?2,106589,108204#msg-108204 you can see my whole story about this device. Can someone suggest any solution?

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[PATCH] rockchip: rk3328: Set VOP QoS to high priority
by Nicolas Frattaroli 05 Jan '23

05 Jan '23

The default priority for the quality of service for the video output results in unsightly glitches on the output whenever there is memory pressure on the system, which happens a lot. This sets the VOP QoS to high priority, which fixes this issue. Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas(a)gmail.com> --- arch/arm/mach-rockchip/rk3328/rk3328.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3328/rk3328.c b/arch/arm/mach-rockchip/rk3328/rk3328.c index de17b88682..2373586b14 100644 --- a/arch/arm/mach-rockchip/rk3328/rk3328.c +++ b/arch/arm/mach-rockchip/rk3328/rk3328.c @@ -19,6 +19,8 @@ DECLARE_GLOBAL_DATA_PTR; #define GRF_BASE 0xFF100000 #define UART2_BASE 0xFF130000 #define FW_DDR_CON_REG 0xFF7C0040 +#define QOS_VOP_OFFSET 0xFF760080 +#define QOS_VOP_PRIORITY 0x8 const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_EMMC] = "/mmc@ff520000", @@ -54,6 +56,9 @@ int arch_cpu_init(void) /* Disable the ddr secure region setting to make it non-secure */ rk_setreg(FW_DDR_CON_REG, 0x200); +#else + printf("Setting VOP QoS\n"); + rk_setreg(QOS_VOP_OFFSET + QOS_VOP_PRIORITY, 0x2); #endif return 0; } -- 2.37.1

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[PATCH] powerpc: dts: keymile: Deduplicate binman code
by Pali Rohár 03 Jan '23

03 Jan '23

kmcent2-u-boot.dtsi file contains copy of powerpc u-boot.dtsi binman file. So remove code duplication and replace it by including u-boot.dtsi file. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- arch/powerpc/dts/kmcent2-u-boot.dtsi | 22 ++-------------------- 1 file changed, 2 insertions(+), 20 deletions(-) diff --git a/arch/powerpc/dts/kmcent2-u-boot.dtsi b/arch/powerpc/dts/kmcent2-u-boot.dtsi index ab76a9f1226c..d0277627644b 100644 --- a/arch/powerpc/dts/kmcent2-u-boot.dtsi +++ b/arch/powerpc/dts/kmcent2-u-boot.dtsi @@ -74,24 +74,6 @@ compatible = "fsl,pcie-t104x"; law_trgt_if = <0>; }; - - binman { - filename = "u-boot-with-dtb.bin"; - skip-at-start = <CONFIG_SYS_TEXT_BASE>; - sort-by-offset; - pad-byte = <0xff>; - size = <CONFIG_SYS_MONITOR_LEN>; - - u-boot-with-ucode-ptr { - offset = <CONFIG_SYS_TEXT_BASE>; - optional-ucode; - }; - - u-boot-dtb-with-ucode { - align = <256>; - }; - powerpc-mpc85xx-bootpg-resetvec { - offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>; - }; - }; }; + +#include "u-boot.dtsi" -- 2.20.1

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Broken commit de47ff536363289f92f85ed1e4901724d238432d
by Pali Rohár 29 Dec '22

29 Dec '22

Hello Tom! Your commit de47ff536363289f92f85ed1e4901724d238432d ("Convert CONFIG_SYS_MPC85XX_NO_RESETVEC to Kconfig") seems to be broken. If you look at P1020RDB-PD_defconfig file change in this commit there is: --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -9,6 +9,7 @@ CONFIG_MPC85xx=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y +CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y Which does not make sense to me. First thing is that CONFIG_MPC85XX_HAVE_RESET_VECTOR and CONFIG_SYS_MPC85XX_NO_RESETVEC are exclusive options. You can either disable generating of reset vector in image or enable it. What is expected from the result when you ask Kconfig to both enable and disable it? First specified option win? Or last specified win? Or random of those two options win? It is not really clear for me. Second thing is that reset vector is required for (parallel) NOR booting and your change is adding CONFIG_SYS_MPC85XX_NO_RESETVEC=y to defconfig for NOR, which to my guess make image non-bootable and broken. And seems that other defconfig files in that change have similar issues.

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[PATCH v1] net: nuvoton: fix build broken for use phy_get_interface_by_name
by Jim Liu 23 Dec '22

23 Dec '22

The original patch is use phy_get_interface_by_name to set interface. The new patch is use dev_read_phy_mode to replace it. Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> --- drivers/net/npcm750_eth.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/npcm750_eth.c b/drivers/net/npcm750_eth.c index 409d5cce4a..bd29a10def 100644 --- a/drivers/net/npcm750_eth.c +++ b/drivers/net/npcm750_eth.c @@ -710,12 +710,12 @@ static int npcm750_eth_ofdata_to_platdata(struct udevice *dev) pdata->phy_interface = -1; phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", NULL); + if (phy_mode) - pdata->phy_interface = phy_get_interface_by_name(phy_mode); - if (pdata->phy_interface == -1) { - printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + pdata->phy_interface = dev_read_phy_mode(dev); + + if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) return -EINVAL; - } pdata->max_speed = 0; cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL); -- 2.17.1

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[PATCH v2 1/1] gitdm: fix typo csets
by Heinrich Schuchardt 22 Dec '22

22 Dec '22

The output should be human readable. %s/csets/changesets/ Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- v2: avoid typo in test --- gitdm | 2 +- tests/expected-results.txt | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/gitdm b/gitdm index 61318ad..aea16b0 100755 --- a/gitdm +++ b/gitdm @@ -546,7 +546,7 @@ for h in hlist: for e in elist: if e.count > 0: nempl += 1 -reports.Write('Processed %d csets from %d developers\n' % (CSCount, +reports.Write('Processed %d changesets from %d developers\n' % (CSCount, ndev)) reports.Write('%d employers found\n' % (nempl)) reports.Write('A total of %d lines added, %d removed (delta %d)\n' % diff --git a/tests/expected-results.txt b/tests/expected-results.txt index 049f887..03985f3 100644 --- a/tests/expected-results.txt +++ b/tests/expected-results.txt @@ -1,4 +1,4 @@ -Processed 10 csets from 4 developers +Processed 10 changesets from 4 developers 4 employers found A total of 24 lines added, 24 removed (delta 0) -- 2.36.1

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[PATCH v1] 1: Adding rngb entry in imx6ull device tree
by Kshitiz Varshney 21 Dec '22

21 Dec '22

From: Kshitiz <kshitiz.varshney(a)nxp.com> Added entry for rngb in imx6ull device tree which is required for Random number generation in u-boot. Signed-off-by: Kshitiz Varshney <kshitiz.varshney(a)nxp.com> Reviewed-by: Ye Li <ye.li(a)nxp.com> --- arch/arm/dts/imx6ull.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi index 46e7ad6bab..c5d5a5ab7b 100644 --- a/arch/arm/dts/imx6ull.dtsi +++ b/arch/arm/dts/imx6ull.dtsi @@ -66,6 +66,12 @@ clocks = <&clks IMX6ULL_CLK_DCP_CLK>; clock-names = "dcp"; }; + rngb: rng@2284000 { + compatible = "fsl,imx6ull-rngb", "fsl,imx25-rngb"; + reg = <0x02284000 0x4000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>; + }; iomuxc_snvs: iomuxc-snvs@2290000 { compatible = "fsl,imx6ull-iomuxc-snvs"; -- 2.25.1

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