September 2022 - U-Boot

[PATCH] rockchip: px30: support debug uart on UART0
by Quentin Schulz 24 Sep '22

24 Sep '22

From: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> UART0 can obviously also be used for debug uart in U-Boot, so let's add its support. Cc: Quentin Schulz <foss+uboot(a)0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> --- arch/arm/include/asm/arch-rockchip/cru_px30.h | 19 ++++++++++ arch/arm/mach-rockchip/px30/px30.c | 37 ++++++++++++++++++- 2 files changed, 54 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/cru_px30.h b/arch/arm/include/asm/arch-rockchip/cru_px30.h index 732ca37040..b66277fc7f 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_px30.h +++ b/arch/arm/include/asm/arch-rockchip/cru_px30.h @@ -445,5 +445,24 @@ enum { /* CRU_PMU_CLK_SEL0_CON */ CLK_PMU_PCLK_DIV_SHIFT = 0, CLK_PMU_PCLK_DIV_MASK = 0x1f << CLK_PMU_PCLK_DIV_SHIFT, + + /* CRU_PMU_CLKSEL3_CON */ + UART0_PLL_SEL_SHIFT = 14, + UART0_PLL_SEL_MASK = 3 << UART0_PLL_SEL_SHIFT, + UART0_PLL_SEL_GPLL = 0, + UART0_PLL_SEL_24M, + UART0_PLL_SEL_480M, + UART0_PLL_SEL_NPLL, + UART0_DIV_CON_SHIFT = 0, + UART0_DIV_CON_MASK = 0x1f << UART0_DIV_CON_SHIFT, + + /* CRU_PMU_CLKSEL4_CON */ + UART0_CLK_SEL_SHIFT = 14, + UART0_CLK_SEL_MASK = 3 << UART0_PLL_SEL_SHIFT, + UART0_CLK_SEL_UART0 = 0, + UART0_CLK_SEL_UART0_NP5, + UART0_CLK_SEL_UART0_FRAC, + UART0_DIVNP5_SHIFT = 0, + UART0_DIVNP5_MASK = 0x1f << UART0_DIVNP5_SHIFT, }; #endif diff --git a/arch/arm/mach-rockchip/px30/px30.c b/arch/arm/mach-rockchip/px30/px30.c index be70d30cc8..0641e6af0f 100644 --- a/arch/arm/mach-rockchip/px30/px30.c +++ b/arch/arm/mach-rockchip/px30/px30.c @@ -41,6 +41,7 @@ struct mm_region *mem_map = px30_mem_map; #define PMUGRF_BASE 0xff010000 #define GRF_BASE 0xff140000 #define CRU_BASE 0xff2b0000 +#define PMUCRU_BASE 0xff2bc000 #define VIDEO_PHY_BASE 0xff2e0000 #define SERVICE_CORE_ADDR 0xff508000 #define DDR_FW_BASE 0xff534000 @@ -198,6 +199,21 @@ enum { GPIO3A1_UART5_RX = 4, }; +/* PMUGRF_GPIO0BL_IOMUX */ +enum { + GPIO0B3_SHIFT = 6, + GPIO0B3_MASK = 0x3 << GPIO0B3_SHIFT, + GPIO0B3_GPIO = 0, + GPIO0B3_UART0_RX, + GPIO0B3_PMU_DEBUG1, + + GPIO0B2_SHIFT = 4, + GPIO0B2_MASK = 0x3 << GPIO0B2_SHIFT, + GPIO0B2_GPIO = 0, + GPIO0B2_UART0_TX, + GPIO0B2_PMU_DEBUG0, +}; + /* PMUGRF_GPIO0CL_IOMUX */ enum { GPIO0C1_SHIFT = 2, @@ -276,12 +292,16 @@ int arch_cpu_init(void) void board_debug_uart_init(void) { #if defined(CONFIG_DEBUG_UART_BASE) && \ - (CONFIG_DEBUG_UART_BASE == 0xff168000) && \ - (CONFIG_DEBUG_UART_CHANNEL != 1) + (((CONFIG_DEBUG_UART_BASE == 0xff168000) && \ + (CONFIG_DEBUG_UART_CHANNEL != 1)) || \ + CONFIG_DEBUG_UART_BASE == 0xff030000) static struct px30_pmugrf * const pmugrf = (void *)PMUGRF_BASE; #endif static struct px30_grf * const grf = (void *)GRF_BASE; static struct px30_cru * const cru = (void *)CRU_BASE; +#if defined(CONFIG_DEBUG_UART_BASE) && CONFIG_DEBUG_UART_BASE == 0xff030000 + static struct px30_pmucru * const pmucru = (void *)PMUCRU_BASE; +#endif #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff158000) /* uart_sel_clk default select 24MHz */ @@ -346,6 +366,19 @@ void board_debug_uart_init(void) GPIO3A2_MASK | GPIO3A1_MASK, GPIO3A2_UART5_TX << GPIO3A2_SHIFT | GPIO3A1_UART5_RX << GPIO3A1_SHIFT); +#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff030000) + /* uart_sel_clk default select 24MHz */ + rk_clrsetreg(&pmucru->pmu_clksel_con[3], + UART0_PLL_SEL_MASK | UART0_DIV_CON_MASK, + UART0_PLL_SEL_24M << UART0_PLL_SEL_SHIFT | 0); + rk_clrsetreg(&pmucru->pmu_clksel_con[4], + UART0_CLK_SEL_MASK, + UART0_CLK_SEL_UART0 << UART0_CLK_SEL_SHIFT); + + rk_clrsetreg(&pmugrf->gpio0bl_iomux, + GPIO0B3_MASK | GPIO0B2_MASK, + GPIO0B3_UART0_RX << GPIO0B3_SHIFT | + GPIO0B2_UART0_TX << GPIO0B2_SHIFT); #else /* GRF_IOFUNC_CON0 */ enum { -- 2.37.3

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[PATCH] ram: rockchip: fix typo in KConfig option label
by Quentin Schulz 24 Sep '22

24 Sep '22

From: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> RAM_PX30_DDR4 is for DDR4 support and not DDR3 so let's fix the typo. Fixes: 2db36c64bd5a ("ram: rockchip: px30: add a config-based ddr selection") Cc: Quentin Schulz <foss+uboot(a)0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> --- drivers/ram/rockchip/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ram/rockchip/Kconfig b/drivers/ram/rockchip/Kconfig index c459bbf5e2..c29d5e8b38 100644 --- a/drivers/ram/rockchip/Kconfig +++ b/drivers/ram/rockchip/Kconfig @@ -23,7 +23,7 @@ config RAM_ROCKCHIP_DEBUG initialization, configurations and etc. config RAM_PX30_DDR4 - bool "DDR3 support for Rockchip PX30" + bool "DDR4 support for Rockchip PX30" depends on RAM_ROCKCHIP && ROCKCHIP_PX30 help This enables DDR4 sdram support instead of the default DDR3 support -- 2.37.3

2 1

[PATCH] board_f: show_dram_config: Print also real DRAM size
by Pali Rohár 24 Sep '22

24 Sep '22

32-bit U-Boot builds cannot use more than around 2 GB of DDR memory. But on some platforms/boards it is possible to connect also 4 GB SODIMM DDR memory. U-Boot currently prints only effective size of RAM which can use, which may be misleading as somebody would expect that this line prints total size of connected DDR modules. So change show_dram_config code to prints both real and effective DRAM size if they are different. If they are same then print just one number like before. It is possible that effective size is just few bytes smaller than the real size, so print both numbers only in case function print_size() prints formats them differently. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- common/board_f.c | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/common/board_f.c b/common/board_f.c index 9e34fbee147e..3131a06db940 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -54,6 +54,7 @@ #include <asm/sections.h> #include <dm/root.h> #include <linux/errno.h> +#include <linux/log2.h> /* * Pointer to initial global data area @@ -213,6 +214,30 @@ static int announce_dram_init(void) return 0; } +/* + * Check if the sizes in their natural units written in decimal format with + * one fraction number are same. + */ +static int sizes_near(unsigned long long size1, unsigned long long size2) +{ + unsigned int size1_scale = ilog2(size1) / 10 * 10; + unsigned int size1_val = (10 * size1 + ((1ULL << size1_scale) >> 1)) >> size1_scale; + unsigned int size2_scale = ilog2(size2) / 10 * 10; + unsigned int size2_val = (10 * size2 + ((1ULL << size2_scale) >> 1)) >> size2_scale; + + if (size1_val == 10240) { + size1_val = 10; + size1_scale += 10; + } + + if (size2_val == 10240) { + size2_val = 10; + size2_scale += 10; + } + + return size1_scale == size2_scale && size1_val == size2_val; +} + static int show_dram_config(void) { unsigned long long size; @@ -229,7 +254,11 @@ static int show_dram_config(void) } debug("\nDRAM: "); - print_size(size, ""); + print_size(gd->ram_size, ""); + if (!sizes_near(gd->ram_size, size)) { + printf(" (effective "); + print_size(size, ")"); + } board_add_ram_info(0); putc('\n'); -- 2.20.1

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[PATCH] display_options: print_size: Fix order overflow
by Pali Rohár 24 Sep '22

24 Sep '22

Function print_size() round size to the nearst value with one decimal fraction number. But in special cases also unit order may overflow. For example value 1073689396 is printed as "1024 MiB" and value 1073741824 as "1 GiB". Fix this issue by detecting order overflow and increasing unit order. With this change also value 1073689396 is printed as "1 GiB". Signed-off-by: Pali Rohár <pali(a)kernel.org> --- lib/display_options.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/lib/display_options.c b/lib/display_options.c index 360b01bcf5ff..c281c1d2c10d 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -126,6 +126,12 @@ void print_size(uint64_t size, const char *s) if (m >= 10) { m -= 10; n += 1; + + if (n == 1024 && i > 0) { + n = 1; + m = 0; + c = names[i - 1]; + } } } -- 2.20.1

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[PATCH 0/9] Support for 4 GB DDR modules for 32-bit U-Boot builds
by Pali Rohár 24 Sep '22

24 Sep '22

This patch series fixes U-Boot code to correctly handle RAM size larger than 2 GB and then fixes fsl ddr driver to do not crash U-Boot when 4 GB DDR module is detected when U-Boot operates in 32-bit mode (as opposite of the 36-bit mode). With this patch series it is possible to boot 32-bit U-Boot with 4 GB SODIMM DDR3 module without crashes. U-Boot will still use just CONFIG_MAX_MEM_MAPPED amount of RAM, but it is better than crashing due to the truncating of 4GB value to 32-bit number (which is zero). I tested this patch series on powerpc P2020 based board but only with U-Boot v2022.04 because U-Boot master branch is still broken on P2020. Pali Rohár (9): common/memsize.c: Fix get_effective_memsize() to always check for CONFIG_MAX_MEM_MAPPED common/memsize.c: Fix get_effective_memsize() to check for overflow board_f: Fix types for board_get_usable_ram_top() board_f: Fix printing gd->ram_size and gd->ram_top ddr: fsl: Fix checking for maximal mappable memory ddr: fsl: Fix fsl_ddr_sdram_size() for 4GB modules with 32-bit phys_size_t ddr: fsl: Allow to detect 4 GB DDR modules in 32-bit mode ddr: fsl: Fix re-align of verbose DRAM information for non-SPL builds powerpc/mpc85xx: Explain TLB unmapped memory message arch/arm/mach-imx/imx8m/soc.c | 2 +- arch/arm/mach-mvebu/arm64-common.c | 2 +- arch/arm/mach-rockchip/sdram.c | 2 +- arch/arm/mach-stm32mp/dram_init.c | 2 +- arch/arm/mach-sunxi/board.c | 2 +- arch/arm/mach-tegra/board2.c | 2 +- arch/mips/mach-jz47xx/jz4780/jz4780.c | 2 +- arch/mips/mach-octeon/dram.c | 2 +- arch/powerpc/cpu/mpc85xx/tlb.c | 2 +- arch/riscv/cpu/fu540/dram.c | 2 +- arch/riscv/cpu/fu740/dram.c | 2 +- arch/riscv/cpu/generic/dram.c | 2 +- arch/x86/cpu/broadwell/sdram.c | 2 +- arch/x86/cpu/coreboot/sdram.c | 2 +- arch/x86/cpu/efi/payload.c | 2 +- arch/x86/cpu/efi/sdram.c | 2 +- arch/x86/cpu/intel_common/mrc.c | 4 ++-- arch/x86/cpu/ivybridge/sdram.c | 2 +- arch/x86/cpu/qemu/dram.c | 2 +- arch/x86/cpu/quark/dram.c | 2 +- arch/x86/cpu/slimbootloader/sdram.c | 2 +- arch/x86/cpu/tangier/sdram.c | 2 +- arch/x86/include/asm/mrc_common.h | 2 +- arch/x86/include/asm/u-boot-x86.h | 2 +- arch/x86/lib/fsp1/fsp_dram.c | 2 +- arch/x86/lib/fsp2/fsp_dram.c | 2 +- board/broadcom/bcmns3/ns3.c | 2 +- board/imgtec/boston/ddr.c | 2 +- board/menlo/m53menlo/m53menlo.c | 2 +- board/raspberrypi/rpi/rpi.c | 2 +- board/ti/am65x/evm.c | 2 +- board/ti/j721e/evm.c | 2 +- board/ti/j721s2/evm.c | 2 +- board/xilinx/zynqmp/zynqmp.c | 2 +- common/board_f.c | 6 ++--- common/memsize.c | 20 ++++++++++++---- drivers/ddr/fsl/lc_common_dimm_params.c | 3 +++ drivers/ddr/fsl/main.c | 31 ++++++++++++++++++++----- drivers/video/fsl_dcu_fb.c | 2 +- include/init.h | 2 +- 40 files changed, 84 insertions(+), 50 deletions(-) -- 2.20.1

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[PATCH] configs: evb-px30_defconfig: Drop TPL_MAX_SIZE definition
by Michael Trimarchi 23 Sep '22

23 Sep '22

The max size is defined at architectural level Signed-off-by: Michael Trimarchi <michael(a)amarulasolutions.com> --- configs/evb-px30_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/evb-px30_defconfig b/configs/evb-px30_defconfig index 240a044b2a..4f88879e18 100644 --- a/configs/evb-px30_defconfig +++ b/configs/evb-px30_defconfig @@ -17,7 +17,6 @@ CONFIG_SPL_STACK_R_ADDR=0x600000 CONFIG_DEBUG_UART_BASE=0xFF160000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SYS_LOAD_ADDR=0x800800 -CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x400000 -- 2.34.1

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[PATCH v3 00/32] Add support for MediaTek MT7981/MT7986 SoCs - v3
by Weijie Gao 23 Sep '22

23 Sep '22

This patch series add support for MediaTek MT7981/MT7986 SoCs with their reference boards and related drivers. This patch series add basic boot support on eMMC/SD/SPI-NOR/SPI-NAND for these boards. The clock, pinctrl drivers and the SoC initializaton code are also included. Product spec for MT7986: https://www.mediatek.com/products/home-networking/mediatek-filogic-830 Changes of v3: - Use regmap for cpu driver to access hwver registers Changes of v2: - Add cpu driver for print_cpuinfo() - Fix NULL pointer dereference in mtk_image - Fix coding style - Minor changes Weijie Gao (32): arm: mediatek: add support for MediaTek MT7986 SoC arm: mediatek: add support for MediaTek MT7981 SoC board: mediatek: add MT7986 reference boards board: mediatek: add MT7981 reference boards mmc: mediatek: add support for MediaTek MT7891/MT7986 SoCs net: mediatek: use a struct to cover variations of all SoCs net: mediatek: stop using bitfileds for DMA descriptors net: mediatek: add support for PDMA v2 net: mediatek: add support for MediaTek MT7981/MT7986 serial: mtk: add support for using dynamic baud clock souce arm: dts: mt7622: force high-speed mode for uart pwm: mtk: add support for MediaTek MT7986 SoC pwm: mtk: add support for MediaTek MT7981 SoC timer: mtk: add support for MediaTek MT7981/MT7986 SoCs watchdog: mediatek: add support for MediaTek MT7986 SoC spi: add support for MediaTek spi-mem controller i2c: add support for MediaTek I2C interface arm: dts: mt7622: add i2c support dt-bindings: pinctrl: mediatek: add a header for common pinconf parameters pinctrl: mediatek: add pinctrl driver for MT7981 SoC pinctrl: mediatek: add pinctrl driver for MT7986 SoC clk: mediatek: add CLK_BYPASS_XTAL flag to allow bypassing searching clock parent of xtal clock clk: mediatek: add support to configure clock driver parent clk: mediatek: add infrasys clock mux support clk: mediatek: add CLK_XTAL support for clock driver clk: mediatek: add clock driver support for MediaTek MT7986 SoC clk: mediatek: add clock driver support for MediaTek MT7981 SoC cpu: add basic cpu driver for MediaTek ARM chips tools: mtk_image: split gfh header verification into a new function tools: mtk_image: split the code of generating NAND header into a new file tools: mtk_image: add support for nand headers used by newer chips MAINTAINERS: update maintainer for MediaTek ARM platform MAINTAINERS | 6 + arch/arm/dts/Makefile | 9 + arch/arm/dts/mt7622-rfb.dts | 18 + arch/arm/dts/mt7622.dtsi | 25 + arch/arm/dts/mt7981-emmc-rfb.dts | 139 +++ arch/arm/dts/mt7981-rfb.dts | 173 +++ arch/arm/dts/mt7981-sd-rfb.dts | 139 +++ arch/arm/dts/mt7981.dtsi | 295 +++++ arch/arm/dts/mt7986-u-boot.dtsi | 33 + arch/arm/dts/mt7986.dtsi | 350 ++++++ arch/arm/dts/mt7986a-emmc-rfb.dts | 16 + arch/arm/dts/mt7986a-rfb.dts | 218 ++++ arch/arm/dts/mt7986a-sd-rfb.dts | 177 +++ arch/arm/dts/mt7986b-emmc-rfb.dts | 16 + arch/arm/dts/mt7986b-rfb.dts | 204 ++++ arch/arm/dts/mt7986b-sd-rfb.dts | 173 +++ arch/arm/mach-mediatek/Kconfig | 23 + arch/arm/mach-mediatek/Makefile | 2 + arch/arm/mach-mediatek/mt7981/Makefile | 4 + arch/arm/mach-mediatek/mt7981/init.c | 45 + arch/arm/mach-mediatek/mt7981/lowlevel_init.S | 32 + arch/arm/mach-mediatek/mt7986/Makefile | 4 + arch/arm/mach-mediatek/mt7986/init.c | 45 + arch/arm/mach-mediatek/mt7986/lowlevel_init.S | 32 + board/mediatek/mt7981/MAINTAINERS | 10 + board/mediatek/mt7981/Makefile | 3 + board/mediatek/mt7981/mt7981_rfb.c | 10 + board/mediatek/mt7986/MAINTAINERS | 10 + board/mediatek/mt7986/Makefile | 3 + board/mediatek/mt7986/mt7986_rfb.c | 10 + configs/mt7981_emmc_rfb_defconfig | 64 + configs/mt7981_rfb_defconfig | 69 ++ configs/mt7981_sd_rfb_defconfig | 64 + configs/mt7986_rfb_defconfig | 66 ++ configs/mt7986a_bpir3_emmc_defconfig | 64 + configs/mt7986a_bpir3_sd_defconfig | 64 + drivers/clk/mediatek/Makefile | 2 + drivers/clk/mediatek/clk-mt7981.c | 683 +++++++++++ drivers/clk/mediatek/clk-mt7986.c | 672 +++++++++++ drivers/clk/mediatek/clk-mtk.c | 156 ++- drivers/clk/mediatek/clk-mtk.h | 13 +- drivers/cpu/Makefile | 1 + drivers/cpu/mtk_cpu.c | 86 ++ drivers/i2c/Kconfig | 9 + drivers/i2c/Makefile | 1 + drivers/i2c/mtk_i2c.c | 822 +++++++++++++ drivers/mmc/mtk-sd.c | 68 +- drivers/net/mtk_eth.c | 261 ++-- drivers/net/mtk_eth.h | 101 +- drivers/pinctrl/mediatek/Kconfig | 8 + drivers/pinctrl/mediatek/Makefile | 2 + drivers/pinctrl/mediatek/pinctrl-mt7981.c | 1049 +++++++++++++++++ drivers/pinctrl/mediatek/pinctrl-mt7986.c | 775 ++++++++++++ drivers/pwm/pwm-mtk.c | 40 +- drivers/serial/serial_mtk.c | 80 +- drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/mtk_spim.c | 701 +++++++++++ drivers/timer/mtk_timer.c | 59 +- drivers/watchdog/mtk_wdt.c | 1 + include/configs/mt7981.h | 26 + include/configs/mt7986.h | 26 + include/dt-bindings/clock/mt7981-clk.h | 267 +++++ include/dt-bindings/clock/mt7986-clk.h | 249 ++++ include/dt-bindings/pinctrl/mt65xx.h | 41 + tools/Makefile | 1 + tools/mtk_image.c | 377 ++---- tools/mtk_image.h | 25 - tools/mtk_nand_headers.c | 668 +++++++++++ tools/mtk_nand_headers.h | 165 +++ 70 files changed, 9511 insertions(+), 548 deletions(-) create mode 100644 arch/arm/dts/mt7981-emmc-rfb.dts create mode 100644 arch/arm/dts/mt7981-rfb.dts create mode 100644 arch/arm/dts/mt7981-sd-rfb.dts create mode 100644 arch/arm/dts/mt7981.dtsi create mode 100644 arch/arm/dts/mt7986-u-boot.dtsi create mode 100644 arch/arm/dts/mt7986.dtsi create mode 100644 arch/arm/dts/mt7986a-emmc-rfb.dts create mode 100644 arch/arm/dts/mt7986a-rfb.dts create mode 100644 arch/arm/dts/mt7986a-sd-rfb.dts create mode 100644 arch/arm/dts/mt7986b-emmc-rfb.dts create mode 100644 arch/arm/dts/mt7986b-rfb.dts create mode 100644 arch/arm/dts/mt7986b-sd-rfb.dts create mode 100644 arch/arm/mach-mediatek/mt7981/Makefile create mode 100644 arch/arm/mach-mediatek/mt7981/init.c create mode 100644 arch/arm/mach-mediatek/mt7981/lowlevel_init.S create mode 100644 arch/arm/mach-mediatek/mt7986/Makefile create mode 100644 arch/arm/mach-mediatek/mt7986/init.c create mode 100644 arch/arm/mach-mediatek/mt7986/lowlevel_init.S create mode 100644 board/mediatek/mt7981/MAINTAINERS create mode 100644 board/mediatek/mt7981/Makefile create mode 100644 board/mediatek/mt7981/mt7981_rfb.c create mode 100644 board/mediatek/mt7986/MAINTAINERS create mode 100644 board/mediatek/mt7986/Makefile create mode 100644 board/mediatek/mt7986/mt7986_rfb.c create mode 100644 configs/mt7981_emmc_rfb_defconfig create mode 100644 configs/mt7981_rfb_defconfig create mode 100644 configs/mt7981_sd_rfb_defconfig create mode 100644 configs/mt7986_rfb_defconfig create mode 100644 configs/mt7986a_bpir3_emmc_defconfig create mode 100644 configs/mt7986a_bpir3_sd_defconfig create mode 100644 drivers/clk/mediatek/clk-mt7981.c create mode 100644 drivers/clk/mediatek/clk-mt7986.c create mode 100644 drivers/cpu/mtk_cpu.c create mode 100644 drivers/i2c/mtk_i2c.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7981.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7986.c create mode 100644 drivers/spi/mtk_spim.c create mode 100644 include/configs/mt7981.h create mode 100644 include/configs/mt7986.h create mode 100644 include/dt-bindings/clock/mt7981-clk.h create mode 100644 include/dt-bindings/clock/mt7986-clk.h create mode 100644 include/dt-bindings/pinctrl/mt65xx.h create mode 100644 tools/mtk_nand_headers.c create mode 100644 tools/mtk_nand_headers.h -- 2.17.1

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PX30 TPL max size
by Michael Nazzareno Trimarchi 23 Sep '22

23 Sep '22

Hi Tom In uboot 2022.01 we had tpl max size for px30 to 10240 but now after some conversion I can see TPL_MAX_SIZE 0x20000 for the same CPU. Now I think that internal memory is 16Kb for this cpu. Do you have any explanation? Michael

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Pull request: u-boot-imx u-boot-imx-20220919
by Stefano Babic 23 Sep '22

23 Sep '22

Hi Tom, Please pull from u-boot-imx, just some fixes for releases, thanks ! The following changes since commit 12ed6d4911ced1df099a365e0a994b54211b60f3: Merge https://gitlab.denx.de/u-boot/custodians/u-boot-usb (2022-09-19 16:49:18 -0400) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git tags/u-boot-imx-20220922 for you to fetch changes up to 1d8f4c85e3c04f596b0464542221b3507af0014e: kontron-sl-mx8mm: Let CONFIG_SPL_FIT_IMAGE_TINY be selected (2022-09-21 16:19:45 +0200) ---------------------------------------------------------------- u-boot-imx-20220922 ------------------- Fixes for 2022.10 CI : https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/13548 ---------------------------------------------------------------- Fabio Estevam (2): mx8m: csf.sh: Fix the calculation of fit_block_size kontron-sl-mx8mm: Let CONFIG_SPL_FIT_IMAGE_TINY be selected Marek Vasut (1): ARM: imx: Deduplicate i.MX8M SNVS LPGPR unlock Tim Harvey (2): arm: dts: imx8mp-venice-gw74xx: add dsa phy handles to u-boot dtsi arm: dts: imx8mm-venice-gw7901: add dsa phy handles to u-boot dtsi arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/dts/imx8mp-venice-gw74xx-u-boot.dtsi | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-imx8m/imx-regs.h | 5 +++++ arch/arm/mach-imx/imx8m/soc.c | 12 ++++++++++++ board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c | 17 ----------------- board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c | 17 ----------------- board/menlo/mx8menlo/mx8menlo.c | 17 ----------------- configs/kontron-sl-mx8mm_defconfig | 1 - doc/imx/habv4/csf_examples/mx8m/csf.sh | 2 +- 9 files changed, 128 insertions(+), 53 deletions(-) -- ===================================================================== DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, 82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

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[PATCH] ARM: dts: stm32mp15: update DDR node
by Patrick Delaunay 23 Sep '22

23 Sep '22

Remove the unnecessary nodes for TFABOOT and keep the mandatory part in SOC dtsi, only the DDRCTRL and DDRPHY addresses. This patch allows to manage the DDR configuration setting in U-Boot device tree only if it is needed, when CONFIG_SPL is defined. With TFABOOT, the DDR configuration is done in TF-A BL2 and the DDR size is dynamically computed in U-Boot since commit d72e7bbe7c28 ("ram: stm32mp1: compute DDR size from DDRCTL registers"). Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/dts/stm32mp15-ddr.dtsi | 16 ++++++++++++++++ arch/arm/dts/stm32mp15-u-boot.dtsi | 14 -------------- arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi | 1 - arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi | 1 - 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi index 0aac9131a60..d02f79dac66 100644 --- a/arch/arm/dts/stm32mp15-ddr.dtsi +++ b/arch/arm/dts/stm32mp15-ddr.dtsi @@ -4,7 +4,22 @@ */ #include <linux/stringify.h> +#ifdef CONFIG_SPL &ddr { + clocks = <&rcc AXIDCG>, + <&rcc DDRC1>, + <&rcc DDRC2>, + <&rcc DDRPHYC>, + <&rcc DDRCAPB>, + <&rcc DDRPHYCAPB>; + + clock-names = "axidcg", + "ddrc1", + "ddrc2", + "ddrphyc", + "ddrcapb", + "ddrphycapb"; + config-DDR_MEM_COMPATIBLE { u-boot,dm-pre-reloc; @@ -119,6 +134,7 @@ status = "okay"; }; }; +#endif #undef DDR_MEM_COMPATIBLE #undef DDR_MEM_NAME diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index d9d04743ac8..d5c87d29d88 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -53,20 +53,6 @@ reg = <0x5a003000 0x550 0x5a004000 0x234>; - clocks = <&rcc AXIDCG>, - <&rcc DDRC1>, - <&rcc DDRC2>, - <&rcc DDRPHYC>, - <&rcc DDRCAPB>, - <&rcc DDRPHYCAPB>; - - clock-names = "axidcg", - "ddrc1", - "ddrc2", - "ddrphyc", - "ddrcapb", - "ddrphycapb"; - status = "okay"; }; }; diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi index 2db045e7cec..1209dfe009c 100644 --- a/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi @@ -5,7 +5,6 @@ #include <dt-bindings/clock/stm32mp1-clksrc.h> #include "stm32mp15-scmi-u-boot.dtsi" -#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi" / { aliases { diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi index 54662f7e290..c265745ff10 100644 --- a/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi @@ -5,7 +5,6 @@ #include <dt-bindings/clock/stm32mp1-clksrc.h> #include "stm32mp15-scmi-u-boot.dtsi" -#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" / { aliases { -- 2.25.1

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