September 2022 - U-Boot

[PATCH v2 1/3] arm: dts: rockchip: rk3288: move thermal sub nodes to dtsi
by Johan Jonker 28 Sep '22

28 Sep '22

In order to better compare the Linux rk3288.dtsi version with the u-boot version move thermal sub nodes to the dtsi file and remove rk3288-thermal.dtsi Changed: replace underscore in nodename remove comments about sensor and ID use gpu phandle add #cooling-cells to gpu node lower critical temparature remove linux,hwmon property Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> Reviewed-by: Kever Yang <kever.yang(a)rock-chips.com> --- arch/arm/dts/rk3288-thermal.dtsi | 87 -------------------------------- arch/arm/dts/rk3288.dtsi | 74 ++++++++++++++++++++++++++- 2 files changed, 73 insertions(+), 88 deletions(-) delete mode 100644 arch/arm/dts/rk3288-thermal.dtsi diff --git a/arch/arm/dts/rk3288-thermal.dtsi b/arch/arm/dts/rk3288-thermal.dtsi deleted file mode 100644 index 87dd8142..00000000 --- a/arch/arm/dts/rk3288-thermal.dtsi +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for RK3288 SoC thermal - * - * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd - */ - -#include <dt-bindings/thermal/thermal.h> - -reserve_thermal: reserve_thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&tsadc 0>; - -}; - -cpu_thermal: cpu_thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&tsadc 1>; - linux,hwmon; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <100000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -gpu_thermal: gpu_thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&tsadc 2>; - linux,hwmon; - - trips { - gpu_alert0: gpu_alert0 { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - gpu_crit: gpu_crit { - temperature = <100000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 53ee760b..754c77cc 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -339,7 +339,78 @@ }; thermal: thermal-zones { - #include "rk3288-thermal.dtsi" + reserve_thermal: reserve-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 0>; + }; + + cpu_thermal: cpu-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT 6>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 2>; + + trips { + gpu_alert0: gpu_alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_crit: gpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; }; tsadc: tsadc@ff280000 { @@ -849,6 +920,7 @@ /* 500000 1200000 - See crosbug.com/p/33857 */ 600000 1250000 >; + #cooling-cells = <2>; /* min followed by max */ power-domains = <&power RK3288_PD_GPU>; status = "disabled"; }; -- 2.20.1

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[PATCH v1] gpio: adp5585: add gpio driver for ADP5585 I/O Expander Controller
by Alice Guo (OSS) 28 Sep '22

28 Sep '22

From: Alice Guo <alice.guo(a)nxp.com> Signed-off-by: Alice Guo <alice.guo(a)nxp.com> --- arch/arm/include/asm/arch-imx9/gpio.h | 2 + drivers/gpio/Kconfig | 6 + drivers/gpio/Makefile | 1 + drivers/gpio/adp5585_gpio.c | 238 ++++++++++++++++++++++++++ 4 files changed, 247 insertions(+) create mode 100644 drivers/gpio/adp5585_gpio.c diff --git a/arch/arm/include/asm/arch-imx9/gpio.h b/arch/arm/include/asm/arch-imx9/gpio.h index 40732022e7..599f7511c3 100644 --- a/arch/arm/include/asm/arch-imx9/gpio.h +++ b/arch/arm/include/asm/arch-imx9/gpio.h @@ -6,6 +6,8 @@ #ifndef __ASM_ARCH_IMX9_GPIO_H #define __ASM_ARCH_IMX9_GPIO_H +#include <common.h> + struct gpio_regs { u32 gpio_pdor; u32 gpio_psor; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index c949f9d2f7..550ff9c586 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -605,4 +605,10 @@ config TURRIS_OMNIA_MCU help Support for GPIOs on MCU connected to Turris Omnia via i2c. +config ADP5585_GPIO + bool "ADP5585 GPIO driver" + depends on DM_GPIO && DM_I2C + help + Support ADP5585 GPIO expander on i.MX platform. + endif diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 9d718a554e..2f60b98384 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -75,3 +75,4 @@ obj-$(CONFIG_SL28CPLD_GPIO) += sl28cpld-gpio.o obj-$(CONFIG_ZYNQMP_GPIO_MODEPIN) += zynqmp_gpio_modepin.o obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o obj-$(CONFIG_$(SPL_TPL_)TURRIS_OMNIA_MCU) += turris_omnia_mcu.o +obj-$(CONFIG_ADP5585_GPIO) += adp5585_gpio.o diff --git a/drivers/gpio/adp5585_gpio.c b/drivers/gpio/adp5585_gpio.c new file mode 100644 index 0000000000..ea0cb75459 --- /dev/null +++ b/drivers/gpio/adp5585_gpio.c @@ -0,0 +1,238 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2022 NXP + * + * ADP5585 I/O Expander Controller + * + * Author: Alice Guo <alice.guo(a)nxp.com> + */ + +#include <asm/gpio.h> +#include <dm.h> +#include <dt-bindings/gpio/gpio.h> +#include <i2c.h> + +#define ADP5585_ID 0x00 +#define ADP5585_INT_STATUS 0x01 +#define ADP5585_STATUS 0x02 +#define ADP5585_FIFO_1 0x03 +#define ADP5585_FIFO_2 0x04 +#define ADP5585_FIFO_3 0x05 +#define ADP5585_FIFO_4 0x06 +#define ADP5585_FIFO_5 0x07 +#define ADP5585_FIFO_6 0x08 +#define ADP5585_FIFO_7 0x09 +#define ADP5585_FIFO_8 0x0A +#define ADP5585_FIFO_9 0x0B +#define ADP5585_FIFO_10 0x0C +#define ADP5585_FIFO_11 0x0D +#define ADP5585_FIFO_12 0x0E +#define ADP5585_FIFO_13 0x0F +#define ADP5585_FIFO_14 0x10 +#define ADP5585_FIFO_15 0x11 +#define ADP5585_FIFO_16 0x12 +#define ADP5585_GPI_INT_STAT_A 0x13 +#define ADP5585_GPI_INT_STAT_B 0x14 +#define ADP5585_GPI_STATUS_A 0x15 +#define ADP5585_GPI_STATUS_B 0x16 +#define ADP5585_RPULL_CONFIG_A 0x17 +#define ADP5585_RPULL_CONFIG_B 0x18 +#define ADP5585_RPULL_CONFIG_C 0x19 +#define ADP5585_RPULL_CONFIG_D 0x1A +#define ADP5585_GPI_INT_LEVEL_A 0x1B +#define ADP5585_GPI_INT_LEVEL_B 0x1C +#define ADP5585_GPI_EVENT_EN_A 0x1D +#define ADP5585_GPI_EVENT_EN_B 0x1E +#define ADP5585_GPI_INTERRUPT_EN_A 0x1F +#define ADP5585_GPI_INTERRUPT_EN_B 0x20 +#define ADP5585_DEBOUNCE_DIS_A 0x21 +#define ADP5585_DEBOUNCE_DIS_B 0x22 +#define ADP5585_GPO_DATA_OUT_A 0x23 +#define ADP5585_GPO_DATA_OUT_B 0x24 +#define ADP5585_GPO_OUT_MODE_A 0x25 +#define ADP5585_GPO_OUT_MODE_B 0x26 +#define ADP5585_GPIO_DIRECTION_A 0x27 +#define ADP5585_GPIO_DIRECTION_B 0x28 +#define ADP5585_RESET1_EVENT_A 0x29 +#define ADP5585_RESET1_EVENT_B 0x2A +#define ADP5585_RESET1_EVENT_C 0x2B +#define ADP5585_RESET2_EVENT_A 0x2C +#define ADP5585_RESET2_EVENT_B 0x2D +#define ADP5585_RESET_CFG 0x2E +#define ADP5585_PWM_OFFT_LOW 0x2F +#define ADP5585_PWM_OFFT_HIGH 0x30 +#define ADP5585_PWM_ONT_LOW 0x31 +#define ADP5585_PWM_ONT_HIGH 0x32 +#define ADP5585_PWM_CFG 0x33 +#define ADP5585_LOGIC_CFG 0x34 +#define ADP5585_LOGIC_FF_CFG 0x35 +#define ADP5585_LOGIC_INT_EVENT_EN 0x36 +#define ADP5585_POLL_PTIME_CFG 0x37 +#define ADP5585_PIN_CONFIG_A 0x38 +#define ADP5585_PIN_CONFIG_B 0x39 +#define ADP5585_PIN_CONFIG_D 0x3A +#define ADP5585_GENERAL_CFG 0x3B +#define ADP5585_INT_EN 0x3C + +#define ADP5585_MAXGPIO 10 +#define ADP5585_BANK(offs) ((offs) > 4) +#define ADP5585_BIT(offs) ((offs) > 4 ? \ + 1u << ((offs) - 5) : 1u << (offs)) + +struct adp5585_plat { + fdt_addr_t addr; + u8 id; + u8 dat_out[2]; + u8 dir[2]; +}; + +static int adp5585_direction_input(struct udevice *dev, unsigned int offset) +{ + int ret; + unsigned int bank; + struct adp5585_plat *plat = dev_get_plat(dev); + + bank = ADP5585_BANK(offset); + + plat->dir[bank] &= ~ADP5585_BIT(offset); + ret = dm_i2c_write(dev, ADP5585_GPIO_DIRECTION_A + bank, &plat->dir[bank], 1); + + return ret; +} + +static int adp5585_direction_output(struct udevice *dev, unsigned int offset, + int value) +{ + int ret; + unsigned int bank, bit; + struct adp5585_plat *plat = dev_get_plat(dev); + + bank = ADP5585_BANK(offset); + bit = ADP5585_BIT(offset); + + plat->dir[bank] |= bit; + + if (value) + plat->dat_out[bank] |= bit; + else + plat->dat_out[bank] &= ~bit; + + ret = dm_i2c_write(dev, ADP5585_GPO_DATA_OUT_A + bank, &plat->dat_out[bank], 1); + ret |= dm_i2c_write(dev, ADP5585_GPIO_DIRECTION_A + bank, &plat->dir[bank], 1); + + return ret; +} + +static int adp5585_get_value(struct udevice *dev, unsigned int offset) +{ + struct adp5585_plat *plat = dev_get_plat(dev); + unsigned int bank = ADP5585_BANK(offset); + unsigned int bit = ADP5585_BIT(offset); + u8 val; + + if (plat->dir[bank] & bit) + val = plat->dat_out[bank]; + else + dm_i2c_read(dev, ADP5585_GPI_STATUS_A + bank, &val, 1); + + return !!(val & bit); +} + +static int adp5585_set_value(struct udevice *dev, unsigned int offset, int value) +{ + int ret; + unsigned int bank, bit; + struct adp5585_plat *plat = dev_get_plat(dev); + + bank = ADP5585_BANK(offset); + bit = ADP5585_BIT(offset); + + if (value) + plat->dat_out[bank] |= bit; + else + plat->dat_out[bank] &= ~bit; + + ret = dm_i2c_write(dev, ADP5585_GPO_DATA_OUT_A + bank, &plat->dat_out[bank], 1); + + return ret; +} + +static int adp5585_get_function(struct udevice *dev, unsigned int offset) +{ + unsigned int bank, bit, dir; + struct adp5585_plat *plat = dev_get_plat(dev); + + bank = ADP5585_BANK(offset); + bit = ADP5585_BIT(offset); + dir = plat->dir[bank] & bit; + + if (!dir) + return GPIOF_INPUT; + else + return GPIOF_OUTPUT; +} + +static int adp5585_xlate(struct udevice *dev, struct gpio_desc *desc, + struct ofnode_phandle_args *args) +{ + desc->offset = args->args[0]; + desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; + + return 0; +} + +static const struct dm_gpio_ops adp5585_ops = { + .direction_input = adp5585_direction_input, + .direction_output = adp5585_direction_output, + .get_value = adp5585_get_value, + .set_value = adp5585_set_value, + .get_function = adp5585_get_function, + .xlate = adp5585_xlate, +}; + +static int adp5585_probe(struct udevice *dev) +{ + struct adp5585_plat *plat = dev_get_plat(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + int ret; + + if (!plat) + return 0; + + plat->addr = dev_read_addr(dev); + if (plat->addr == FDT_ADDR_T_NONE) + return -EINVAL; + + ret = dm_i2c_read(dev, ADP5585_ID, &plat->id, 1); + if (ret < 0) + return ret; + + uc_priv->gpio_count = ADP5585_MAXGPIO; + uc_priv->bank_name = "adp5585-gpio"; + + for (int i = 0; i < 2; i++) { + ret = dm_i2c_read(dev, ADP5585_GPO_DATA_OUT_A + i, &plat->dat_out[i], 1); + if (ret) + return ret; + + ret = dm_i2c_read(dev, ADP5585_GPIO_DIRECTION_A + i, &plat->dir[i], 1); + if (ret) + return ret; + } + + return 0; +} + +static const struct udevice_id adp5585_ids[] = { + { .compatible = "adp5585" }, + { } +}; + +U_BOOT_DRIVER(adp5585) = { + .name = "adp5585", + .id = UCLASS_GPIO, + .of_match = adp5585_ids, + .probe = adp5585_probe, + .ops = &adp5585_ops, + .plat_auto = sizeof(struct adp5585_plat), +}; -- 2.17.1

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[PATCH v3 4/5] arm: dts: rockchip: rk3128: fix DT node names
by Johan Jonker 28 Sep '22

28 Sep '22

The rk3128 DT node names should be generic. Rename them to the pattern defined in the DT bindings. Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- arch/arm/dts/rk3128-evb.dts | 5 +++ arch/arm/dts/rk3128.dtsi | 62 +++++++++++++++++-------------------- 2 files changed, 33 insertions(+), 34 deletions(-) diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts index e7d8f7c9..93291d78 100644 --- a/arch/arm/dts/rk3128-evb.dts +++ b/arch/arm/dts/rk3128-evb.dts @@ -15,6 +15,11 @@ stdout-path = &uart2; }; + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + vcc5v0_otg: vcc5v0-otg-drv { compatible = "regulator-fixed"; regulator-name = "vcc5v0_otg"; diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi index b58804b6..48833bff 100644 --- a/arch/arm/dts/rk3128.dtsi +++ b/arch/arm/dts/rk3128.dtsi @@ -8,7 +8,6 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/clock/rk3128-cru.h> -#include "skeleton.dtsi" / { compatible = "rockchip,rk3128"; @@ -34,11 +33,6 @@ mmc1 = &sdmmc; }; - memory { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - arm-pmu { compatible = "arm,cortex-a7-pmu"; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, @@ -52,10 +46,10 @@ #size-cells = <0>; enable-method = "rockchip,rk3128-smp"; - cpu0:cpu@0x000 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; - reg = <0x000>; + reg = <0x0>; operating-points = < /* KHz uV */ 816000 1000000 @@ -65,22 +59,22 @@ clocks = <&cru ARMCLK>; }; - cpu1:cpu@0x001 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a7"; - reg = <0x001>; + reg = <0x1>; }; - cpu2:cpu@0x002 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a7"; - reg = <0x002>; + reg = <0x2>; }; - cpu3:cpu@0x003 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a7"; - reg = <0x003>; + reg = <0x3>; }; }; @@ -165,7 +159,7 @@ interrupt-parent = <&gic>; ranges; - pdma: pdma@20078000 { + pdma: dma-controller@20078000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x20078000 0x4000>; arm,pl330-broken-no-flushp;//2 @@ -207,7 +201,7 @@ rockchip,broadcast = <1>; }; - watchdog: wdt@2004c000 { + watchdog: watchdog@2004c000 { compatible = "rockchip,watch dog"; reg = <0x2004c000 0x100>; clock-names = "pclk_wdt"; @@ -224,7 +218,7 @@ #reset-cells = <1>; }; - nandc: nandc@10500000 { + nandc: nand-controller@10500000 { compatible = "rockchip,rk-nandc"; reg = <0x10500000 0x4000>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; @@ -247,7 +241,7 @@ assigned-clock-rates = <594000000>; }; - uart0: serial0@20060000 { + uart0: serial@20060000 { compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; reg = <0x20060000 0x100>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; @@ -262,7 +256,7 @@ #dma-cells = <2>; }; - uart1: serial1@20064000 { + uart1: serial@20064000 { compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; reg = <0x20064000 0x100>; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; @@ -277,7 +271,7 @@ #dma-cells = <2>; }; - uart2: serial2@20068000 { + uart2: serial@20068000 { compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; reg = <0x20068000 0x100>; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; @@ -304,7 +298,7 @@ status = "disabled"; }; - pwm0: pwm0@20050000 { + pwm0: pwm@20050000 { compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; reg = <0x20050000 0x10>; #pwm-cells = <3>; @@ -314,7 +308,7 @@ clock-names = "pwm"; }; - pwm1: pwm1@20050010 { + pwm1: pwm@20050010 { compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; reg = <0x20050010 0x10>; #pwm-cells = <3>; @@ -324,7 +318,7 @@ clock-names = "pwm"; }; - pwm2: pwm2@20050020 { + pwm2: pwm@20050020 { compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; reg = <0x20050020 0x10>; #pwm-cells = <3>; @@ -334,7 +328,7 @@ clock-names = "pwm"; }; - pwm3: pwm3@20050030 { + pwm3: pwm@20050030 { compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; reg = <0x20050030 0x10>; #pwm-cells = <3>; @@ -430,7 +424,7 @@ status = "disabled"; }; - sdmmc: dwmmc@10214000 { + sdmmc: mmc@10214000 { compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10214000 0x4000>; max-frequency = <150000000>; @@ -445,7 +439,7 @@ status = "disabled"; }; - emmc: dwmmc@1021c000 { + emmc: mmc@1021c000 { compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x1021c000 0x4000>; max-frequency = <150000000>; @@ -464,7 +458,7 @@ status = "disabled"; }; - i2c0: i2c0@20072000 { + i2c0: i2c@20072000 { compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; reg = <20072000 0x1000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; @@ -476,7 +470,7 @@ pinctrl-0 = <&i2c0_xfer>; }; - i2c1: i2c1@20056000 { + i2c1: i2c@20056000 { compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; reg = <0x20056000 0x1000>; interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; @@ -488,7 +482,7 @@ pinctrl-0 = <&i2c1_xfer>; }; - i2c2: i2c2@2005a000 { + i2c2: i2c@2005a000 { compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; reg = <0x2005a000 0x1000>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; @@ -500,7 +494,7 @@ pinctrl-0 = <&i2c2_xfer>; }; - i2c3: i2c3@2005e000 { + i2c3: i2c@2005e000 { compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; reg = <0x2005e000 0x1000>; interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; @@ -546,7 +540,7 @@ #size-cells = <1>; ranges; - gpio0: gpio0@2007c000 { + gpio0: gpio@2007c000 { compatible = "rockchip,gpio-bank"; reg = <0x2007c000 0x100>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; @@ -557,7 +551,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@20080000 { + gpio1: gpio@20080000 { compatible = "rockchip,gpio-bank"; reg = <0x20080000 0x100>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; @@ -568,7 +562,7 @@ #interrupt-cells = <2>; }; - gpio2: gpio2@20084000 { + gpio2: gpio@20084000 { compatible = "rockchip,gpio-bank"; reg = <0x20084000 0x100>; interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; @@ -579,7 +573,7 @@ #interrupt-cells = <2>; }; - gpio3: gpio2@20088000 { + gpio3: gpio@20088000 { compatible = "rockchip,gpio-bank"; reg = <0x20088000 0x100>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; -- 2.20.1

2 2

[PATCH v3 2/5] arm: dts: rockchip: rk3128: bulk convert gpios to their constant counterparts
by Johan Jonker 28 Sep '22

28 Sep '22

Bulk convert rk3128 DT gpios to their constant counterparts. sed -i -f script.sed rk3128.dtsi sed -i -f script.sed rk3128-evb.dts ================================ /rockchip,pins *=/bcheck b # to end of script :append-next-line N :check /^[^;]*$/bappend-next-line s/<RK_GPIO$[0-9]$ /<\1 /g s/<$[^ ][^ ]* *$0 /<\1RK_PA0 /g s/<$[^ ][^ ]* *$1 /<\1RK_PA1 /g s/<$[^ ][^ ]* *$2 /<\1RK_PA2 /g s/<$[^ ][^ ]* *$3 /<\1RK_PA3 /g s/<$[^ ][^ ]* *$4 /<\1RK_PA4 /g s/<$[^ ][^ ]* *$5 /<\1RK_PA5 /g s/<$[^ ][^ ]* *$6 /<\1RK_PA6 /g s/<$[^ ][^ ]* *$7 /<\1RK_PA7 /g s/<$[^ ][^ ]* *$8 /<\1RK_PB0 /g s/<$[^ ][^ ]* *$9 /<\1RK_PB1 /g s/<$[^ ][^ ]* *$10 /<\1RK_PB2 /g s/<$[^ ][^ ]* *$11 /<\1RK_PB3 /g s/<$[^ ][^ ]* *$12 /<\1RK_PB4 /g s/<$[^ ][^ ]* *$13 /<\1RK_PB5 /g s/<$[^ ][^ ]* *$14 /<\1RK_PB6 /g s/<$[^ ][^ ]* *$15 /<\1RK_PB7 /g s/<$[^ ][^ ]* *$16 /<\1RK_PC0 /g s/<$[^ ][^ ]* *$17 /<\1RK_PC1 /g s/<$[^ ][^ ]* *$18 /<\1RK_PC2 /g s/<$[^ ][^ ]* *$19 /<\1RK_PC3 /g s/<$[^ ][^ ]* *$20 /<\1RK_PC4 /g s/<$[^ ][^ ]* *$21 /<\1RK_PC5 /g s/<$[^ ][^ ]* *$22 /<\1RK_PC6 /g s/<$[^ ][^ ]* *$23 /<\1RK_PC7 /g s/<$[^ ][^ ]* *$24 /<\1RK_PD0 /g s/<$[^ ][^ ]* *$25 /<\1RK_PD1 /g s/<$[^ ][^ ]* *$26 /<\1RK_PD2 /g s/<$[^ ][^ ]* *$27 /<\1RK_PD3 /g s/<$[^ ][^ ]* *$28 /<\1RK_PD4 /g s/<$[^ ][^ ]* *$29 /<\1RK_PD5 /g s/<$[^ ][^ ]* *$30 /<\1RK_PD6 /g s/<$[^ ][^ ]* *$31 /<\1RK_PD7 /g s/<$[^ ][^ ]* *[^ ][^ ]* *$0 /<\1RK_FUNC_GPIO /g s/<$[^ ][^ ]* *[^ ][^ ]* *$RK_FUNC_$[1-9]$ /<\1\2 /g Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- arch/arm/dts/rk3128-evb.dts | 4 +- arch/arm/dts/rk3128.dtsi | 86 ++++++++++++++++++------------------- 2 files changed, 45 insertions(+), 45 deletions(-) diff --git a/arch/arm/dts/rk3128-evb.dts b/arch/arm/dts/rk3128-evb.dts index 2fb2b0da..a407ac2d 100644 --- a/arch/arm/dts/rk3128-evb.dts +++ b/arch/arm/dts/rk3128-evb.dts @@ -82,13 +82,13 @@ &pinctrl { usb_otg { otg_vbus_drv: host-vbus-drv { - rockchip,pins = <0 26 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; }; }; usb_host { host_vbus_drv: host-vbus-drv { - rockchip,pins = <2 23 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; }; }; }; diff --git a/arch/arm/dts/rk3128.dtsi b/arch/arm/dts/rk3128.dtsi index 3c5f54f6..5a1c1547 100644 --- a/arch/arm/dts/rk3128.dtsi +++ b/arch/arm/dts/rk3128.dtsi @@ -618,85 +618,85 @@ */ emmc_clk: emmc-clk { - rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; }; emmc_cmd: emmc-cmd { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; emmc_pwren: emmc-pwren { - rockchip,pins = <2 5 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA5 2 &pcfg_pull_none>; }; emmc_bus8: emmc-bus8 { - rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>, - <1 25 RK_FUNC_2 &pcfg_pull_none>, - <1 26 RK_FUNC_2 &pcfg_pull_none>, - <1 27 RK_FUNC_2 &pcfg_pull_none>, - <1 28 RK_FUNC_2 &pcfg_pull_none>, - <1 29 RK_FUNC_2 &pcfg_pull_none>, - <1 30 RK_FUNC_2 &pcfg_pull_none>, - <1 31 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, + <1 RK_PD1 2 &pcfg_pull_none>, + <1 RK_PD2 2 &pcfg_pull_none>, + <1 RK_PD3 2 &pcfg_pull_none>, + <1 RK_PD4 2 &pcfg_pull_none>, + <1 RK_PD5 2 &pcfg_pull_none>, + <1 RK_PD6 2 &pcfg_pull_none>, + <1 RK_PD7 2 &pcfg_pull_none>; }; }; nandc{ nandc_ale:nandc-ale { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_cle:nandc-cle { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_wrn:nandc-wrn { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_rdn:nandc-rdn { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_rdy:nandc-rdy { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_cs0:nandc-cs0 { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; nandc_data: nandc-data { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; }; uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>, - <0 17 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>, + <0 RK_PC1 1 &pcfg_pull_none>; }; uart0_cts: uart0-cts { - rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC2 1 &pcfg_pull_none>; }; uart0_rts: uart0-rts { - rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>; }; }; uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>, - <2 23 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>, + <2 RK_PC7 1 &pcfg_pull_none>; }; }; uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>, - <1 19 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_none>, + <1 RK_PC3 2 &pcfg_pull_none>; }; }; @@ -727,75 +727,75 @@ pwm0 { pwm0_pin: pwm0-pin { - rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; }; }; pwm1 { pwm1_pin: pwm1-pin { - rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; }; }; pwm2 { pwm2_pin: pwm2-pin { - rockchip,pins = <0 1 2 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>; }; }; pwm3 { pwm3_pin: pwm3-pin { - rockchip,pins = <0 27 1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; }; }; i2c0 { i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, - <0 1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, + <0 RK_PA1 1 &pcfg_pull_none>; }; }; i2c1 { i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, - <0 3 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, + <0 RK_PA3 1 &pcfg_pull_none>; }; }; i2c2 { i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 20 3 &pcfg_pull_none>, - <2 21 3 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, + <2 RK_PC5 3 &pcfg_pull_none>; }; }; i2c3 { i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, - <0 7 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, + <0 RK_PA7 1 &pcfg_pull_none>; }; }; spi0 { spi0_txd_mux0:spi0-txd-mux0 { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; spi0_rxd_mux0:spi0-rxd-mux0 { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; spi0_clk_mux0:spi0-clk-mux0 { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; spi0_cs0_mux0:spi0-cs0-mux0 { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; spi0_cs1_mux0:spi0-cs1-mux0 { - rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; }; }; -- 2.20.1

2 1

[PATCH v1 1/3] arm: dts: rockchip: rk3288: move thermal sub nodes to dtsi
by Johan Jonker 28 Sep '22

28 Sep '22

In order to better compare the Linux rk3288.dtsi version with the u-boot version move thermal sub nodes to the dtsi file and remove rk3288-thermal.dtsi Changed: replace underscore in nodename remove comments about sensor and ID use gpu phandle add #cooling-cells to gpu node lower critical temparature remove linux,hwmon property Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- arch/arm/dts/rk3288-thermal.dtsi | 87 -------------------------------- arch/arm/dts/rk3288.dtsi | 74 ++++++++++++++++++++++++++- 2 files changed, 73 insertions(+), 88 deletions(-) delete mode 100644 arch/arm/dts/rk3288-thermal.dtsi diff --git a/arch/arm/dts/rk3288-thermal.dtsi b/arch/arm/dts/rk3288-thermal.dtsi deleted file mode 100644 index 87dd8142..00000000 --- a/arch/arm/dts/rk3288-thermal.dtsi +++ /dev/null @@ -1,87 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Device Tree Source for RK3288 SoC thermal - * - * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd - */ - -#include <dt-bindings/thermal/thermal.h> - -reserve_thermal: reserve_thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&tsadc 0>; - -}; - -cpu_thermal: cpu_thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&tsadc 1>; - linux,hwmon; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <100000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; - -gpu_thermal: gpu_thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&tsadc 2>; - linux,hwmon; - - trips { - gpu_alert0: gpu_alert0 { - temperature = <80000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - gpu_crit: gpu_crit { - temperature = <100000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; -}; diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 9fb6d86b..c46741b0 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -339,7 +339,78 @@ }; thermal: thermal-zones { - #include "rk3288-thermal.dtsi" + reserve_thermal: reserve-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 0>; + }; + + cpu_thermal: cpu-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT 6>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 2>; + + trips { + gpu_alert0: gpu_alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_crit: gpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; }; tsadc: tsadc@ff280000 { @@ -849,6 +920,7 @@ /* 500000 1200000 - See crosbug.com/p/33857 */ 600000 1250000 >; + #cooling-cells = <2>; /* min followed by max */ power-domains = <&power RK3288_PD_GPU>; status = "disabled"; }; -- 2.20.1

2 2

rockchip: rk3399: add Support NanoPi R4S 1GB DDR3 Version
by h3lmut 28 Sep '22

28 Sep '22

The NanoPi R4S 1GB version (rk3399) doesnt boot up with current u-boot. Armbian team has done some patches which will work with both versions (1GB and 4GB) Github Pr: https://github.com/anaelorlinski/OpenWrt-NanoPi-R2S-R4S-Builds/commit/9d836… From 1bc90230df5cd55513268f2f7a43abdbad1161b5 Mon Sep 17 00:00:00 2001 From: hmz007 <hmz007(a)gmail.com> Date: Sat, 19 Dec 2020 19:39:14 +0800 Subject: [PATCH 3/4] ram: rk3399: Add support for multiple DDR types Move rockchip,sdram-params to named subnode to include multiple sdram parameters, and then read the parameters (by subnode name, first subnode or current node) before rk3399_dmc_init(). Signed-off-by: hmz007 <hmz007(a)gmail.com> --- arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi | 6 ++- arch/arm/dts/rk3399-sdram-ddr3-1600.dtsi | 5 +- arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi | 6 ++- .../arm/dts/rk3399-sdram-lpddr3-2GB-1600.dtsi | 3 ++ .../arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi | 3 ++ .../rk3399-sdram-lpddr3-samsung-4GB-1866.dtsi | 3 ++ arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi | 3 ++ drivers/ram/rockchip/sdram_rk3399.c | 49 +++++++++++++++---- 8 files changed, 64 insertions(+), 14 deletions(-) diff --git a/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi b/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi index 7fae249536..dad5b7fbd4 100644 --- a/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi +++ b/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi

2 1

[PATCH] tee: optee: discover services dependent on tee-supplicant
by Etienne Carriere 28 Sep '22

28 Sep '22

This change makes OP-TEE to enumerate both standalone services and the services depending on tee-supplicant support in U-Boot. This change also drivers for this later to be bind. It is assumed that one implementing an OP-TEE device driver has all expected tee-supplicant services support in U-Boot. Signed-off-by: Etienne Carriere <etienne.carriere(a)linaro.org> --- drivers/tee/optee/core.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c index 9240277579..7da35f2eda 100644 --- a/drivers/tee/optee/core.c +++ b/drivers/tee/optee/core.c @@ -102,13 +102,14 @@ static int bind_service_list(struct udevice *dev, struct tee_shm *service_list, return 0; } -static int __enum_services(struct udevice *dev, struct tee_shm *shm, size_t *shm_size, u32 tee_sess) +static int __enum_services(struct udevice *dev, struct tee_shm *shm, size_t *shm_size, u32 tee_sess, + unsigned int pta_cmd) { struct tee_invoke_arg arg = { }; struct tee_param param = { }; int ret = 0; - arg.func = PTA_CMD_GET_DEVICES; + arg.func = pta_cmd; arg.session = tee_sess; /* Fill invoke cmd params */ @@ -118,7 +119,7 @@ static int __enum_services(struct udevice *dev, struct tee_shm *shm, size_t *shm ret = tee_invoke_func(dev, &arg, 1, &param); if (ret || (arg.ret && arg.ret != TEE_ERROR_SHORT_BUFFER)) { - dev_err(dev, "PTA_CMD_GET_DEVICES invoke function err: 0x%x\n", arg.ret); + dev_err(dev, "Enumeration command 0x%x failed: 0x%x\n", pta_cmd, arg.ret); return -EINVAL; } @@ -127,12 +128,13 @@ static int __enum_services(struct udevice *dev, struct tee_shm *shm, size_t *shm return 0; } -static int enum_services(struct udevice *dev, struct tee_shm **shm, size_t *count, u32 tee_sess) +static int enum_services(struct udevice *dev, struct tee_shm **shm, size_t *count, u32 tee_sess, + unsigned int pta_cmd) { size_t shm_size = 0; int ret; - ret = __enum_services(dev, NULL, &shm_size, tee_sess); + ret = __enum_services(dev, NULL, &shm_size, tee_sess, pta_cmd); if (ret) return ret; @@ -142,7 +144,7 @@ static int enum_services(struct udevice *dev, struct tee_shm **shm, size_t *coun return ret; } - ret = __enum_services(dev, *shm, &shm_size, tee_sess); + ret = __enum_services(dev, *shm, &shm_size, tee_sess, pta_cmd); if (!ret) *count = shm_size / sizeof(struct tee_optee_ta_uuid); @@ -174,20 +176,32 @@ static int bind_service_drivers(struct udevice *dev) struct tee_shm *service_list = NULL; size_t service_count; u32 tee_sess; - int ret; + int ret, ret2; ret = open_enum_session(dev, &tee_sess); if (ret) return ret; - ret = enum_services(dev, &service_list, &service_count, tee_sess); + ret = enum_services(dev, &service_list, &service_count, tee_sess, + PTA_CMD_GET_DEVICES); if (!ret) ret = bind_service_list(dev, service_list, service_count); tee_shm_free(service_list); + + ret2 = enum_services(dev, &service_list, &service_count, tee_sess, + PTA_CMD_GET_DEVICES_SUPP); + if (!ret2) + ret2 = bind_service_list(dev, service_list, service_count); + + tee_shm_free(service_list); + tee_close_session(dev, tee_sess); - return ret; + if (ret) + return ret; + + return ret2; } /** -- 2.25.1

1 1

[PATCH v4] tee: optee: rework TA bus scanning code
by Patrick DELAUNAY 28 Sep '22

28 Sep '22

Hi Simon, On 9/12/22 20:31, Simon Glass wrote: > Hi Ilias, > > On Wed, 7 Sept 2022 at 15:32, Ilias Apalodimas > <ilias.apalodimas(a)linaro.org> wrote: >> Hi Simon, >> >> On Thu, 8 Sept 2022 at 00:11, Simon Glass <sjg(a)chromium.org> wrote: >>> Hi Ilias, >>> >>> On Tue, 6 Sept 2022 at 15:23, Ilias Apalodimas >>> <ilias.apalodimas(a)linaro.org> wrote: >>>> Hi Simon, >>>> >>>> On Tue, Sep 06, 2022 at 03:18:28PM -0600, Simon Glass wrote: >>>>> Hi, >>>>> >>>>> On Tue, 6 Sept 2022 at 03:37, Ilias Apalodimas >>>>> <ilias.apalodimas(a)linaro.org> wrote: >>>>>> Late versions of OP-TEE support a pseudo bus. TAs that behave as >>>>>> hardware blocks (e.g TPM, RNG etc) present themselves on a bus >>>>>> whichwe can >>>>>> scan. Unfortunately U-Boot doesn't support that yet. It's worth >>>>>> noting >>>>>> that we already have a workaround for RNG. The details are in >>>>>> commit 70812bb83da6 ("tee: optee: bind rng optee driver") >>>>>> >>>>>> So let's add a list of devices based on U-Boot Kconfig options >>>>>> that we will >>>>>> scan until we properly implement the tee-bus functionality. >>>>>> >>>>>> While at it change the behaviour of the tee core itself wrt to device >>>>>> binding. If some device binding fails, print a warning instead of >>>>>> disabling OP-TEE. >>>>>> >>>>>> Signed-off-by: Ilias Apalodimas <ilias.apalodimas(a)linaro.org> >>>>>> Reviewed-by: Jens Wiklander <jens.wiklander(a)linaro.org> >>>>>> Reviewed-by: Etienne Carriere <etienne.carriere(a)linaro.org> >>>>>> --- >>>>>> Changes since v3: >>>>>> - Use NULL instead of a child ptr on device_bind_driver(), since >>>>>> it's not >>>>>> really needed >>>>>> - Changed the style of the optee_bus_probe[] definition to >>>>>> {.drv_name = xxx, .dev_name = yyy } >>>>>> >>>>>> Changes since v2: >>>>>> - Fixed typo on driver name ftpm-tee -> ftpm_tee >>>>>> >>>>>> Changes since v1: >>>>>> - remove a macro and use ARRAY_SIZE directly >>>>>> drivers/tee/optee/core.c | 24 +++++++++++++++++++----- >>>>>> 1 file changed, 19 insertions(+), 5 deletions(-) >>>>>> >>>>>> diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c >>>>>> index a89d62aaf0b3..c201a4635e6b 100644 >>>>>> --- a/drivers/tee/optee/core.c >>>>>> +++ b/drivers/tee/optee/core.c >>>>>> @@ -31,6 +31,18 @@ struct optee_pdata { >>>>>> optee_invoke_fn *invoke_fn; >>>>>> }; >>>>>> >>>>>> +static const struct { >>>>>> + const char *drv_name; >>>>>> + const char *dev_name; >>>>>> +} optee_bus_probe[] = { >>>>>> +#ifdef CONFIG_RNG_OPTEE >>>>>> + { .drv_name = "optee-rng", .dev_name = "optee-rng" }, >>>>>> +#endif >>>>>> +#ifdef CONFIG_TPM2_FTPM_TEE >>>>>> + { .drv_name = "ftpm_tee", .dev_name = "ftpm_tee" }, >>>>>> +#endif >>>>>> +}; >>>>>> + >>>>>> struct rpc_param { >>>>>> u32 a0; >>>>>> u32 a1; >>>>>> @@ -642,8 +654,7 @@ static int optee_probe(struct udevice *dev) >>>>>> { >>>>>> struct optee_pdata *pdata = dev_get_plat(dev); >>>>>> u32 sec_caps; >>>>>> - struct udevice *child; >>>>>> - int ret; >>>>>> + int ret, i; >>>>>> >>>>>> if (!is_optee_api(pdata->invoke_fn)) { >>>>>> dev_err(dev, "OP-TEE api uid mismatch\n"); >>>>>> @@ -672,10 +683,13 @@ static int optee_probe(struct udevice *dev) >>>>>> * in U-Boot, the discovery of TA on the TEE bus is not supported: >>>>>> * only bind the drivers associated to the supported OP-TEETA >>>>>> */ >>>>>> - if (IS_ENABLED(CONFIG_RNG_OPTEE)) { >>>>>> - ret = device_bind_driver(dev, "optee-rng", "optee-rng", &child); >>>>>> + >>>>>> + for (i = 0; i < ARRAY_SIZE(optee_bus_probe); i++) { >>>>>> + ret = device_bind_driver(dev, optee_bus_probe[i].drv_name, >>>>>> + optee_bus_probe[i].dev_name, NULL); >>>>>> if (ret) >>>>>> - return ret; >>>>>> + dev_warn(dev, "Failed to bind device %s\n", >>>>>> + optee_bus_probe[i].dev_name); >>>>> Please add device tree nodes for these and all this code can go away. >>>> That's the exact opposite of what the commit message describes. OP-TEE >>>> supports a scannable bus ifor TAs that behave like hardware blocks and >>>> doesn't need a DT entry. Since it's really the TAs compilation decision >>>> to support that or not having them as a DT node is not always the right >>>> choice. >>> This is continuing the perversion of how things are supposed to work >>> in driver model. >> Which is not the only thing we need to keep in mind though. >> >>> We need to talk about this because it is simply the wrong way to be >>> approaching this. >> This is already part of other software components though, e.g it's >> already in the kernel. So I don't think it's the wrong approach. >> >>> There is nothing wrong with putting things in the DT >>> and this is how U-Boot works. For now, please create a binding and get >>> it reviewed. You don't need all the internal objects but you do need >>> an OP-TEE driver and node, as we have with PCI. >> Some things *are* working without a DT entry. You had similar >> concerns on FF-A (where you requested a DT node again) and people gave >> the exact same response. As long as a bus is scanable in any way, >> it's preferable to than adding a DT entry. Moreover this code does >> not prevent anyone from adding a DT entry. >> >> To make things even worse if the TA is compiled as 'scanable' and has >> a DT entry, it might cause issues down the road when being probed by >> the kernel. So really this is just a patch that makes u-boot behave >> and plug in properly to the rest of the ecosystem > Calling device_bind() is supposed to be used in extremis. I don't see > any scanning of an OP-TEE bus here. I just see it binding two child > devices which are hard-coded in U-Boot. What am I missing? The tee bus is supported in Linux kernel (each TA have a UUID and is discoverable by the TEE driver). see drivers/tee/optee/core.c::optee_bus_scan() and "struct tee_client_driver" with TA UUID It wasn't supported in U-Boot is the first TEE/OP-TEE driver implementation => TA support was hardcoded, under the associated CONFIG and the probe failed when the TA is not present. for example, I add this binding for TA_RNG in drivers/rng/optee_rng.c The TEE bus feature is added by the Etienne in the serie [1]. This bus is more flexible and avoid OP-TEE to dynamically modify the device tree to add/remove the supported SW component (TA support are activated during OP-TEE compilation) as the binding is managed dynamically in OP-TEE as it is done in Linux. For information, on STM32MP15 platform, I have the trace "can't open session:" for RNG TA for each 'rng' command when this TA is not supported in OP-TEE but OP-TEE RNG driver is activated in U-Boot, because the driver is binding. [1] drivers: tee: optee: remove unused probe local variable http://patchwork.ozlabs.org/project/uboot/list/?series=311351&state=* > This appears to be a Linaro binding, so you should be able to update > it easily enough. > > Regards, > Simon Regards Patrick

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[PATCH] rockchip: rk3399: add ethaddr and serial# init, enable for R4S
by Christian Kohlschütter 28 Sep '22

28 Sep '22

Some RK3399 boards, such as newer revisions of NanoPi R4S, do not provide an EEPROM chip containing a globally unique MAC address. Currently, this means that a randomly generated temporary MAC address may be generated each time the device is rebooted, leading to ARP cache issues and other confusing bugs. Since RK3399 CPUs provide a built-in unique serial number, we can reliably derive a locally MAC address from it by reading the corresponding bits from the non-secure efuse block. Port from uboot-rockchip 0c294d0, fix compilation issues and adjust coding style. rockchip: board: puma_rk3399: derive ethaddr from cpuid rockchip: board: puma_rk3399: add support for serial# and cpuid# rockchip: efuse: add (misc) driver for RK3399 non-secure efuse block via efuses Signed-off-by: Christian Kohlschütter <christian(a)kohlschutter.com> --- board/rockchip/evb_rk3399/evb-rk3399.c | 120 +++++++++++++++++++++++++ configs/nanopi-r4s-rk3399_defconfig | 4 + drivers/misc/Makefile | 2 +- 3 files changed, 125 insertions(+), 1 deletion(-) diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index abb76585cf..ab8738ccf3 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -5,11 +5,20 @@ #include <common.h> #include <dm.h> +#include <misc.h> +#include <env.h> +#include <u-boot/crc.h> +#include <hash.h> #include <init.h> #include <log.h> #include <asm/arch-rockchip/periph.h> +#include <asm/setup.h> +#include <u-boot/sha256.h> #include <power/regulator.h> +#define RK3399_CPUID_OFF 0x7 +#define RK3399_CPUID_LEN 0x10 + #ifndef CONFIG_SPL_BUILD int board_early_init_f(void) { @@ -30,3 +39,114 @@ out: return 0; } #endif +static void setup_macaddr(void) +{ + if (!IS_ENABLED(CONFIG_CMD_NET)) + return; + + int ret; + const char *cpuid = env_get("cpuid#"); + u8 hash[SHA256_SUM_LEN]; + int size = sizeof(hash); + u8 mac_addr[6]; + + /* Only generate a MAC address if none is set in the environment */ + if (env_get("ethaddr")) + return; + + if (!cpuid) { + debug("%s: could not retrieve 'cpuid#'\n", __func__); + return; + } + + ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size); + if (ret) { + debug("%s: failed to calculate SHA256\n", __func__); + return; + } + + /* Copy 6 bytes of the hash to base the MAC address on */ + memcpy(mac_addr, hash, 6); + + /* Make this a valid MAC address and set it */ + mac_addr[0] &= 0xfe; /* clear multicast bit */ + mac_addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ + eth_env_set_enetaddr("ethaddr", mac_addr); +} + +static void setup_serial(void) +{ + if (!IS_ENABLED(CONFIG_ROCKCHIP_EFUSE)) + return; + + struct udevice *dev; + int ret, i; + u8 cpuid[RK3399_CPUID_LEN]; + u8 low[RK3399_CPUID_LEN / 2], high[RK3399_CPUID_LEN / 2]; + char cpuid_str[RK3399_CPUID_LEN * 2 + 1]; + u64 serialno; + char serialno_str[16]; + + /* retrieve the device */ + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_efuse), &dev); + if (ret) { + debug("%s: could not find efuse device\n", __func__); + return; + } + + /* read the cpu_id range from the efuses */ + ret = misc_read(dev, RK3399_CPUID_OFF, &cpuid, sizeof(cpuid)); + if (ret) { + debug("%s: reading cpuid from the efuses failed\n", + __func__); + return; + } + + memset(cpuid_str, 0, sizeof(cpuid_str)); + for (i = 0; i < 16; i++) + sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]); + + debug("cpuid: %s\n", cpuid_str); + + /* + * Mix the cpuid bytes using the same rules as in + * ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c + */ + for (i = 0; i < 8; i++) { + low[i] = cpuid[1 + (i << 1)]; + high[i] = cpuid[i << 1]; + } + + serialno = crc32_no_comp(0, low, 8); + serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32; + snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno); + + env_set("cpuid#", cpuid_str); + env_set("serial#", serialno_str); +} + +int misc_init_r(void) +{ + setup_serial(); + setup_macaddr(); + + return 0; +} + +void get_board_serial(struct tag_serialnr *serialnr) +{ + u64 serial = 0; + + if (IS_ENABLED(CONFIG_SERIAL_TAG)) { + char *serial_string; + + serial_string = env_get("serial#"); + + if (serial_string) + serial = simple_strtoull(serial_string, NULL, 16); + } + + serialnr->high = (u32)(serial >> 32); + serialnr->low = (u32)(serial & 0xffffffff); +} diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig index 46ba07f4d5..aa89ac5854 100644 --- a/configs/nanopi-r4s-rk3399_defconfig +++ b/configs/nanopi-r4s-rk3399_defconfig @@ -63,3 +63,7 @@ CONFIG_VIDEO_ROCKCHIP=y CONFIG_DISPLAY_ROCKCHIP_HDMI=y CONFIG_SPL_TINY_MEMSET=y CONFIG_ERRNO_STR=y +CONFIG_MISC=y +CONFIG_MISC_INIT_R=y +CONFIG_ROCKCHIP_EFUSE=y +CONFIG_ROCKCHIP_OTP=y diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index b9c54bdd99..a2ce9e737c 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -64,7 +64,7 @@ obj-$(CONFIG_QFW_PIO) += qfw_pio.o obj-$(CONFIG_QFW_MMIO) += qfw_mmio.o obj-$(CONFIG_SANDBOX) += qfw_sandbox.o endif -obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o +obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o misc-uclass.o obj-$(CONFIG_ROCKCHIP_OTP) += rockchip-otp.o obj-$(CONFIG_SANDBOX) += syscon_sandbox.o misc_sandbox.o obj-$(CONFIG_SIFIVE_OTP) += sifive-otp.o -- 2.36.2

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[PATCH v1] ARM: imx8mp: verdin-imx8mp: Add memory size detection
by Francesco Dolcini 28 Sep '22

28 Sep '22

Add RAM auto-sizing, without this change memory size for all SKU is set to 8GB and the system will crash on SKU with less memory as soon as the non existent memory addresses are accessed. Fixes: 2bc2f817cea7 ("board: toradex: add verdin imx8m plus support") Signed-off-by: Francesco Dolcini <francesco.dolcini(a)toradex.com> --- board/toradex/verdin-imx8mp/verdin-imx8mp.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c index e3c1a1201daa..743e00bf9c46 100644 --- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c +++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c @@ -121,6 +121,16 @@ int board_late_init(void) return 0; } +int board_phys_sdram_size(phys_size_t *size) +{ + if (!size) + return -EINVAL; + + *size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE); + + return 0; +} + #if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { -- 2.25.1

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