September 2022 - U-Boot

[RFC PATCH 0/4] Alternative debug outputs for rockchip devices
by Marty E. Plummer 29 Sep '22

29 Sep '22

I don't intend for the last change to be included in mainline, I just need some form of serial output to see why archlinuxarm, alpine linux, and Fedora workstation all fail to boot on this hardware (rk3399-gru-kevin). Or at least, I think its failing. At the point of booting the kernel the bottom inch or so of the screen corrupts a bit and then nothing. It could be working, but without output on screen or uart2dbga I have no idea what is going wrong. I *would* use the uart-to-usb functionality of the rk3399, but as far as I know this only works with the 2.0, and I'm not sure if those are available on the rk3399-gru-kevin's type c ports. Do correct me if I'm wrong. In addition, the GRF_SOC_CON7:grf_uart_dbg_sel is, as far as I know, undocumented, outside of the GRF_UART_DBG_SEL_C enum in grf_rk3399, so the other two options (A and B) are just based on my assumptions. If someone who *actually knows* could elaborate on it and correct me if needed I'd greatly appreciate it. Marty E. Plummer (4): rockchip: rk3288: enable u-boot.rom for speedy rockchip: rk3288: enable uart2->usb redirection rockchip: rk3399: fix typo in grf file rockchip: rk3399: attempt to redirect uart2dbga to sdcard arch/arm/dts/rk3399-gru.dtsi | 7 +--- arch/arm/dts/rk3399.dtsi | 4 +- .../include/asm/arch-rockchip/grf_rk3288.h | 41 +++++++++++++++++++ .../include/asm/arch-rockchip/grf_rk3399.h | 5 ++- arch/arm/mach-rockchip/rk3288/Kconfig | 2 + arch/arm/mach-rockchip/rk3288/rk3288.c | 20 +++++++++ arch/arm/mach-rockchip/rk3399/rk3399.c | 18 ++++---- 7 files changed, 80 insertions(+), 17 deletions(-) -- 2.37.3

2 9

[PATCH] smbios: dts: Add "asset-tag" property to "enclosure" subnode
by Christian Kohlschütter 29 Sep '22

29 Sep '22

Currently, device trees can only specify an asset tag for the "baseboard" type, not for the "chassis" (system enclosure) type, which usually carries the more user-visible asset tag. Add support for the chassis asset-tag, and update the documentation. Signed-off-by: Christian Kohlschütter <christian(a)kohlschutter.com> --- doc/device-tree-bindings/sysinfo/smbios.txt | 4 ++++ lib/smbios.c | 1 + 2 files changed, 5 insertions(+) diff --git a/doc/device-tree-bindings/sysinfo/smbios.txt b/doc/device-tree-bindings/sysinfo/smbios.txt index b522322802..2c1c9abf7c 100644 --- a/doc/device-tree-bindings/sysinfo/smbios.txt +++ b/doc/device-tree-bindings/sysinfo/smbios.txt @@ -44,6 +44,9 @@ Within each subnode the following tables are recognised: "chassis" subnode optional properties: - manufacturer: Product manufacturer for chassis + - asset-tag: Asset tag for the system enclosure, sometimes used in + organisations to track devices + Example: @@ -72,6 +75,7 @@ sysinfo { /* Type 3 table */ chassis { manufacturer = "Google"; + asset-tag = "XYZ789"; }; }; }; diff --git a/lib/smbios.c b/lib/smbios.c index d7f4999e8b..8f8f160882 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -347,6 +347,7 @@ static int smbios_write_type3(ulong *current, int handle, if (!t->manufacturer) t->manufacturer = smbios_add_string(ctx, "Unknown"); t->chassis_type = SMBIOS_ENCLOSURE_DESKTOP; + t->asset_tag_number = smbios_add_prop(ctx, "asset-tag"); t->bootup_state = SMBIOS_STATE_SAFE; t->power_supply_state = SMBIOS_STATE_SAFE; t->thermal_state = SMBIOS_STATE_SAFE; -- 2.36.2

2 1

[PATCH 00/21] Finish migration to DM_ETH
by Tom Rini 28 Sep '22

28 Sep '22

As I've noted before, with v2022.07 being released, we have gone 2 years past the DM_ETH migration deadline. What this series does is a few things: - Remove some boards that either lack DM migration at all, or lack OF_CONTROL. DM migration has had an explicit deadline, and OF_CONTROL an implict one. - Remove some un-migrated ethernet drivers. I had reached out in private to some people about this and they had hoped to have done the conversion by now. Unfortunately, here we now are. - Perform some minor forceful migrations on boards. These boards use OF_CONTROL and drivers which use DM_ETH, so I am hopeful that just removing or guarding the code here is fine and works. - Disable networkgin on some other boards. Unlike boards in the above case, it looks like the board code itself needs some updates, as was done on the platforms that have already been migrated. - Finally, select DM_ETH for all NETDEVICES and update dependencies. This series depends on https://patchwork.ozlabs.org/project/uboot/patch/8ae444f17dc5db69a1da809875… being applied and in practical terms depennds on my current outstanding Kconfig migrations as well. -- Tom

7 65

[PATCH v2] crypto/fsl: Add support for black key blob
by Gaurav Jain 28 Sep '22

28 Sep '22

modified caam descriptor to support black key blob. Signed-off-by: Gaurav Jain <gaurav.jain(a)nxp.com> --- changes in v2: - rebase to latest cmd/blob.c | 12 ++++++++---- drivers/crypto/fsl/desc.h | 1 + drivers/crypto/fsl/fsl_blob.c | 21 +++++++++++++-------- drivers/crypto/fsl/jobdesc.c | 24 +++++++++++++++++++----- drivers/crypto/fsl/jobdesc.h | 8 ++++++-- 5 files changed, 47 insertions(+), 19 deletions(-) diff --git a/cmd/blob.c b/cmd/blob.c index e2efae7a11..5c459b6f19 100644 --- a/cmd/blob.c +++ b/cmd/blob.c @@ -21,10 +21,12 @@ * @src: - Address of data to be decapsulated * @dst: - Address of data to be decapsulated * @len: - Size of data to be decapsulated + * @keycolor - Determines if the source data is covered (black key) or + * plaintext. * * Returns zero on success,and negative on error. */ -__weak int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) +__weak int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len, u8 keycolor) { return 0; } @@ -35,10 +37,12 @@ __weak int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) * @src: - Address of data to be encapsulated * @dst: - Address of data to be encapsulated * @len: - Size of data to be encapsulated + * @keycolor - Determines if the source data is covered (black key) or + * plaintext. * * Returns zero on success,and negative on error. */ -__weak int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len) +__weak int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len, u8 keycolor) { return 0; } @@ -91,9 +95,9 @@ static int do_blob(struct cmd_tbl *cmdtp, int flag, int argc, #endif if (enc) - ret = blob_encap(km_ptr, src_ptr, dst_ptr, len); + ret = blob_encap(km_ptr, src_ptr, dst_ptr, len, 0); else - ret = blob_decap(km_ptr, src_ptr, dst_ptr, len); + ret = blob_decap(km_ptr, src_ptr, dst_ptr, len, 0); return ret; } diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h index 5705c4f944..4c148a2fc4 100644 --- a/drivers/crypto/fsl/desc.h +++ b/drivers/crypto/fsl/desc.h @@ -435,6 +435,7 @@ /* Assuming OP_TYPE = OP_TYPE_UNI_PROTOCOL */ #define OP_PCLID_SECMEM 0x08 #define OP_PCLID_BLOB (0x0d << OP_PCLID_SHIFT) +#define OP_PCL_BLOB_BLACK 0x0004 #define OP_PCLID_SECRETKEY (0x11 << OP_PCLID_SHIFT) #define OP_PCLID_PUBLICKEYPAIR (0x14 << OP_PCLID_SHIFT) #define OP_PCLID_DSA_SIGN (0x15 << OP_PCLID_SHIFT) diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c index 9b6e4bca06..034e6ae5df 100644 --- a/drivers/crypto/fsl/fsl_blob.c +++ b/drivers/crypto/fsl/fsl_blob.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2022 NXP * */ @@ -22,13 +23,15 @@ * @src: - Source address (blob) * @dst: - Destination address (data) * @len: - Size of decapsulated data + * @keycolor - Determines if the source data is covered (black key) or + * plaintext. * * Note: Start and end of the key_mod, src and dst buffers have to be aligned to * the cache line size (ARCH_DMA_MINALIGN) for the CAAM operation to succeed. * * Returns zero on success, negative on error. */ -int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) +int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len, u8 keycolor) { int ret, size, i = 0; u32 *desc; @@ -55,7 +58,7 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) flush_dcache_range((unsigned long)src, (unsigned long)src + size); - inline_cnstr_jobdesc_blob_decap(desc, key_mod, src, dst, len); + inline_cnstr_jobdesc_blob_decap(desc, key_mod, src, dst, len, keycolor); debug("Descriptor dump:\n"); for (i = 0; i < 14; i++) @@ -65,8 +68,8 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) flush_dcache_range((unsigned long)desc, (unsigned long)desc + size); - flush_dcache_range((unsigned long)dst, - (unsigned long)dst + size); + size = ALIGN(len, ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)dst, (unsigned long)dst + size); ret = run_descriptor_jr(desc); @@ -94,13 +97,15 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) * @src: - Source address (data) * @dst: - Destination address (blob) * @len: - Size of data to be encapsulated + * @keycolor - Determines if the source data is covered (black key) or + * plaintext. * * Note: Start and end of the key_mod, src and dst buffers have to be aligned to * the cache line size (ARCH_DMA_MINALIGN) for the CAAM operation to succeed. * * Returns zero on success, negative on error. */ -int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len) +int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len, u8 keycolor) { int ret, size, i = 0; u32 *desc; @@ -127,7 +132,7 @@ int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len) flush_dcache_range((unsigned long)src, (unsigned long)src + size); - inline_cnstr_jobdesc_blob_encap(desc, key_mod, src, dst, len); + inline_cnstr_jobdesc_blob_encap(desc, key_mod, src, dst, len, keycolor); debug("Descriptor dump:\n"); for (i = 0; i < 14; i++) @@ -137,8 +142,8 @@ int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len) flush_dcache_range((unsigned long)desc, (unsigned long)desc + size); - flush_dcache_range((unsigned long)dst, - (unsigned long)dst + size); + size = ALIGN(BLOB_SIZE(len), ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)dst, (unsigned long)dst + size); ret = run_descriptor_jr(desc); diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index 542b1652d8..1280e6122e 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -4,7 +4,7 @@ * Basic job descriptor construction * * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018, 2022 NXP * */ @@ -210,13 +210,14 @@ void inline_cnstr_jobdesc_hash(uint32_t *desc, #ifndef CONFIG_SPL_BUILD void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr, uint8_t *plain_txt, uint8_t *enc_blob, - uint32_t in_sz) + uint32_t in_sz, uint8_t keycolor) { caam_dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out; uint32_t key_sz = KEY_IDNFR_SZ_BYTES; /* output blob will have 32 bytes key blob in beginning and * 16 byte HMAC identifier at end of data blob */ uint32_t out_sz = in_sz + KEY_BLOB_SIZE + MAC_SIZE; + uint32_t bk_store; dma_addr_key_idnfr = virt_to_phys((void *)key_idnfr); dma_addr_in = virt_to_phys((void *)plain_txt); @@ -230,16 +231,23 @@ void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr, append_seq_out_ptr(desc, dma_addr_out, out_sz, 0); - append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB); + bk_store = OP_PCLID_BLOB; + + /* An input black key cannot be stored in a red blob */ + if (keycolor == BLACK_KEY) + bk_store |= OP_PCL_BLOB_BLACK; + + append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | bk_store); } void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr, uint8_t *enc_blob, uint8_t *plain_txt, - uint32_t out_sz) + uint32_t out_sz, uint8_t keycolor) { caam_dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out; uint32_t key_sz = KEY_IDNFR_SZ_BYTES; uint32_t in_sz = out_sz + KEY_BLOB_SIZE + MAC_SIZE; + uint32_t bk_store; dma_addr_key_idnfr = virt_to_phys((void *)key_idnfr); dma_addr_in = virt_to_phys((void *)enc_blob); @@ -253,7 +261,13 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr, append_seq_out_ptr(desc, dma_addr_out, out_sz, 0); - append_operation(desc, OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB); + bk_store = OP_PCLID_BLOB; + + /* An input black key cannot be stored in a red blob */ + if (keycolor == BLACK_KEY) + bk_store |= OP_PCL_BLOB_BLACK; + + append_operation(desc, OP_TYPE_DECAP_PROTOCOL | bk_store); } #endif /* diff --git a/drivers/crypto/fsl/jobdesc.h b/drivers/crypto/fsl/jobdesc.h index c4501abd26..99ac049c3e 100644 --- a/drivers/crypto/fsl/jobdesc.h +++ b/drivers/crypto/fsl/jobdesc.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2022 NXP * */ @@ -13,6 +14,9 @@ #define KEY_IDNFR_SZ_BYTES 16 +/* Encrypted key */ +#define BLACK_KEY 1 + #ifdef CONFIG_CMD_DEKBLOB /* inline_cnstr_jobdesc_blob_dek: * Intializes and constructs the job descriptor for DEK encapsulation @@ -33,11 +37,11 @@ void inline_cnstr_jobdesc_hash(uint32_t *desc, void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr, uint8_t *plain_txt, uint8_t *enc_blob, - uint32_t in_sz); + uint32_t in_sz, uint8_t keycolor); void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr, uint8_t *enc_blob, uint8_t *plain_txt, - uint32_t out_sz); + uint32_t out_sz, uint8_t keycolor); void inline_cnstr_jobdesc_rng_instantiation(u32 *desc, int handle, int do_sk); -- 2.25.1

2 1

[RFC PATCH v2] clk: fix clk_get_rate() always return ulong
by Julien Masson 28 Sep '22

28 Sep '22

According to clk_ops struct definition, the callback `get_rate()` return current clock rate value as ulong. `clk_get_rate()` should handle the clock rate returned as ulong also. Otherwise we may have invalid/truncated clock rate value returned by `clk_get_rate()`. `log_ret` has also been removed since it use an `int` in the macro definition. Signed-off-by: Julien Masson <jmasson(a)baylibre.com> --- drivers/clk/clk-uclass.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index b89c77bf79..c351fa97d1 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -469,7 +469,7 @@ void clk_free(struct clk *clk) ulong clk_get_rate(struct clk *clk) { const struct clk_ops *ops; - int ret; + ulong ret; debug("%s(clk=%p)\n", __func__, clk); if (!clk_valid(clk)) @@ -479,11 +479,7 @@ ulong clk_get_rate(struct clk *clk) if (!ops->get_rate) return -ENOSYS; - ret = ops->get_rate(clk); - if (ret) - return log_ret(ret); - - return 0; + return ops->get_rate(clk); } struct clk *clk_get_parent(struct clk *clk) -- 2.37.2

3 3

[PATCH v2 00/14] SCMI multi-channel and optee shm
by Etienne Carriere 28 Sep '22

28 Sep '22

Dear all, This series implements 2 features in driver/firmware/scmi. First, a single change adds support for SCMI OP-TEE transport to use OP-TEE native shared memory. See the 1st patch in this series: "firmware: scmi: optee: use TEE shared memory for SCMI messages". Then come changes for supporting multi-channel in the SCMI drivers. I've split the implementation in 11 several small incremental changes in the hope it helps the review. Few minor fixup commits are also inserted in the series. Changes since v1: - Update scmi_clk.c, scmi_reset.c and scmi_regulator.c to store SCMI channel reference in private data rather than using private data reference as an opaque reference to the target SCMI channel. Etienne Carriere (14): firmware: scmi: optee: use TEE shared memory for SCMI messages firmware: scmi: optee: fix inline description of PTA_SCMI_CMD_GET_CHANNEL firmware: scmi: prepare scmi uclass API to multi-channel firmware: scmi: prepare uclass to pass channel reference firmware: scmi: factorize scmi transport look up firmware: scmi: add multi-channel support firmware: scmi: mailbox transport: implement multi-channel firmware: scmi: smccc transport: implement multi-channel firmware: scmi: optee transport: implement multi-channel clk: scmi: support SCMI multi-channel reset: scmi: support SCMI multi-channel power: regulator: scmi: support SCMI multi-channel power: regulator: scmi: simplify scmi_voltd_set_enable() firmware: scmi: use multi channel in mailbox, optee and smccc agents drivers/clk/clk_scmi.c | 33 ++++- drivers/firmware/scmi/mailbox_agent.c | 65 +++++++-- drivers/firmware/scmi/optee_agent.c | 147 ++++++++++++++++----- drivers/firmware/scmi/sandbox-scmi_agent.c | 1 + drivers/firmware/scmi/scmi_agent-uclass.c | 48 +++++-- drivers/firmware/scmi/smccc_agent.c | 56 +++++++- drivers/firmware/scmi/smt.c | 53 +++++++- drivers/firmware/scmi/smt.h | 45 ++++++- drivers/power/regulator/scmi_regulator.c | 36 +++-- drivers/reset/reset-scmi.c | 25 +++- include/scmi_agent-uclass.h | 15 ++- include/scmi_agent.h | 14 +- 12 files changed, 458 insertions(+), 80 deletions(-) -- 2.25.1

4 18

[PATCH 1/9] drivers: clk: dm: Add clock driver for Diamond Mesa
by Jit Loon Lim 28 Sep '22

28 Sep '22

From: Siew Chin Lim <elly.siew.chin.lim(a)intel.com> Add clock manager driver for Diamond Mesa. Provides clock initialization and get_rate functions. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim(a)intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim(a)intel.com> --- drivers/clk/altera/clk-dm.c | 504 +++++++++++++++++++++++++++ drivers/clk/altera/clk-dm.h | 217 ++++++++++++ include/dt-bindings/clock/dm-clock.h | 71 ++++ 3 files changed, 792 insertions(+) create mode 100644 drivers/clk/altera/clk-dm.c create mode 100644 drivers/clk/altera/clk-dm.h create mode 100644 include/dt-bindings/clock/dm-clock.h diff --git a/drivers/clk/altera/clk-dm.c b/drivers/clk/altera/clk-dm.c new file mode 100644 index 0000000000..1076240b41 --- /dev/null +++ b/drivers/clk/altera/clk-dm.c @@ -0,0 +1,504 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 Intel Corporation <www.intel.com> + */ + +#include <common.h> +#include <asm/arch/clock_manager.h> +#include <asm/io.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/lists.h> +#include <dm/util.h> +#include <dt-bindings/clock/dm-clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct socfpga_clk_plat { + void __iomem *regs; +}; + +/* + * function to write the bypass register which requires a poll of the + * busy bit + */ +static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val) +{ + CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS); + cm_wait_for_fsm(); +} + +static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val) +{ + CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS); + cm_wait_for_fsm(); +} + +#ifndef CONFIG_TARGET_SOCFPGA_DM +/* function to write the ctrl register which requires a poll of the busy bit */ +static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val) +{ + CM_REG_WRITEL(plat, val, CLKMGR_CTRL); + cm_wait_for_fsm(); +} +#endif + +/* + * Setup clocks while making no assumptions about previous state of the clocks. + */ +static void clk_basic_init(struct udevice *dev, + const struct cm_config * const cfg) +{ + struct socfpga_clk_plat *plat = dev_get_plat(dev); + + if (!cfg) + return; + +#ifndef CONFIG_TARGET_SOCFPGA_DM +#ifdef CONFIG_SPL_BUILD + /* Always force clock manager into boot mode before any configuration */ + clk_write_ctrl(plat, + CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE); +#else + /* Skip clock configuration in SSBL if it's not in boot mode */ + if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE)) + return; +#endif +#endif + + /* Put both PLLs in bypass */ + clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL); + clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL); + + /* Put both PLLs in Reset */ + CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLCTRL, + CLKMGR_PLLCTRL_BYPASS_MASK); + CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLCTRL, + CLKMGR_PLLCTRL_BYPASS_MASK); + +#ifndef CONFIG_TARGET_SOCFPGA_DM + /* setup main PLL */ + CM_REG_WRITEL(plat, cfg->main_pll_pllglob, CLKMGR_MAINPLL_PLLGLOB); + CM_REG_WRITEL(plat, cfg->main_pll_plldiv, CLKMGR_MAINPLL_PLLDIV); + CM_REG_WRITEL(plat, cfg->main_pll_plloutdiv, CLKMGR_MAINPLL_PLLOUTDIV); + CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK); + CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK); + CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV); + + /* setup peripheral */ + CM_REG_WRITEL(plat, cfg->per_pll_pllglob, CLKMGR_PERPLL_PLLGLOB); + CM_REG_WRITEL(plat, cfg->per_pll_plldiv, CLKMGR_PERPLL_PLLDIV); + CM_REG_WRITEL(plat, cfg->per_pll_plloutdiv, CLKMGR_PERPLL_PLLOUTDIV); + CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL); + CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV); +#endif + + /* Take both PLL out of reset and power up */ + CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLCTRL, + CLKMGR_PLLCTRL_BYPASS_MASK); + CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLCTRL, + CLKMGR_PLLCTRL_BYPASS_MASK); + + cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK); + +#ifndef CONFIG_TARGET_SOCFPGA_DM + CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR); + CM_REG_WRITEL(plat, cfg->alt_emacbctr, CLKMGR_ALTR_EMACBCTR); + CM_REG_WRITEL(plat, cfg->alt_emacptpctr, CLKMGR_ALTR_EMACPTPCTR); + CM_REG_WRITEL(plat, cfg->alt_gpiodbctr, CLKMGR_ALTR_GPIODBCTR); + CM_REG_WRITEL(plat, cfg->alt_sdmmcctr, CLKMGR_ALTR_SDMMCCTR); + CM_REG_WRITEL(plat, cfg->alt_s2fuser0ctr, CLKMGR_ALTR_S2FUSER0CTR); + CM_REG_WRITEL(plat, cfg->alt_s2fuser1ctr, CLKMGR_ALTR_S2FUSER1CTR); + CM_REG_WRITEL(plat, cfg->alt_psirefctr, CLKMGR_ALTR_PSIREFCTR); +#endif + + /* Configure ping pong counters in altera group */ + CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_MAINPLL_LOSTLOCK); + CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_PERPLL_LOSTLOCK); + + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLGLOB) | + CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK, + CLKMGR_MAINPLL_PLLGLOB); + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLGLOB) | + CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK, + CLKMGR_PERPLL_PLLGLOB); + + /* Take all PLLs out of bypass */ + clk_write_bypass_mainpll(plat, 0); + clk_write_bypass_perpll(plat, 0); + + /* Clear the loss of lock bits (write 1 to clear) */ + CM_REG_CLRBITS(plat, CLKMGR_INTRCLR, + CLKMGR_INTER_PERPLLLOST_MASK | + CLKMGR_INTER_MAINPLLLOST_MASK); + + /* Take all ping pong counters out of reset */ + CM_REG_CLRBITS(plat, CLKMGR_ALTR_EXTCNTRST, + CLKMGR_ALT_EXTCNTRST_ALLCNTRST_MASK); + +#ifndef CONFIG_TARGET_SOCFPGA_DM + /* Out of boot mode */ + clk_write_ctrl(plat, + CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE); +#endif +} + +static u32 clk_get_5_1_clk_src(struct socfpga_clk_plat *plat, u32 reg) +{ + u32 clksrc = CM_REG_READL(plat, reg); + + return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET; +} + +static u64 clk_get_pll_output_hz(struct socfpga_clk_plat *plat, + u32 pllglob_reg, u32 plldiv_reg) +{ + u64 clock = 0; + u32 clklsrc, divf, divr, divq, power = 1; + + /* Get input clock frequency */ + clklsrc = (CM_REG_READL(plat, pllglob_reg) & + CLKMGR_PLLGLOB_VCO_PSRC_MASK) >> + CLKMGR_PLLGLOB_VCO_PSRC_OFFSET; + + switch (clklsrc) { + case CLKMGR_VCO_PSRC_EOSC1: + clock = cm_get_osc_clk_hz(); + break; + case CLKMGR_VCO_PSRC_INTOSC: + clock = cm_get_intosc_clk_hz(); + break; + case CLKMGR_VCO_PSRC_F2S: + clock = cm_get_fpga_clk_hz(); + break; + } + + /* Calculate pll out clock frequency */ + divf = (CM_REG_READL(plat, plldiv_reg) & + CLKMGR_PLLDIV_FDIV_MASK) >> + CLKMGR_PLLDIV_FDIV_OFFSET; + + divr = (CM_REG_READL(plat, plldiv_reg) & + CLKMGR_PLLDIV_REFCLKDIV_MASK) >> + CLKMGR_PLLDIV_REFCLKDIV_OFFSET; + + divq = (CM_REG_READL(plat, plldiv_reg) & + CLKMGR_PLLDIV_OUTDIV_QDIV_MASK) >> + CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET; + + while (divq) { + power *= 2; + divq--; + } + + return ((clock * 2 * (divf + 1)) / ((divr + 1) * power)); +} + +static u64 clk_get_clksrc_hz(struct socfpga_clk_plat *plat, u32 clksrc_reg, + u32 main_div, u32 per_div) +{ + u64 clock = 0; + u32 clklsrc = clk_get_5_1_clk_src(plat, clksrc_reg); + + switch (clklsrc) { + case CLKMGR_CLKSRC_MAIN: + clock = clk_get_pll_output_hz(plat, + CLKMGR_MAINPLL_PLLGLOB, + CLKMGR_MAINPLL_PLLDIV); + clock /= 1 + main_div; + break; + + case CLKMGR_CLKSRC_PER: + clock = clk_get_pll_output_hz(plat, + CLKMGR_PERPLL_PLLGLOB, + CLKMGR_PERPLL_PLLDIV); + clock /= 1 + per_div; + break; + + case CLKMGR_CLKSRC_OSC1: + clock = cm_get_osc_clk_hz(); + break; + + case CLKMGR_CLKSRC_INTOSC: + clock = cm_get_intosc_clk_hz(); + break; + + case CLKMGR_CLKSRC_FPGA: + clock = cm_get_fpga_clk_hz(); + break; + default: + return 0; + } + + return clock; +} + +static u64 clk_get_mpu_clk_hz(struct socfpga_clk_plat *plat) +{ + u32 mainpll_c0cnt = (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLOUTDIV) & + CLKMGR_PLLOUTDIV_C0CNT_MASK) >> + CLKMGR_PLLOUTDIV_C0CNT_OFFSET; + + u32 perpll_c0cnt = (CM_REG_READL(plat, CLKMGR_PERPLL_PLLOUTDIV) & + CLKMGR_PLLOUTDIV_C0CNT_MASK) >> + CLKMGR_PLLOUTDIV_C0CNT_OFFSET; + + u64 clock = clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_MPUCLK, + mainpll_c0cnt, perpll_c0cnt); + + clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_MPUCLK) & + CLKMGR_CLKCNT_MSK); + + return clock; +} + +static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_plat *plat) +{ + u32 mainpll_c1cnt = (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLOUTDIV) & + CLKMGR_PLLOUTDIV_C1CNT_MASK) >> + CLKMGR_PLLOUTDIV_C1CNT_OFFSET; + + u32 perpll_c1cnt = (CM_REG_READL(plat, CLKMGR_PERPLL_PLLOUTDIV) & + CLKMGR_PLLOUTDIV_C1CNT_MASK) >> + CLKMGR_PLLOUTDIV_C1CNT_OFFSET; + + return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK, + mainpll_c1cnt, perpll_c1cnt); +} + +static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_plat *plat) +{ + u64 clock = clk_get_l3_main_clk_hz(plat); + + clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >> + CLKMGR_NOCDIV_L4MAIN_OFFSET) & + CLKMGR_NOCDIV_DIVIDER_MASK); + + return clock; +} + +static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_plat *plat) +{ + u32 mainpll_c3cnt = (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLOUTDIV) & + CLKMGR_PLLOUTDIV_C3CNT_MASK) >> + CLKMGR_PLLOUTDIV_C3CNT_OFFSET; + + u32 perpll_c3cnt = (CM_REG_READL(plat, CLKMGR_PERPLL_PLLOUTDIV) & + CLKMGR_PLLOUTDIV_C3CNT_MASK) >> + CLKMGR_PLLOUTDIV_C3CNT_OFFSET; + + u64 clock = clk_get_clksrc_hz(plat, CLKMGR_ALTR_SDMMCCTR, + mainpll_c3cnt, perpll_c3cnt); + + clock /= 1 + (CM_REG_READL(plat, CLKMGR_ALTR_SDMMCCTR) & + CLKMGR_CLKCNT_MSK); + + return clock / 4; +} + +#ifndef CONFIG_TARGET_SOCFPGA_DM +static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_plat *plat) +{ + u64 clock = clk_get_l3_main_clk_hz(plat); + + clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >> + CLKMGR_NOCDIV_L4SPCLK_OFFSET) & + CLKMGR_NOCDIV_DIVIDER_MASK); + + return clock; +} +#endif + +static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_plat *plat) +{ + u64 clock = clk_get_l3_main_clk_hz(plat); + + clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >> + CLKMGR_NOCDIV_L4MPCLK_OFFSET) & + CLKMGR_NOCDIV_DIVIDER_MASK); + + return clock; +} + +static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_plat *plat) +{ + if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE) + return clk_get_l3_main_clk_hz(plat) / 2; + + return clk_get_l3_main_clk_hz(plat) / 4; +} + +static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id) +{ + bool emacsel_a; + u32 ctl; + u32 ctr_reg; + u32 clock; + u32 div; + u32 reg; + + /* Get EMAC clock source */ + ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL); + if (emac_id == DM_EMAC0_CLK) + ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) & + CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK; + else if (emac_id == DM_EMAC1_CLK) + ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) & + CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK; + else if (emac_id == DM_EMAC2_CLK) + ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) & + CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK; + else + return 0; + + if (ctl) { + /* EMAC B source */ + emacsel_a = false; + ctr_reg = CLKMGR_ALTR_EMACBCTR; + } else { + /* EMAC A source */ + emacsel_a = true; + ctr_reg = CLKMGR_ALTR_EMACACTR; + } + + reg = CM_REG_READL(plat, ctr_reg); + clock = (reg & CLKMGR_ALT_EMACCTR_SRC_MASK) + >> CLKMGR_ALT_EMACCTR_SRC_OFFSET; + div = (reg & CLKMGR_ALT_EMACCTR_CNT_MASK) + >> CLKMGR_ALT_EMACCTR_CNT_OFFSET; + + switch (clock) { + case CLKMGR_CLKSRC_MAIN: + clock = clk_get_pll_output_hz(plat, + CLKMGR_MAINPLL_PLLGLOB, + CLKMGR_MAINPLL_PLLDIV); + + if (emacsel_a) { + clock /= 1 + ((CM_REG_READL(plat, + CLKMGR_MAINPLL_PLLOUTDIV) & + CLKMGR_PLLOUTDIV_C2CNT_MASK) >> + CLKMGR_PLLOUTDIV_C2CNT_OFFSET); + } else { + clock /= 1 + ((CM_REG_READL(plat, + CLKMGR_MAINPLL_PLLOUTDIV) & + CLKMGR_PLLOUTDIV_C3CNT_MASK) >> + CLKMGR_PLLOUTDIV_C3CNT_OFFSET); + } + break; + + case CLKMGR_CLKSRC_PER: + clock = clk_get_pll_output_hz(plat, + CLKMGR_PERPLL_PLLGLOB, + CLKMGR_PERPLL_PLLDIV); + if (emacsel_a) { + clock /= 1 + ((CM_REG_READL(plat, + CLKMGR_PERPLL_PLLOUTDIV) & + CLKMGR_PLLOUTDIV_C2CNT_MASK) >> + CLKMGR_PLLOUTDIV_C2CNT_OFFSET); + } else { + clock /= 1 + ((CM_REG_READL(plat, + CLKMGR_PERPLL_PLLOUTDIV) & + CLKMGR_PLLOUTDIV_C3CNT_MASK >> + CLKMGR_PLLOUTDIV_C3CNT_OFFSET)); + } + break; + + case CLKMGR_CLKSRC_OSC1: + clock = cm_get_osc_clk_hz(); + break; + + case CLKMGR_CLKSRC_INTOSC: + clock = cm_get_intosc_clk_hz(); + break; + + case CLKMGR_CLKSRC_FPGA: + clock = cm_get_fpga_clk_hz(); + break; + } + + clock /= 1 + div; + + return clock; +} + +static ulong socfpga_clk_get_rate(struct clk *clk) +{ + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev); + + switch (clk->id) { + case DM_MPU_CLK: + return clk_get_mpu_clk_hz(plat); + case DM_L4_MAIN_CLK: + return clk_get_l4_main_clk_hz(plat); + case DM_L4_SYS_FREE_CLK: + return clk_get_l4_sys_free_clk_hz(plat); + case DM_L4_MP_CLK: + return clk_get_l4_mp_clk_hz(plat); + case DM_L4_SP_CLK: +#ifndef CONFIG_TARGET_SOCFPGA_DM + return clk_get_l4_sp_clk_hz(plat); +#else + return 76800; +#endif + case DM_SDMMC_CLK: + return clk_get_sdmmc_clk_hz(plat); + case DM_EMAC0_CLK: + case DM_EMAC1_CLK: + case DM_EMAC2_CLK: + return clk_get_emac_clk_hz(plat, clk->id); + case DM_USB_CLK: + case DM_NAND_X_CLK: + return clk_get_l4_mp_clk_hz(plat); + case DM_NAND_CLK: + return clk_get_l4_mp_clk_hz(plat) / 4; + default: + return -ENXIO; + } +} + +static int socfpga_clk_enable(struct clk *clk) +{ + return 0; +} + +static int socfpga_clk_probe(struct udevice *dev) +{ + const struct cm_config *cm_default_cfg = cm_get_default_config(); + + clk_basic_init(dev, cm_default_cfg); + + return 0; +} + +static int socfpga_clk_of_to_plat(struct udevice *dev) +{ + struct socfpga_clk_plat *plat = dev_get_plat(dev); + fdt_addr_t addr; + + addr = devfdt_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + plat->regs = (void __iomem *)addr; + + return 0; +} + +static struct clk_ops socfpga_clk_ops = { + .enable = socfpga_clk_enable, + .get_rate = socfpga_clk_get_rate, +}; + +static const struct udevice_id socfpga_clk_match[] = { + { .compatible = "intel,dm-clkmgr" }, + {} +}; + +U_BOOT_DRIVER(socfpga_dm_clk) = { + .name = "clk-dm", + .id = UCLASS_CLK, + .of_match = socfpga_clk_match, + .ops = &socfpga_clk_ops, + .probe = socfpga_clk_probe, + .of_to_plat = socfpga_clk_of_to_plat, + .plat_auto = sizeof(struct socfpga_clk_plat), +}; diff --git a/drivers/clk/altera/clk-dm.h b/drivers/clk/altera/clk-dm.h new file mode 100644 index 0000000000..89d3a92a34 --- /dev/null +++ b/drivers/clk/altera/clk-dm.h @@ -0,0 +1,217 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 Intel Corporation <www.intel.com> + */ + +#ifndef _CLK_DM_ +#define _CLK_DM_ + +#ifndef __ASSEMBLY__ +#include <linux/bitops.h> +#endif + +#define CM_REG_READL(plat, reg) \ + readl((plat)->regs + (reg)) + +#define CM_REG_WRITEL(plat, data, reg) \ + writel(data, (plat)->regs + (reg)) + +#define CM_REG_CLRBITS(plat, reg, clear) \ + clrbits_le32((plat)->regs + (reg), (clear)) + +#define CM_REG_SETBITS(plat, reg, set) \ + setbits_le32((plat)->regs + (reg), (set)) + +struct cm_config { + /* main group */ + u32 main_pll_mpuclk; + u32 main_pll_nocclk; + u32 main_pll_nocdiv; + u32 main_pll_pllglob; + u32 main_pll_plldiv; + u32 main_pll_plloutdiv; + u32 spare_1[4]; + + /* peripheral group */ + u32 per_pll_emacctl; + u32 per_pll_gpiodiv; + u32 per_pll_pllglob; + u32 per_pll_plldiv; + u32 per_pll_plloutdiv; + u32 spare_2[4]; + + /* altera group */ + u32 alt_emacactr; + u32 alt_emacbctr; + u32 alt_emacptpctr; + u32 alt_gpiodbctr; + u32 alt_sdmmcctr; + u32 alt_s2fuser0ctr; + u32 alt_s2fuser1ctr; + u32 alt_psirefctr; + + /* incoming clock */ + u32 hps_osc_clk_hz; + u32 fpga_clk_hz; + u32 spare_3[3]; + + /* memory clock group */ + u32 mem_memdiv; + u32 mem_pllglob; + u32 mem_plldiv; + u32 mem_plloutdiv; + u32 spare_4[4]; +}; + +/* Clock Manager registers */ +#define CLKMGR_CTRL 0 +#define CLKMGR_STAT 4 +#define CLKMGR_TESTIOCTRL 8 +#define CLKMGR_INTRGEN 0x0c +#define CLKMGR_INTRMSK 0x10 +#define CLKMGR_INTRCLR 0x14 +#define CLKMGR_INTRSTS 0x18 +#define CLKMGR_INTRSTK 0x1c +#define CLKMGR_INTRRAW 0x20 + +/* Clock Manager Main PPL group registers */ +#define CLKMGR_MAINPLL_EN 0x24 +#define CLKMGR_MAINPLL_ENS 0x28 +#define CLKMGR_MAINPLL_ENR 0x2c +#define CLKMGR_MAINPLL_BYPASS 0x30 +#define CLKMGR_MAINPLL_BYPASSS 0x34 +#define CLKMGR_MAINPLL_BYPASSR 0x38 +#define CLKMGR_MAINPLL_MPUCLK 0x3c +#define CLKMGR_MAINPLL_NOCCLK 0x40 +#define CLKMGR_MAINPLL_NOCDIV 0x44 +#define CLKMGR_MAINPLL_PLLGLOB 0x48 +#define CLKMGR_MAINPLL_PLLCTRL 0x4c +#define CLKMGR_MAINPLL_PLLDIV 0x50 +#define CLKMGR_MAINPLL_PLLOUTDIV 0x54 +#define CLKMGR_MAINPLL_LOSTLOCK 0x58 + +/* Clock Manager Peripheral PPL group registers */ +#define CLKMGR_PERPLL_EN 0x7c +#define CLKMGR_PERPLL_ENS 0x80 +#define CLKMGR_PERPLL_ENR 0x84 +#define CLKMGR_PERPLL_BYPASS 0x88 +#define CLKMGR_PERPLL_BYPASSS 0x8c +#define CLKMGR_PERPLL_BYPASSR 0x90 +#define CLKMGR_PERPLL_EMACCTL 0x94 +#define CLKMGR_PERPLL_GPIODIV 0x98 +#define CLKMGR_PERPLL_PLLGLOB 0x9c +#define CLKMGR_PERPLL_PLLCTRL 0xa0 +#define CLKMGR_PERPLL_PLLDIV 0xa4 +#define CLKMGR_PERPLL_PLLOUTDIV 0xa8 +#define CLKMGR_PERPLL_LOSTLOCK 0xac + +/* Clock Manager Altera group registers */ +#define CLKMGR_ALTR_EMACACTR 0xd4 +#define CLKMGR_ALTR_EMACBCTR 0xd8 +#define CLKMGR_ALTR_EMACPTPCTR 0xdc +#define CLKMGR_ALTR_GPIODBCTR 0xe0 +#define CLKMGR_ALTR_SDMMCCTR 0xe4 +#define CLKMGR_ALTR_S2FUSER0CTR 0xe8 +#define CLKMGR_ALTR_S2FUSER1CTR 0xec +#define CLKMGR_ALTR_PSIREFCTR 0xf0 +#define CLKMGR_ALTR_EXTCNTRST 0xf4 + +#define CLKMGR_CTRL_BOOTMODE BIT(0) + +#define CLKMGR_STAT_BUSY BIT(0) +#define CLKMGR_STAT_MAINPLL_LOCKED BIT(8) +#define CLKMGR_STAT_MAIN_TRANS BIT(9) +#define CLKMGR_STAT_PERPLL_LOCKED BIT(16) +#define CLKMGR_STAT_PERF_TRANS BIT(17) +#define CLKMGR_STAT_BOOTMODE BIT(24) +#define CLKMGR_STAT_BOOTCLKSRC BIT(25) + +#define CLKMGR_STAT_ALLPLL_LOCKED_MASK \ + (CLKMGR_STAT_MAINPLL_LOCKED | CLKMGR_STAT_PERPLL_LOCKED) + +#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001 +#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002 +#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004 +#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008 + +#define CLKMGR_CLKSRC_MASK GENMASK(18, 16) +#define CLKMGR_CLKSRC_OFFSET 16 +#define CLKMGR_CLKSRC_MAIN 0 +#define CLKMGR_CLKSRC_PER 1 +#define CLKMGR_CLKSRC_OSC1 2 +#define CLKMGR_CLKSRC_INTOSC 3 +#define CLKMGR_CLKSRC_FPGA 4 +#define CLKMGR_CLKCNT_MSK GENMASK(10, 0) + +#define CLKMGR_BYPASS_MAINPLL_ALL 0x7 +#define CLKMGR_BYPASS_PERPLL_ALL 0x7f + +#define CLKMGR_NOCDIV_L4MAIN_OFFSET 0 +#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8 +#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16 +#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24 +#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26 +#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28 +#define CLKMGR_NOCDIV_DIVIDER_MASK 0x3 + +#define CLKMGR_PLLGLOB_VCO_PSRC_MASK GENMASK(17, 16) +#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16 +#define CLKMGR_PLLGLOB_LOSTLOCK_BYPASS_EN_MASK BIT(28) +#define CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK BIT(29) + +#define CLKMGR_VCO_PSRC_EOSC1 0 +#define CLKMGR_VCO_PSRC_INTOSC 1 +#define CLKMGR_VCO_PSRC_F2S 2 + +#define CLKMGR_PLLCTRL_BYPASS_MASK BIT(0) +#define CLKMGR_PLLCTRL_RST_N_MASK BIT(1) + +#define CLKMGR_PLLDIV_REFCLKDIV_MASK GENMASK(5, 0) +#define CLKMGR_PLLDIV_FDIV_MASK GENMASK(16, 8) +#define CLKMGR_PLLDIV_OUTDIV_QDIV_MASK GENMASK(26, 24) +#define CLKMGR_PLLDIV_RANGE_MASK GENMASK(30, 28) + +#define CLKMGR_PLLDIV_REFCLKDIV_OFFSET 0 +#define CLKMGR_PLLDIV_FDIV_OFFSET 8 +#define CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET 24 +#define CLKMGR_PLLDIV_RANGE_OFFSET 28 + +#define CLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0) +#define CLKMGR_PLLOUTDIV_C1CNT_MASK GENMASK(12, 8) +#define CLKMGR_PLLOUTDIV_C2CNT_MASK GENMASK(20, 16) +#define CLKMGR_PLLOUTDIV_C3CNT_MASK GENMASK(28, 24) + +#define CLKMGR_PLLOUTDIV_C0CNT_OFFSET 0 +#define CLKMGR_PLLOUTDIV_C1CNT_OFFSET 8 +#define CLKMGR_PLLOUTDIV_C2CNT_OFFSET 16 +#define CLKMGR_PLLOUTDIV_C3CNT_OFFSET 24 + +#define CLKMGR_PLLCX_EN_SET_MSK BIT(27) +#define CLKMGR_PLLCX_MUTE_SET_MSK BIT(28) + +#define CLKMGR_VCOCALIB_MSCNT_MASK GENMASK(23, 16) +#define CLKMGR_VCOCALIB_MSCNT_OFFSET 16 +#define CLKMGR_VCOCALIB_HSCNT_MASK GENMASK(9, 0) +#define CLKMGR_VCOCALIB_MSCNT_CONST 100 +#define CLKMGR_VCOCALIB_HSCNT_CONST 4 + +#define CLKMGR_PLLM_MDIV_MASK GENMASK(9, 0) + +#define CLKMGR_LOSTLOCK_SET_MASK BIT(0) + +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5) +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET 26 +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK BIT(26) +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET 27 +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK BIT(27) +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET 28 +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK BIT(28) + +#define CLKMGR_ALT_EMACCTR_SRC_OFFSET 16 +#define CLKMGR_ALT_EMACCTR_SRC_MASK GENMASK(18, 16) +#define CLKMGR_ALT_EMACCTR_CNT_OFFSET 0 +#define CLKMGR_ALT_EMACCTR_CNT_MASK GENMASK(10, 0) + +#define CLKMGR_ALT_EXTCNTRST_ALLCNTRST_MASK GENMASK(15, 0) + +#endif /* _CLK_DM_ */ diff --git a/include/dt-bindings/clock/dm-clock.h b/include/dt-bindings/clock/dm-clock.h new file mode 100644 index 0000000000..d624ac723c --- /dev/null +++ b/include/dt-bindings/clock/dm-clock.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020, Intel Corporation + */ + +#ifndef __DM_CLOCK_H +#define __DM_CLOCK_H + +/* fixed rate clocks */ +#define DM_OSC1 0 +#define DM_CB_INTOSC_HS_DIV2_CLK 1 +#define DM_CB_INTOSC_LS_CLK 2 +#define DM_L4_SYS_FREE_CLK 3 +#define DM_F2S_FREE_CLK 4 + +/* PLL clocks */ +#define DM_MAIN_PLL_CLK 5 +#define DM_MAIN_PLL_C0_CLK 6 +#define DM_MAIN_PLL_C1_CLK 7 +#define DM_MAIN_PLL_C2_CLK 8 +#define DM_MAIN_PLL_C3_CLK 9 +#define DM_PERIPH_PLL_CLK 10 +#define DM_PERIPH_PLL_C0_CLK 11 +#define DM_PERIPH_PLL_C1_CLK 12 +#define DM_PERIPH_PLL_C2_CLK 13 +#define DM_PERIPH_PLL_C3_CLK 14 +#define DM_MPU_FREE_CLK 15 +#define DM_MPU_CCU_CLK 16 +#define DM_BOOT_CLK 17 + +/* fixed factor clocks */ +#define DM_L3_MAIN_FREE_CLK 18 +#define DM_NOC_FREE_CLK 19 +#define DM_S2F_USR0_CLK 20 +#define DM_NOC_CLK 21 +#define DM_EMAC_A_FREE_CLK 22 +#define DM_EMAC_B_FREE_CLK 23 +#define DM_EMAC_PTP_FREE_CLK 24 +#define DM_GPIO_DB_FREE_CLK 25 +#define DM_SDMMC_FREE_CLK 26 +#define DM_S2F_USER0_FREE_CLK 27 +#define DM_S2F_USER1_FREE_CLK 28 +#define DM_PSI_REF_FREE_CLK 29 + +/* Gate clocks */ +#define DM_MPU_CLK 30 +#define DM_MPU_PERIPH_CLK 31 +#define DM_L4_MAIN_CLK 32 +#define DM_L4_MP_CLK 33 +#define DM_L4_SP_CLK 34 +#define DM_CS_AT_CLK 35 +#define DM_CS_TRACE_CLK 36 +#define DM_CS_PDBG_CLK 37 +#define DM_CS_TIMER_CLK 38 +#define DM_S2F_USER0_CLK 39 +#define DM_EMAC0_CLK 40 +#define DM_EMAC1_CLK 41 +#define DM_EMAC2_CLK 42 +#define DM_EMAC_PTP_CLK 43 +#define DM_GPIO_DB_CLK 44 +#define DM_NAND_CLK 45 +#define DM_PSI_REF_CLK 46 +#define DM_S2F_USER1_CLK 47 +#define DM_SDMMC_CLK 48 +#define DM_SPI_M_CLK 49 +#define DM_USB_CLK 50 +#define DM_NAND_X_CLK 51 +#define DM_NAND_ECC_CLK 52 +#define DM_NUM_CLKS 53 + +#endif /* __DM_CLOCK_H */ -- 2.26.2

2 9

[PATCH 0/2] efi_loader: provide media ID
by Heinrich Schuchardt 28 Sep '22

28 Sep '22

The medium a device like 'mmc 0' or 'usb 0' points to may change over time. Hence device type and number are not sufficient to identify the inserted medium. The same is true for the device path generated for such a device. This is why the EFI_BLOCK_IO_PROTOCOL provides a field MediaId. Whenever a removable medium is changed or a new block device with a previously used device path is created we should provide a different MediaID. This series adds a field media_id to the block device descriptor and fills it after probing. The value of the field is then copied to the EFI_BLOCK_IO_PROTOCOL. With future patches we can refine this in sub-systems like USB, MMC, SCSI to indicate media changes Heinrich Schuchardt (2): dm: blk: assign media ID to block devices efi_loader: fill media_id from block device descriptor drivers/block/blk-uclass.c | 16 +++++++++++++++- include/blk.h | 11 +++++++++++ lib/efi_loader/efi_disk.c | 6 +----- 3 files changed, 27 insertions(+), 6 deletions(-) -- 2.37.2

4 16

Re: [RESEND 0/3] rockchip: Fix RAM training on RK3399 based platforms (Rock Pi 4)
by Lee Jones 28 Sep '22

28 Sep '22

On Thu, 11 Aug 2022, Lee Jones wrote: > This set fixes several issues found on the Rock Pi 4. > > For full context, please see this initial bug report: > > "There appear to be a number of issues with the Rockchip rk3399 DDR RAM > initialisation sequence in Mainline. Specifically, I'm seeing > consistent failures on the Rock Pi 4+ during early boot. A typical > failure looks something like this: > > U-Boot TPL 2022.07-rc3-00005-g1b04a961c6 (May 25 2022 - 11:09:19) > Channel 0: LPDDR4, 50MHz > BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB > Channel 1: col error > Cap error! > 256B stride > lpddr4_set_rate: change freq to 400000000 mhz 0, 1 > lpddr4_set_rate: change freq to 800000000 mhz 1, 0 > Trying to boot from BOOTROM > Returning to boot ROM... > > Even when the system boots to a terminal, which happens very > infrequently, the LPDDR4 RAM chip at Channel 1 can have conflicting > discovery information printed during TPL. The following 3 lines were > printed during successive reboots using the same SD card with no > changes: > > # Boot 1: > BW=32 Col=9 Bk=4 CS0 Row=16/15 CS=1 Die BW=16 Size=384MB > > # Boot 2: > BW=32 Col=10 Bk=4 CS0 Row=16/15 CS=1 Die BW=16 Size=768MB > > # Boot 3: > BW=32 Col=10 Bk=4 CS0 Row=15 CS=1 Die BW=16 Size=512MB > > The story changes when I build the idbloader.img image with Rockchip's > TBL (?) binary blob [0]. With that built in, presumably in place of > the upstream TBL, both RAM chips are successfully enumerated and boot > succeeds with 100% success rate: > > tools/mkimage -n rk3399 -T rksd -d \ > rk3399_ddr_933MHz_v1.25.bin:spl/u-boot-spl.bin idbloader.img > > Another thing that is very different between the 2 is the initial > frequency the LPDDR4 chips are clocked at. Using the upstream TBL > version, the default is 50Mhz, which seems very low. If using the > Rockchip supplied binary blob file, this is increased to a respectable > 416MHz: > > # Mainline > Channel 0: LPDDR4, 50MHz > > # Rockchip TBL blob > Channel 0: LPDDR4,416MHz > > One thing I did try was to load in the 400Mhz configuration settings > from drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc as the default > initial values, instead of the 50MHz default taken from > arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi, but this failed in a number > of ways: > > Setting clock: Freq: 400MHz (400000000) > Calling SDRAM init: 2 Channels > Starting SDRAM initialization... > mr5:0 mr12:0 mr14:0 > Training failed for rank 2, ch 0 (ret: -22) > mr5:0 mr12:0 mr14:0 > Training failed for rank 1, ch 0 (ret: -22) > mr5:0 mr12:0 mr14:0 > Training failed for rank 2, ch 1 (ret: -22) > mr5:0 mr12:0 mr14:0 > Training failed for rank 1, ch 1 (ret: -22) > Rank for Channel 1 is 0x0 > Rank for Channel 0 is 0x0 > Rank for Channel 1 is 0x0 > sdram_init: LPDDR4 - 400MHz failed! > rk3399_dmc_init DRAM init failed -22 > > So my question is; does Rockchip, or anyone else for that matter, have > any plans on updating Mainline U-Boot with the upgraded/working LPDDR4 > initialisation sequence?" > > Lee Jones (3): > ram: rk3399: Fix .set_rate_index() error handling > ram: rk3399: Fix faulty frequency change reports > ram: rk3399: Conduct memory training at 400MHz > > drivers/ram/rockchip/sdram_rk3399.c | 38 +++++++++++++++++------------ > 1 file changed, 23 insertions(+), 15 deletions(-) Looks as though we have all the Reviews we need. Would someone be kind enough to merge these patches please? They solve some pretty serious user reported issues. Thank you. -- Lee Jones [李琼斯]

3 5

[PATCH v2 2/3] arm: dts: rockchip: update cpu and gpu nodes
by Johan Jonker 28 Sep '22

28 Sep '22

In order to better compare the Linux rk3288.dtsi version with the u-boot version update the cpu and gpu nodes. Changed: use operating-points-v2 update thermal for all cpus add labels to all cpus change gpu compatible change gpu interrupt names Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> Reviewed-by: Kever Yang <kever.yang(a)rock-chips.com> --- arch/arm/dts/rk3288.dtsi | 148 +++++++++++++++++++++++++++++---------- 1 file changed, 111 insertions(+), 37 deletions(-) diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 754c77cc..f473691c 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -45,44 +45,99 @@ device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x500>; - operating-points = < - /* KHz uV */ - 1800000 1400000 - 1704000 1350000 - 1608000 1300000 - 1512000 1250000 - 1416000 1200000 - 1200000 1100000 - 1008000 1050000 - 816000 1000000 - 696000 950000 - 600000 900000 - 408000 900000 - 216000 900000 - 126000 900000 - >; + resets = <&cru SRST_CORE0>; + operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ clock-latency = <40000>; clocks = <&cru ARMCLK>; - resets = <&cru SRST_CORE0>; + dynamic-power-coefficient = <370>; }; - cpu@501 { + cpu1: cpu@501 { device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x501>; resets = <&cru SRST_CORE1>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + dynamic-power-coefficient = <370>; }; - cpu@502 { + cpu2: cpu@502 { device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x502>; resets = <&cru SRST_CORE2>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + dynamic-power-coefficient = <370>; }; - cpu@503 { + cpu3: cpu@503 { device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x503>; resets = <&cru SRST_CORE3>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + dynamic-power-coefficient = <370>; + }; + }; + + cpu_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-126000000 { + opp-hz = /bits/ 64 <126000000>; + opp-microvolt = <900000>; + }; + opp-216000000 { + opp-hz = /bits/ 64 <216000000>; + opp-microvolt = <900000>; + }; + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <900000>; + }; + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <900000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + }; + opp-696000000 { + opp-hz = /bits/ 64 <696000000>; + opp-microvolt = <950000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1050000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1200000>; + }; + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1300000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1350000>; }; }; @@ -374,12 +429,18 @@ map0 { trip = <&cpu_alert0>; cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>; + <&cpu0 THERMAL_NO_LIMIT 6>, + <&cpu1 THERMAL_NO_LIMIT 6>, + <&cpu2 THERMAL_NO_LIMIT 6>, + <&cpu3 THERMAL_NO_LIMIT 6>; }; map1 { trip = <&cpu_alert1>; cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; }; @@ -900,31 +961,44 @@ }; gpu: gpu@ffa30000 { - compatible = "arm,malit764", - "arm,malit76x", - "arm,malit7xx", - "arm,mali-midgard"; + compatible = "rockchip,rk3288-mali", "arm,mali-t760"; reg = <0xffa30000 0x10000>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "JOB", "MMU", "GPU"; + interrupt-names = "job", "mmu", "gpu"; clocks = <&cru ACLK_GPU>; - clock-names = "aclk_gpu"; - operating-points = < - /* KHz uV */ - 100000 950000 - 200000 950000 - 300000 1000000 - 400000 1100000 - /* 500000 1200000 - See crosbug.com/p/33857 */ - 600000 1250000 - >; + operating-points-v2 = <&gpu_opp_table>; #cooling-cells = <2>; /* min followed by max */ power-domains = <&power RK3288_PD_GPU>; status = "disabled"; }; + gpu_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <950000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <950000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1000000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1100000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1250000>; + }; + }; + dmac_bus_s: dma-controller@ffb20000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xffb20000 0x4000>; -- 2.20.1

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