September 2022 - U-Boot

[PATCH v2 0/1] dm: fpga: Introduce new uclass
by Alexander Dahl 04 Oct '22

04 Oct '22

Hei hei, tried to address all the feedback I got from Simon, thanks for that. Build tested on Debian GNU/Linux 11 (bullseye) on arch amd64, tried on i386 first, but got some nasty errors there (see IRC backlog). Tried in sandbox console, and everythings looks fine to me, as far as I can judge. `dm tree` and `dm uclass` and `dm drivers` list the right things, and `ut dm fpga` returns with success. I refused to add Simon's Reviewed-by, because I did some changes compared to RFC (see notes on patch). One technical question: should I add SANDBOX_FPGA to sandbox_defconfig? And Michal, is it okay to add you as maintainer for the unit test as I did in v2 of the patch now? Greets Alex Alexander Dahl (1): dm: fpga: Introduce new uclass MAINTAINERS | 1 + arch/sandbox/dts/test.dts | 4 ++++ drivers/fpga/Kconfig | 19 +++++++++++++++++++ drivers/fpga/Makefile | 3 +++ drivers/fpga/fpga-uclass.c | 11 +++++++++++ drivers/fpga/sandbox.c | 17 +++++++++++++++++ include/dm/uclass-id.h | 1 + test/dm/Makefile | 1 + test/dm/fpga.c | 20 ++++++++++++++++++++ 9 files changed, 77 insertions(+) create mode 100644 drivers/fpga/fpga-uclass.c create mode 100644 drivers/fpga/sandbox.c create mode 100644 test/dm/fpga.c base-commit: 97c0a9c5708dc60d82cad721a8b882f0ce37e83d -- 2.30.2

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Testing v2022.10-rc5 on mt7621
by Sven F. 03 Oct '22

03 Oct '22

Dear readers, I have a mt7621 spi nor with 256MB DDR board, and I am trying to get an open source software suite on it. IE : u-boot 2022.10 and open wrt v22.03.0 I follow instruction and build u-boot with : export CROSS_COMPILE=mipsel-linux-gnu- make mrproper && make O=build mt7621_rfb_defconfig && \ make O=build -j$(nproc) 2>&1 | tee ../uboot.build.log.mt7621_rfb_defconfig The output file looks ok but the last part of LZMA is not recognized fully. $ binwalk ./build/u-boot-mt7621.bin DECIMAL HEXADECIMAL DESCRIPTION -------------------------------------------------------------------------------- 2156 0x86C uImage header, header size: 64 bytes, header CRC: 0x3D774D5C, created: 2022-09-21 13:56:55, image size: 3 8828 bytes, Data Address: 0x80100000, Entry Point: 0x80100000, data CRC: 0x38979001, OS: Firmware, CPU: MIPS, \ image type: Standalone Program, compression type: none, image name: "MT7621 U-Boot SPL" 41048 0xA058 uImage header, header size: 64 bytes, header CRC: 0x18B75518, created: 2022-09-21 13:56:49, image size: 1 45331 bytes, Data Address: 0x80200000, Entry Point: 0x80200000, data CRC: 0xB39FB0D8, OS: Firmware, CPU: MIPS, \ image type: Standalone Program, compression type: lzma, image name: "U-Boot 2022.10-rc4 for mt7621 bo" 41112 0xA098 LZMA compressed data, properties: 0x5D, dictionary size: 67108864 bytes, uncompressed size: -1 bytes Remark on the build process, only one warning: /home/toor/2022/official/bootloader/u-boot/build/../scripts/dtc/pylibfdt/setup.py:21 DeprecationWarning: \ The distutils package is deprecated and slated for removal in Python 3.12. Use setuptools or check PEP 632 for potential alternatives I think it would sensible to put some checksum of the online binaries file for the `DDR initialization binary blob` + 1dda68aa089f0ff262e01539b990dea478952e9fb68bcc0a8cd6f76f0135c62e ./mt7621_stage_sram.bin + 8ee419275144fc298e9444d413d98e965a55d283152a74ea6a1f8de79eb516b6 ./mt7621_stage_sram_noprint.bin and the CROSS_COMPILE define may be signal `mipsel-linux-gnu-` in https://github.com/u-boot/u-boot/blob/master/doc/board/mediatek/mt7621.rst Before burning the ROM , I would like to validate the build somehow since it is very hard to recover from a bad bootloader ! `Burn the u-boot-mt7621.bin to the SPI-NOR` is a bit drastic. Is it possible to boot one of those from memory using the `go` command to check if the build looks ok 1990a6e661e450d944ff69c103cb0ca7 ./build/u-boot-dtb.img 1990a6e661e450d944ff69c103cb0ca7 ./build/u-boot.img d025641feb8aeb423c5bb829a989ddd4 ./build/u-boot-lzma.img 27b67fb29c11ea542405e25829df00ee ./build/u-boot-spl-ddr.img 0c7d7fa983b3e7b7c9cd202e89f6cb07 ./build/mt7621_stage_sram.bin d1ee76fe3750386e4ec5de3cb0599c8f ./build/u-boot.bin d1ee76fe3750386e4ec5de3cb0599c8f ./build/u-boot-dtb.bin be651a79adc284ee3aac5edfc873eacc ./build/u-boot-mt7621.bin 6fa3b83a89174c828b4af8c53beeece6 ./build/u-boot-nodtb.bin d7d4fd33c9c2bdeeb074d3367b09cf10 ./build/u-boot-spl-ddr.bin 980971dba7452050a975398324d771e1 ./build/u-boot Is it possible to do something similar ? please advice => bootp 0x80010000 u-boot-nodtb.bin => go 0x80010000 Thank you for reading that far. PS: some board data. => bdinfo boot_params = 0x8FEB1160 memstart = 0x80000000 memsize = 0x10000000 flashstart = 0x00000000 flashsize = 0x00000000 flashoffset = 0x00000000 ethaddr = (not set) IP addr = 192.168.1. baudrate = 115200 bps relocaddr = 0x8FFB0000 reloc off = 0x0FDB0000 >> Initializing DDR3 >> Applying AC timing parameters (try 1) Expected DRAM size: 128MB >> Setting DDR/CPU PLL ... Using 3PLL mode with External loopback DDR/CPU clock will be set to 1200MHz/880MHz >> Starting DDR PLL calibration ... DDR PLL2/3/4 feedback delay: 23/13/18 DDR 3PLL mode calibration passed >> Starting DQS Gating Window Delay calibration 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 ---------------------------------------------------------------- 0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000E:| 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 000F:| 0 0 0 0 0 1 1 0 1 1 1 0 1 1 0 0 0010:| 1 1 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0011:| 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Found coarse/fine delay value: 16/32 >> Starting DLE calibration 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ---------------------------------------------------------------- 0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Failed to find optimal DQS factor >> Got DRAM size 0MB Retrying ... >> Applying AC timing parameters (try 2) Expected DRAM size: 256MB >> Setting DDR/CPU PLL ... Using 3PLL mode with External loopback DDR/CPU clock will be set to 1200MHz/880MHz >> Starting DDR PLL calibration ... DDR PLL2/3/4 feedback delay: 23/13/18 DDR 3PLL mode calibration passed >> Starting DQS Gating Window Delay calibration 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 ---------------------------------------------------------------- 0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000E:| 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 000F:| 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0010:| 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0011:| 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Found coarse/fine delay value: 15/80 >> Starting DLE calibration 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ---------------------------------------------------------------- 0000:| 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 Optimal DQS factor: 9 >> Starting RX DQ per-bit delay calibration Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ---------------------------------------------------------------- Delay 11 11 11 12 9 11 9 9 7 7 9 8 9 10 8 10 >> Starting DQS delay calibration Bit ( Range ) Center -------------------- 0 ( 1~ 62) 31 1 ( 1~ 61) 31 2 ( 1~ 60) 30 3 ( 1~ 62) 31 4 ( 0~ 62) 31 5 ( 1~ 63) 32 6 ( 1~ 61) 31 7 ( 1~ 63) 32 DQS0 input delay: 32 Bit ( Range ) Center -------------------- 8 ( 1~ 59) 30 9 ( 1~ 58) 29 10 ( 1~ 59) 30 11 ( 1~ 58) 29 12 ( 2~ 60) 31 13 ( 1~ 59) 30 14 ( 1~ 59) 30 15 ( 1~ 60) 30 DQS1 input delay: 31 >> Final DQ delay value Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ---------------------------------------------------------------- Delay 12 12 13 13 10 11 10 9 8 9 10 10 9 11 9 11 >> Starting TX DQ/QDS per-byte calibration Byte 0: (DQS,DQ)=(8,8) Byte 1: (DQS,DQ)=(8,8) DDR calibration passed >> Got DRAM size 256MB DRAM initialization succeeded U-Boot SPL 2018.09-svn35 (Mar 11 2021 - 19:17:36 +0800) Trying to boot from NOR U-Boot 2018.09-svn35 (Mar 11 2021 - 19:17:36 +0800) CPU: MediaTek MT7621AT ver 1, eco 3 Clocks: CPU: 880MHz, DDR: 1200MHz, Bus: 220MHz, XTAL: 40MHz Model: MediaTek MT7621 reference board DRAM: 256 MiB Loading Environment from SPI Flash... SF: Detected w25q128bv with page size 256 Bytes, erase size 64 KiB, total 16 MiB *** Warning - bad CRC, using default environment In: uartlite0@1e000c00 Out: uartlite0@1e000c00 Err: uartlite0@1e000c00 Net: Warning: eth@1e100000 (eth0) using random MAC address - 5e:69:c8:f8:cf:5b eth0: eth@1e100000 Hit any key to stop autoboot: 0 *** U-Boot Boot Menu *** 1. Startup system (Default) 2. Upgrade firmware 3. Upgrade bootloader 4. Upgrade bootloader (advanced mode) 5. Load image 0. U-Boot console

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[PATCH v10 00/15] FWU: Add FWU Multi Bank Update feature support
by Sughosh Ganu 03 Oct '22

03 Oct '22

The patchset adds support for the FWU Multi Bank Update[1] feature. Certain aspects of the Dependable Boot[2] specification have also been implemented. The FWU multi bank update feature is used for supporting multiple sets(also called banks) of firmware image(s), allowing the platform to boot from a different bank, in case it fails to boot from the active bank. This functionality is supported by keeping the relevant information in a structure called metadata, which provides information on the images. Among other parameters, the metadata structure contains information on the currect active bank that is being used to boot image(s). Functionality is being added to work with the UEFI capsule driver in u-boot. The metadata is read to gather information on the update bank, which is the bank to which the firmware images would be flashed to. On a successful completion of the update of all components, the active bank field in the metadata is updated, to reflect the bank from which the platform will boot on the subsequent boots. Currently, the feature is being enabled on the STM32MP157C-DK2 and Synquacer boards. The DK2 board boots a FIP image from a uSD card partitioned with the GPT partioning scheme, while the Synquacer board boots a FIP image from a MTD partitioned SPI NOR flash device. This feature also requires changes in a previous stage of bootloader, which parses the metadata and selects the bank to boot the image(s) from. Support has being added in tf-a(BL2 stage) for the STM32MP157C-DK2 board to boot the active bank images. These changes have been merged to the upstream tf-a repository. The patch for adding a python test for the feature has been developed, and was sent in the version 5 of the patches[3]. However, the test script depends on adding support for the feature on MTD SPI NOR devices, and that is being done as part of the Synquacer patches. Hence these set of patches do not have the test script for the feature. That will be added through the patches for adding support for the feauture on Synquacer platform. [1] - https://developer.arm.com/documentation/den0118/a [2] - https://git.codelinaro.org/linaro/dependable-boot/mbfw/uploads/6f7ddfe3be24… [3] - https://lists.denx.de/pipermail/u-boot/2022-June/485992.html Changes since V9: * Add a helper function fwu_get_dev_mdata() to get the FWU metadata device and read the metadata. * Rename fwu_get_image_alt_num() as fwu_get_image_image_index() based on suggestion from Takahiro. * s/formated/formatted in the commit message * Add a '\n' character in the log message * Remove the check board_is_stm32mp15x_dk2() as suggested by Etienne * Remove unneeded braces as suggested by Ilias * Change the fwu_plat_get_bootidx() function to take an uint * as the function parameter instead of the void * as suggested by Etienne. * Add a comment to indicate where the event notification will be called, as suggested by Simon. * Remove the unused variable active_idx, as suggested by Etienne * Move the global variables into local variables as suggested by Ilias. * Change fwu_get_image_alt_num() name to fwu_get_image_image_index() as suggested by Takahiro. * Allow capsule updates to be called from efi_init_obj_list() with the FWU feature enabled, as suggested by Takahiro. * Enable EFI_CAPSULE_ON_DISK_EARLY as an imply with the FWU feature enabled. * Define the FWU feature related functions as __maybe_unused to allow for compilation with the FWU feature disabled. * Add a document for the command * Change the fwu_plat_get_bootidx() function to take an uint * as the function parameter instead of the void * as suggested by Etienne. Sughosh Ganu (15): dt/bindings: Add bindings for GPT based FWU Metadata storage device FWU: Add FWU metadata structure and driver for accessing metadata FWU: Add FWU metadata access driver for GPT partitioned block devices stm32mp1: dk2: Add a node for the FWU metadata device stm32mp1: dk2: Add image information for capsule updates FWU: Add helper functions for accessing FWU metadata FWU: STM32MP1: Add support to read boot index from backup register event: Add an event for main_loop FWU: Add boot time checks as highlighted by the FWU specification FWU: Add support for the FWU Multi Bank Update feature FWU: cmd: Add a command to read FWU metadata test: dm: Add test cases for FWU Metadata uclass mkeficapsule: Add support for generating empty capsules mkeficapsule: Add support for setting OEM flags in capsule header FWU: doc: Add documentation for the FWU feature arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi | 7 + arch/arm/mach-stm32mp/include/mach/stm32.h | 5 + arch/sandbox/Kconfig | 6 + arch/sandbox/dts/test.dts | 7 +- board/sandbox/sandbox.c | 8 + board/st/stm32mp1/stm32mp1.c | 44 ++ cmd/Kconfig | 6 + cmd/Makefile | 1 + cmd/fwu_mdata.c | 79 +++ common/board_r.c | 3 + common/event.c | 3 + configs/sandbox64_defconfig | 5 +- doc/develop/uefi/fwu_updates.rst | 165 +++++ doc/develop/uefi/index.rst | 1 + doc/develop/uefi/uefi.rst | 2 + .../firmware/fwu-mdata-gpt.yaml | 32 + doc/mkeficapsule.1 | 33 +- doc/usage/cmd/fwu_mdata.rst | 43 ++ doc/usage/index.rst | 1 + drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/fwu-mdata/Kconfig | 16 + drivers/fwu-mdata/Makefile | 8 + drivers/fwu-mdata/fwu-mdata-uclass.c | 107 ++++ drivers/fwu-mdata/gpt_blk.c | 378 ++++++++++++ include/configs/stm32mp15_common.h | 4 + include/dm/uclass-id.h | 1 + include/event.h | 3 + include/fwu.h | 302 +++++++++ include/fwu_mdata.h | 67 ++ lib/Kconfig | 6 + lib/Makefile | 1 + lib/efi_loader/efi_capsule.c | 243 +++++++- lib/efi_loader/efi_setup.c | 1 + lib/fwu_updates/Kconfig | 33 + lib/fwu_updates/Makefile | 7 + lib/fwu_updates/fwu.c | 577 ++++++++++++++++++ lib/fwu_updates/fwu_gpt.c | 114 ++++ test/dm/Makefile | 1 + test/dm/fwu_mdata.c | 149 +++++ test/dm/fwu_mdata_disk_image.h | 112 ++++ .../test_capsule_firmware_fit.py | 1 - .../test_capsule_firmware_signed_fit.py | 1 - tools/Makefile | 2 +- tools/eficapsule.h | 8 + tools/mkeficapsule.c | 109 +++- 46 files changed, 2679 insertions(+), 26 deletions(-) create mode 100644 cmd/fwu_mdata.c create mode 100644 doc/develop/uefi/fwu_updates.rst create mode 100644 doc/device-tree-bindings/firmware/fwu-mdata-gpt.yaml create mode 100644 doc/usage/cmd/fwu_mdata.rst create mode 100644 drivers/fwu-mdata/Kconfig create mode 100644 drivers/fwu-mdata/Makefile create mode 100644 drivers/fwu-mdata/fwu-mdata-uclass.c create mode 100644 drivers/fwu-mdata/gpt_blk.c create mode 100644 include/fwu.h create mode 100644 include/fwu_mdata.h create mode 100644 lib/fwu_updates/Kconfig create mode 100644 lib/fwu_updates/Makefile create mode 100644 lib/fwu_updates/fwu.c create mode 100644 lib/fwu_updates/fwu_gpt.c create mode 100644 test/dm/fwu_mdata.c create mode 100644 test/dm/fwu_mdata_disk_image.h -- 2.34.1

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[u-boot][PATCH 0/3] Introduce TI GPMC memory controller driver
by Roger Quadros 03 Oct '22

03 Oct '22

Hi, The GPMC is a unified memory controller dedicated for interfacing with external memory devices like - Asynchronous SRAM-like memories and ASICs - Asynchronous, synchronous, and page mode burst NOR flash - NAND flash - Pseudo-SRAM devices This driver will take care of setting up the GPMC based on the settings specified in the Device tree and then probe its children. cheers, -roger Roger Quadros (3): scripts: Makefile.spl: Enable memory drivers to be built for SPL dt/bindings: memory: Add bindings for TI GPMC driver memory: Add TI GPMC driver .../memory/ti,gpmc-child.yaml | 252 ++++ doc/device-tree-bindings/memory/ti,gpmc.yaml | 190 +++ drivers/memory/Kconfig | 16 + drivers/memory/Makefile | 1 + drivers/memory/ti-gpmc.c | 1237 +++++++++++++++++ drivers/memory/ti-gpmc.h | 298 ++++ include/linux/mtd/omap_gpmc.h | 3 + scripts/Makefile.spl | 1 + 8 files changed, 1998 insertions(+) create mode 100644 doc/device-tree-bindings/memory/ti,gpmc-child.yaml create mode 100644 doc/device-tree-bindings/memory/ti,gpmc.yaml create mode 100644 drivers/memory/ti-gpmc.c create mode 100644 drivers/memory/ti-gpmc.h -- 2.17.1

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how u-boot handles the environment (rpi4, fat environment)
by marty leisner 02 Oct '22

02 Oct '22

I'm running ubuntu 20.04 server (which uses u-boot v2021.01 with minor changes/enhancements) fw_printenv doesn't seem to work -- it always comes up with a crc error (I haven't tried fw_setenv yet). Is there a spec of how the environment works? I haven't seen one. Without this patch, I get: Warning: Bad CRC, using default environment The first environment variable has a "0x1" in front of it. When I apply this patch, things seem to work: diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 66cb9d2a..c85b471a 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -1457,8 +1457,8 @@ int fw_env_open(struct env_opts *opts) goto open_cleanup; } - crc0 = crc32(0, (uint8_t *)environment.data, ENV_SIZE); - + crc0 = crc32(0, (uint8_t *) (environment.data + 1) , ENV_SIZE - 1); But I'm not at the phase of doing fw_setenv (I would have used a newer u-boot, but I'm getting resets on bootup (it works on a vanilla 20.04 system). marty marty

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[PATCH] riscv: Fix build against binutils 2.38
by Alexandre Ghiti 02 Oct '22

02 Oct '22

The following description is copied from the equivalent patch for the Linux Kernel proposed by Aurelien Jarno: >From version 2.38, binutils default to ISA spec version 20191213. This means that the csr read/write (csrr*/csrw*) instructions and fence.i instruction has separated from the `I` extension, become two standalone extensions: Zicsr and Zifencei. As the kernel uses those instruction, this causes the following build failure: arch/riscv/cpu/mtrap.S: Assembler messages: arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause' arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc' arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval' arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0' Signed-off-by: Alexandre Ghiti <alexandre.ghiti(a)canonical.com> --- arch/riscv/Makefile | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 0b80eb8d86..53d1194ffb 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) CMODEL = medany endif -ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \ +RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C) + +# Newer binutils versions default to ISA spec version 20191213 which moves some +# instructions from the I extension to the Zicsr and Zifencei extensions. +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei) +ifeq ($(toolchain-need-zicsr-zifencei),y) + RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei +endif + +ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \ -mcmodel=$(CMODEL) PLATFORM_CPPFLAGS += $(ARCH_FLAGS) -- 2.32.0

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[PATCH] pico-imx7d: add baseboard SD card boot detect
by egyszeregy＠freemail.hu 02 Oct '22

02 Oct '22

Migrate SD card boot detection from Technexion u-boot for pico-imx7d SoM. >From ecd4f6ecbec290c63504f7ec3a9b478425235d14 Mon Sep 17 00:00:00 2001 From: "Benjamin Szőke" <egyszeregy(a)freemail.hu> Date: Sun, 21 Aug 2022 21:08:55 +0200 Subject: [PATCH] pico-imx7d: add baseboard SD card boot detect Add SD card boot detection from Technexion u-boot for pico-imx7d SoM. --- arch/arm/dts/imx7d-pico-hobbit.dts | 7 +- arch/arm/dts/imx7d-pico-pi.dts | 7 +- board/technexion/pico-imx7d/Makefile | 2 +- board/technexion/pico-imx7d/pico-imx7d.c | 132 +++++++++++++++++- .../pico-imx7d/{spl.c => pico-imx7d_spl.c} | 125 +++++++++++++++-- common/splash.c | 2 +- configs/pico-dwarf-imx7d_defconfig | 5 + configs/pico-hobbit-imx7d_defconfig | 5 + configs/pico-imx7d_bl33_defconfig | 5 + configs/pico-imx7d_defconfig | 5 + configs/pico-nymph-imx7d_defconfig | 5 + configs/pico-pi-imx7d_defconfig | 5 + include/configs/pico-imx7d.h | 23 +-- 13 files changed, 299 insertions(+), 29 deletions(-) rename board/technexion/pico-imx7d/{spl.c => pico-imx7d_spl.c} (50%) diff --git a/arch/arm/dts/imx7d-pico-hobbit.dts b/arch/arm/dts/imx7d-pico-hobbit.dts index d917dc4f2f..78b10e12f6 100644 --- a/arch/arm/dts/imx7d-pico-hobbit.dts +++ b/arch/arm/dts/imx7d-pico-hobbit.dts @@ -13,6 +13,11 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; + aliases { + mmc0 = &usdhc1; + mmc2 = &usdhc3; + }; + led { label = "gpio-led"; gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; @@ -102,4 +107,4 @@ MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 >; }; -}; +}; \ No newline at end of file diff --git a/arch/arm/dts/imx7d-pico-pi.dts b/arch/arm/dts/imx7d-pico-pi.dts index f263e391e2..7405fcd2a0 100644 --- a/arch/arm/dts/imx7d-pico-pi.dts +++ b/arch/arm/dts/imx7d-pico-pi.dts @@ -13,6 +13,11 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; + aliases { + mmc0 = &usdhc1; + mmc2 = &usdhc3; + }; + led { label = "gpio-led"; gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; @@ -90,4 +95,4 @@ >; }; -}; +}; \ No newline at end of file diff --git a/board/technexion/pico-imx7d/Makefile b/board/technexion/pico-imx7d/Makefile index 4ae3d606b5..b45b127884 100644 --- a/board/technexion/pico-imx7d/Makefile +++ b/board/technexion/pico-imx7d/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ # (C) Copyright 2017 NXP Semiconductors -obj-y := pico-imx7d.o spl.o +obj-y := pico-imx7d.o pico-imx7d_spl.o diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index 1c0cc238df..a693e7b917 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -4,13 +4,11 @@ */ #include <init.h> -#include <net.h> #include <asm/arch/clock.h> #include <asm/arch/crm_regs.h> #include <asm/arch/imx-regs.h> #include <asm/arch/mx7-pins.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/gpio.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/mxc_i2c.h> @@ -21,6 +19,9 @@ #include <power/pmic.h> #include <power/pfuze3000_pmic.h> #include "../../freescale/common/pfuze.h" +#include <mmc.h> +#include <splash.h> +#include <asm/mach-imx/boot_mode.h> DECLARE_GLOBAL_DATA_PTR; @@ -159,6 +160,100 @@ int board_phy_config(struct phy_device *phydev) } #endif +#ifdef CONFIG_SPLASH_SCREEN +static struct splash_location imx_splash_locations[] = { + { + .name = "sf", + .storage = SPLASH_STORAGE_SF, + .flags = SPLASH_STORAGE_RAW, + .offset = 0x100000, + }, + { + .name = "mmc_fs", + .storage = SPLASH_STORAGE_MMC, + .flags = SPLASH_STORAGE_FS, + .devpart = "0:1", + }, + { + .name = "usb_fs", + .storage = SPLASH_STORAGE_USB, + .flags = SPLASH_STORAGE_FS, + .devpart = "0:1", + }, + { + .name = "sata_fs", + .storage = SPLASH_STORAGE_SATA, + .flags = SPLASH_STORAGE_FS, + .devpart = "0:1", + }, +}; + +/*This function is defined in common/splash.c. + Declare here to remove warning. */ +int splash_video_logo_load(void); + +int splash_screen_prepare(void) +{ + imx_splash_locations[1].devpart[0] = mmc_get_env_dev() + '0'; + int ret; + ret = splash_source_load(imx_splash_locations, ARRAY_SIZE(imx_splash_locations)); + if (!ret) + return 0; + else { + printf("\nNo splash.bmp in boot partition!!\n"); + printf("Using default logo!!\n\n"); + return splash_video_logo_load(); + } +} +#endif /* CONFIG_SPLASH_SCREEN */ + +#if CONFIG_IS_ENABLED(FSL_ESDHC_IMX) +int check_mmc_autodetect(void) +{ + char *autodetect_str = env_get("mmcautodetect"); + + if ((autodetect_str != NULL) && + (strcmp(autodetect_str, "yes") == 0)) { + return 1; + } + + return 0; +} + +void board_late_mmc_init(void) +{ + int dev_no = 0; + char cmd[32]; + char mmcblk[32]; + + if (!check_mmc_autodetect()) + return; + + switch (get_boot_device()) { + case SD3_BOOT: + case MMC3_BOOT: + env_set("bootdev", "MMC3"); + dev_no = 2; + break; + case SD1_BOOT: + env_set("bootdev", "SD1"); + dev_no = 0; + break; + default: + printf("Wrong boot device!"); + } + + env_set_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", dev_no); + env_set("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} +#endif + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); @@ -210,6 +305,10 @@ int board_late_init(void) set_wdog_reset(wdog); +#if defined(CONFIG_ENV_IS_IN_MMC) || defined(CONFIG_ENV_IS_NOWHERE) + board_late_mmc_init(); +#endif /* CONFIG_ENV_IS_IN_MMC or CONFIG_ENV_IS_NOWHERE */ + /* * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), * since we use PMIC_PWRON to reset the board. @@ -219,6 +318,29 @@ int board_late_init(void) return 0; } +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + const int *cell; + int offs; + uint32_t cma_size; + unsigned int dram_size; + + dram_size = imx_ddr_size() / 1024 / 1024; + offs = fdt_path_offset(blob, "/reserved-memory/linux,cma"); + cell = fdt_getprop(blob, offs, "size", NULL); + cma_size = fdt32_to_cpu(cell[0]); + if (dram_size == 512) { + /* CMA is aligned by 32MB on i.mx8mq, + so CMA size can only be multiple of 32MB */ + cma_size = env_get_ulong("cma_size", 10, (6 * 32) * 1024 * 1024); + fdt_setprop_u32(blob, offs, "size", (uint64_t)cma_size); + } + + return 0; +} +#endif + int checkboard(void) { puts("Board: i.MX7D PICOSOM\n"); @@ -244,3 +366,9 @@ int board_ehci_hcd_init(int port) } return 0; } + +/* This should be defined for each board */ +__weak int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no; +} diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/pico-imx7d_spl.c similarity index 50% rename from board/technexion/pico-imx7d/spl.c rename to board/technexion/pico-imx7d/pico-imx7d_spl.c index df5f058577..537a6bd583 100644 --- a/board/technexion/pico-imx7d/spl.c +++ b/board/technexion/pico-imx7d/pico-imx7d_spl.c @@ -5,9 +5,9 @@ * Author: Richard Hu <richard.hu(a)technexion.com> */ -#include <common.h> -#include <cpu_func.h> #include <init.h> +#include <command.h> +#include <cpu_func.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/arch/crm_regs.h> @@ -18,6 +18,7 @@ #include <asm/gpio.h> #include <fsl_esdhc_imx.h> #include <spl.h> +#include <asm/mach-imx/boot_mode.h> #if defined(CONFIG_SPL_BUILD) @@ -61,6 +62,8 @@ static struct ddrc ddrc_regs_val = { .dramtmg0 = 0x09081109, .addrmap0 = 0x0000001f, .addrmap1 = 0x00080808, + .addrmap2 = 0x00000000, + .addrmap3 = 0x00000000, .addrmap4 = 0x00000f0f, .addrmap5 = 0x07070707, .addrmap6 = 0x0f0f0707, @@ -100,17 +103,39 @@ static void gpr_init(void) writel(0x4F400005, &gpr_regs->gpr[1]); } +/********************************************** +* Revision Detection +* +* DDR_TYPE_DET_1 DDR_TYPE_DET_2 +* GPIO_1 GPIO_2 +* 0 1 2GB DDR3 +* 0 0 1GB DDR3 +* 1 0 512MB DDR3 +***********************************************/ static bool is_1g(void) { gpio_direction_input(IMX_GPIO_NR(1, 12)); return !gpio_get_value(IMX_GPIO_NR(1, 12)); } -static void ddr_init(void) +static bool is_2g(void) { - if (is_1g()) - ddrc_regs_val.addrmap6 = 0x0f070707; + gpio_direction_input(IMX_GPIO_NR(1, 13)); + return gpio_get_value(IMX_GPIO_NR(1, 13)); +} +static void ddr_init(void) +{ + if (is_1g()) { + if (is_2g()) { + ddrc_regs_val.addrmap0 = 0x0000001f; + ddrc_regs_val.addrmap1 = 0x00181818; + ddrc_regs_val.addrmap4 = 0x00000f0f; + ddrc_regs_val.addrmap5 = 0x04040404; + ddrc_regs_val.addrmap6 = 0x04040404; + } else + ddrc_regs_val.addrmap6 = 0x0f070707; + } mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val, &calib_param); } @@ -134,7 +159,20 @@ void reset_cpu(void) #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) -static iomux_v3_cfg_t const usdhc3_pads[] = { +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) +/* EMMC/SD */ +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 14) +static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -148,20 +186,83 @@ static iomux_v3_cfg_t const usdhc3_pads[] = { MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; -static struct fsl_esdhc_cfg usdhc_cfg[1] = { +static struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC3_BASE_ADDR}, + {USDHC1_BASE_ADDR}, }; int board_mmc_getcd(struct mmc *mmc) { - /* Assume uSDHC3 emmc is always present */ - return 1; + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); /* Assume uSDHC1 sd is always present */ + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); /* Assume uSDHC3 emmc is always present */ + break; + } + + return ret; } int board_mmc_init(struct bd_info *bis) { - imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + int ret; + u32 index = 0; + + /* + * Following map is done: + * (USDHC) (Physical Port) + * usdhc3 SOM MicroSD/MMC + * usdhc1 Carrier board MicroSD + * Always set boot USDHC as mmc0 + */ + + imx_iomux_v3_setup_multiple_pads( + usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_direction_input(USDHC1_CD_GPIO); + + switch (get_boot_device()) { + case SD1_BOOT: + usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].max_bus_width = 4; + break; + case MMC3_BOOT: + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 8; + usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[1].max_bus_width = 4; + break; + case SD3_BOOT: + default: + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].max_bus_width = 4; + usdhc_cfg[1].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[1].max_bus_width = 4; + break; + } + + for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); + if (ret) + return ret; + } + + return 0; } #endif diff --git a/common/splash.c b/common/splash.c index 0e520cc103..d29e08c2ce 100644 --- a/common/splash.c +++ b/common/splash.c @@ -57,7 +57,7 @@ static struct splash_location default_splash_locations[] = { #include <bmp_logo_data.h> -static int splash_video_logo_load(void) +int splash_video_logo_load(void) { char *splashimage; ulong bmp_load_addr; diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 3adba803dd..c90237487f 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -15,8 +15,13 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" CONFIG_TARGET_PICO_IMX7D=y CONFIG_SPL_MMC=y +CONFIG_SPL_DM_MMC=y +CONFIG_SPL_MMC_BOOT=y +CONFIG_MMC_VERBOSE=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y +CONFIG_SUPPORT_SPL=y +CONFIG_SPL_FS_FAT=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index cbfe346820..38070aac44 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -15,8 +15,13 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" CONFIG_TARGET_PICO_IMX7D=y CONFIG_SPL_MMC=y +CONFIG_SPL_DM_MMC=y +CONFIG_SPL_MMC_BOOT=y +CONFIG_MMC_VERBOSE=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y +CONFIG_SUPPORT_SPL=y +CONFIG_SPL_FS_FAT=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index a9d21eb02c..8dfdb30f46 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -14,8 +14,13 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" CONFIG_TARGET_PICO_IMX7D=y CONFIG_SPL_MMC=y +CONFIG_SPL_DM_MMC=y +CONFIG_SPL_MMC_BOOT=y +CONFIG_MMC_VERBOSE=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y +CONFIG_SUPPORT_SPL=y +CONFIG_SPL_FS_FAT=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xa0000000 diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 6a2f87a8bb..1ab569ba7f 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -15,8 +15,13 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" CONFIG_TARGET_PICO_IMX7D=y CONFIG_SPL_MMC=y +CONFIG_SPL_DM_MMC=y +CONFIG_SPL_MMC_BOOT=y +CONFIG_MMC_VERBOSE=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y +CONFIG_SUPPORT_SPL=y +CONFIG_SPL_FS_FAT=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 3adba803dd..c90237487f 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -15,8 +15,13 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" CONFIG_TARGET_PICO_IMX7D=y CONFIG_SPL_MMC=y +CONFIG_SPL_DM_MMC=y +CONFIG_SPL_MMC_BOOT=y +CONFIG_MMC_VERBOSE=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y +CONFIG_SUPPORT_SPL=y +CONFIG_SPL_FS_FAT=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 79aa398e1e..6fb4da0b9e 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -15,8 +15,13 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi" CONFIG_TARGET_PICO_IMX7D=y CONFIG_SPL_MMC=y +CONFIG_SPL_DM_MMC=y +CONFIG_SPL_MMC_BOOT=y +CONFIG_MMC_VERBOSE=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y +CONFIG_SUPPORT_SPL=y +CONFIG_SPL_FS_FAT=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 7fbf2c3f55..0e13815952 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -9,19 +9,12 @@ #define __PICO_IMX7D_CONFIG_H #include "mx7_common.h" - #include "imx7_spl.h" -#ifdef CONFIG_SPL_OS_BOOT -/* Falcon Mode */ - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#endif - #define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR /* MMC Config */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR #define CONFIG_DFU_ENV_SETTINGS \ "dfu_alt_info=" \ @@ -87,9 +80,11 @@ "name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \ "fastboot_partition_alias_system=rootfs\0" \ "setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \ + "mmcautodetect=yes\0" \ PICO_BOOT_ENV #define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 3) \ func(MMC, mmc, 0) \ func(USB, usb, 0) \ func(PXE, pxe, na) \ @@ -98,6 +93,9 @@ #include <config_distro_bootcmd.h> #include <linux/stringify.h> +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) + /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR @@ -113,10 +111,13 @@ /* Environment starts at 768k = 768 * 1024 = 786432 */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 0 /* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 #endif -- 2.35.1.windows.2

3 2

Bug in ext2load?
by Gary Johnson 01 Oct '22

01 Oct '22

I think I've found a bug in the ext2load command. When the file being read is a sparse file, the command fails as in this example. => ext2load usb 0:1 $load_addr firmware_ls2088ardb_norboot.img fs_devread read outside partition 60063712 Failed to load 'firmware_ls2088ardb_norboot.img' However, if the same image file is copied to the USB flash drive on the build machine so that it is not sparse, that is, with "cp --sparse=never ...", then the ext2load command on the target machine succeeds. I think the problem may be in the ext4fs_read_file() command in fs/ext4/ext4fs.c. That is the only function I see in the path from the ext2load command to the error message that does anything explicitly with blocks. Also, this comment at the top of that function suggests that someone tried to optimize the reading of the file and may have missed some sparse-file condition. /* * Taken from openmoko-kernel mailing list: By Andy green * Optimized read file API : collects and defers contiguous sector * reads into one potentially more efficient larger sequential read action */ However, I did not try to debug the problem further, as using "cp --sparse=never" is an adequate workaround and I have more pressing work to do. It appears that the ext2load command runs off the end of the list of blocks in the inode and tries to read beyond the end of the partition. => usb storage Device 0: Vendor: USB Rev: 1.00 Prod: SanDisk 3.2Gen1 Type: Removable Hard Disk Capacity: 29328.0 MB = 28.6 GB (60063744 x 512) Note that the drive capacity is 32 sectors less than the sector reported in the error message. According to the part list command, the partition starts at sector 32, and the number of sectors available matches the number reported in the error message, so this adds up. => part list usb 0 Partition Map for USB device 0 -- Partition Type: DOS Part Start Sector Num Sectors UUID Type 1 32 60063712 eca4cd09-01 83 This error happens with two versions of U-Boot: U-Boot 2016.092.0+ga06b209 (Mar 30 2017 - 01:15:01 +0800) U-Boot 2021.04-ge2eba0cd58 (Aug 27 2021 - 22:23:21 +0800) The last change to fs/ext4/ext4fs.c appears to have been made at commit e6f6f9e648 (2020-05-10). Let me know if you need any addtional information or if I missed something and am wrong about all this. Regards, Gary

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[PATCH] usb: common: Detect USB storage media with "miscellaneous" USB devices
by Christian Kohlschütter 01 Oct '22

01 Oct '22

When detecting USB storage devices, we currently skip everything that is not marked as "undefined device class". Composite devices such as tinyusb's CDC+MSC identify as "miscellaneous" (class 0xEF). Introduce a new constant, USB_CLASS_MISC (0xEF), and allow the detection process to proceed for USB devices with this device class. Signed-off-by: Christian Kohlschütter <christian(a)kohlschutter.com> --- common/usb_storage.c | 3 ++- include/usb_defs.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/common/usb_storage.c b/common/usb_storage.c index eaa31374ef..727b364b3d 100644 --- a/common/usb_storage.c +++ b/common/usb_storage.c @@ -1322,7 +1322,8 @@ int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, /* let's examine the device now */ iface = &dev->config.if_desc[ifnum]; - if (dev->descriptor.bDeviceClass != 0 || + if ((dev->descriptor.bDeviceClass != 0 && dev->descriptor.bDeviceClass + != USB_CLASS_MISC) || iface->desc.bInterfaceClass != USB_CLASS_MASS_STORAGE || iface->desc.bInterfaceSubClass < US_SC_MIN || iface->desc.bInterfaceSubClass > US_SC_MAX) { diff --git a/include/usb_defs.h b/include/usb_defs.h index 6dd2c997f9..f8f87d6a8a 100644 --- a/include/usb_defs.h +++ b/include/usb_defs.h @@ -19,6 +19,7 @@ #define USB_CLASS_MASS_STORAGE 8 #define USB_CLASS_HUB 9 #define USB_CLASS_DATA 10 +#define USB_CLASS_MISC 0xef #define USB_CLASS_VENDOR_SPEC 0xff /* some HID sub classes */ -- 2.36.2

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[RFC PATCH v1 0/3] SPL NVMe support
by Mayuresh Chitale 01 Oct '22

01 Oct '22

This patchset adds support to load images of the SPL's next booting stage from a NVMe device. Mayuresh Chitale (3): spl: Add Kconfig options for NVME nvme: pci: Enable for SPL common: spl: Add spl NVMe boot support arch/riscv/include/asm/spl.h | 1 + common/spl/Kconfig | 25 ++++++++++++++++++++ common/spl/Makefile | 1 + common/spl/spl_nvme.c | 44 ++++++++++++++++++++++++++++++++++++ drivers/Makefile | 2 +- drivers/nvme/Makefile | 2 +- drivers/nvme/nvme_pci.c | 1 + drivers/pci/Kconfig | 7 ++++++ drivers/pci/pci-uclass.c | 3 ++- 9 files changed, 83 insertions(+), 3 deletions(-) create mode 100644 common/spl/spl_nvme.c -- 2.25.1

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