September 2022 - U-Boot

[PATCH] tools: kwbimage: Verify maximal kwbimage header size
by Pali Rohár 06 Oct '22

06 Oct '22

BootROM loads kwbimage header to L2-SRAM and BootROM reserve only 192 kB for it. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- tools/kwbimage.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/kwbimage.c b/tools/kwbimage.c index 94b768539222..6abb9f2d5c01 100644 --- a/tools/kwbimage.c +++ b/tools/kwbimage.c @@ -1969,6 +1969,9 @@ static int kwbimage_verify_header(unsigned char *ptr, int image_size, uint32_t size; uint8_t csum; + if (header_size > 192*1024) + return -FDT_ERR_BADSTRUCTURE; + if (header_size > image_size) return -FDT_ERR_BADSTRUCTURE; -- 2.20.1

2 2

[PATCH] mtd: nand: pxa3xx: simplify ECC hardware parameters
by Chris Packham 06 Oct '22

06 Oct '22

Replace the if/else chain in pxa_ecc_init() with a lookup table. This makes the code more concise and hopefully easier to follow. Remove the unused ecc_layout tables and replace it with a single dummy one (the pxa3xx driver has never used this but the mtd subsystem expects it to be provided). Tested on an Allied Telesis x530 switch with Micron MT29F2G08ABAEAWP NAND Flash. Signed-off-by: Chris Packham <judge.packham(a)gmail.com> --- This code was taken from the Marvell SDK for the AC5/AC5X integrated switch/CPU. There are other changes to support the SoC which I will likely attempt to upstream soon but I think this stands on it's own merit as a nice clean up. Reports of testing on other combinations of hardware would be greatly appreciated. drivers/mtd/nand/raw/pxa3xx_nand.c | 247 ++++++++--------------------- 1 file changed, 68 insertions(+), 179 deletions(-) diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c index 9c29e8a6c214..fcd1b9c63614 100644 --- a/drivers/mtd/nand/raw/pxa3xx_nand.c +++ b/drivers/mtd/nand/raw/pxa3xx_nand.c @@ -330,89 +330,44 @@ static struct nand_bbt_descr bbt_mirror_descr = { }; #endif -static struct nand_ecclayout ecc_layout_2KB_bch4bit = { - .eccbytes = 32, - .eccpos = { - 32, 33, 34, 35, 36, 37, 38, 39, - 40, 41, 42, 43, 44, 45, 46, 47, - 48, 49, 50, 51, 52, 53, 54, 55, - 56, 57, 58, 59, 60, 61, 62, 63}, - .oobfree = { {2, 30} } +struct marvell_hw_ecc_layout { + int page_size; + int strength; + unsigned int ecc_size; + unsigned int nfullchunks; + unsigned int chunk_size; + unsigned int spare_size; + unsigned int last_chunk_size; + unsigned int last_spare_size; }; -static struct nand_ecclayout ecc_layout_2KB_bch8bit = { - .eccbytes = 64, - .eccpos = { - 32, 33, 34, 35, 36, 37, 38, 39, - 40, 41, 42, 43, 44, 45, 46, 47, - 48, 49, 50, 51, 52, 53, 54, 55, - 56, 57, 58, 59, 60, 61, 62, 63, - 64, 65, 66, 67, 68, 69, 70, 71, - 72, 73, 74, 75, 76, 77, 78, 79, - 80, 81, 82, 83, 84, 85, 86, 87, - 88, 89, 90, 91, 92, 93, 94, 95}, - .oobfree = { {1, 4}, {6, 26} } +static const struct marvell_hw_ecc_layout nfc_layouts[] = { + /* page_size strength ecc_size nfullchunks chunk_size spare_size last_chunk last_spare */ + { 512, 1, 8, 1, 512, 8, 0, 0 }, + { 2048, 1, 24, 1, 2048, 40, 0, 0 }, + + { 2048, 4, 32, 1, 2048, 32, 0, 0 }, + { 2048, 8, 32, 1, 1024, 0, 1024, 32 }, + { 2048, 12, 32, 2, 704, 0, 640, 0 }, + { 2048, 16, 32, 4, 512, 0, 0, 32 }, + { 4096, 4, 32, 2, 2048, 32, 0, 0 }, + { 4096, 8, 32, 4, 1024, 0, 0, 64 }, + { 4096, 12, 32, 5, 704, 0, 576, 32 }, + { 4096, 16, 32, 8, 512, 0, 0, 32 }, + + { 8192, 4, 32, 4, 2048, 32, 0, 0 }, + { 8192, 8, 32, 8, 1024, 0, 0, 160 }, + { 8192, 12, 32, 11, 704, 0, 448, 64 }, + { 8192, 16, 32, 16, 512, 0, 0, 32 }, + { }, }; -static struct nand_ecclayout ecc_layout_4KB_bch4bit = { - .eccbytes = 64, - .eccpos = { - 32, 33, 34, 35, 36, 37, 38, 39, - 40, 41, 42, 43, 44, 45, 46, 47, - 48, 49, 50, 51, 52, 53, 54, 55, - 56, 57, 58, 59, 60, 61, 62, 63, - 96, 97, 98, 99, 100, 101, 102, 103, - 104, 105, 106, 107, 108, 109, 110, 111, - 112, 113, 114, 115, 116, 117, 118, 119, - 120, 121, 122, 123, 124, 125, 126, 127}, - /* Bootrom looks in bytes 0 & 5 for bad blocks */ - .oobfree = { {6, 26}, { 64, 32} } -}; - -static struct nand_ecclayout ecc_layout_8KB_bch4bit = { - .eccbytes = 128, - .eccpos = { - 32, 33, 34, 35, 36, 37, 38, 39, - 40, 41, 42, 43, 44, 45, 46, 47, - 48, 49, 50, 51, 52, 53, 54, 55, - 56, 57, 58, 59, 60, 61, 62, 63, - - 96, 97, 98, 99, 100, 101, 102, 103, - 104, 105, 106, 107, 108, 109, 110, 111, - 112, 113, 114, 115, 116, 117, 118, 119, - 120, 121, 122, 123, 124, 125, 126, 127, - - 160, 161, 162, 163, 164, 165, 166, 167, - 168, 169, 170, 171, 172, 173, 174, 175, - 176, 177, 178, 179, 180, 181, 182, 183, - 184, 185, 186, 187, 188, 189, 190, 191, - - 224, 225, 226, 227, 228, 229, 230, 231, - 232, 233, 234, 235, 236, 237, 238, 239, - 240, 241, 242, 243, 244, 245, 246, 247, - 248, 249, 250, 251, 252, 253, 254, 255}, - - /* Bootrom looks in bytes 0 & 5 for bad blocks */ - .oobfree = { {1, 4}, {6, 26}, { 64, 32}, {128, 32}, {192, 32} } -}; - -static struct nand_ecclayout ecc_layout_4KB_bch8bit = { - .eccbytes = 128, - .eccpos = { - 32, 33, 34, 35, 36, 37, 38, 39, - 40, 41, 42, 43, 44, 45, 46, 47, - 48, 49, 50, 51, 52, 53, 54, 55, - 56, 57, 58, 59, 60, 61, 62, 63}, +static struct nand_ecclayout ecc_layout_empty = { + .eccbytes = 0, + .eccpos = { }, .oobfree = { } }; -static struct nand_ecclayout ecc_layout_8KB_bch8bit = { - .eccbytes = 256, - .eccpos = {}, - /* HW ECC handles all ECC data and all spare area is free for OOB */ - .oobfree = {{0, 160} } -}; - #define NDTR0_tCH(c) (min((c), 7) << 19) #define NDTR0_tCS(c) (min((c), 7) << 16) #define NDTR0_tWH(c) (min((c), 7) << 11) @@ -1549,113 +1504,47 @@ static int pxa_ecc_init(struct pxa3xx_nand_info *info, struct nand_ecc_ctrl *ecc, int strength, int ecc_stepsize, int page_size) { - if (strength == 1 && ecc_stepsize == 512 && page_size == 2048) { - info->nfullchunks = 1; - info->ntotalchunks = 1; - info->chunk_size = 2048; - info->spare_size = 40; - info->ecc_size = 24; - ecc->mode = NAND_ECC_HW; - ecc->size = 512; - ecc->strength = 1; + int i = 0; - } else if (strength == 1 && ecc_stepsize == 512 && page_size == 512) { - info->nfullchunks = 1; - info->ntotalchunks = 1; - info->chunk_size = 512; - info->spare_size = 8; - info->ecc_size = 8; - ecc->mode = NAND_ECC_HW; - ecc->size = 512; - ecc->strength = 1; + /* if ecc strength is 1 ecc algo is Hamming else bch */ + info->ecc_bch = (strength == 1) ? 0 : 1; - /* - * Required ECC: 4-bit correction per 512 bytes - * Select: 16-bit correction per 2048 bytes + ecc->mode = NAND_ECC_HW; + + /* ecc->layout is not in use for pxa driver (but shouldn't be NULL)*/ + if (info->ecc_bch == 1) + ecc->layout = &ecc_layout_empty; + + /* for bch actual ecc strength is 16 per chunk */ + ecc->strength = (info->ecc_bch == 1) ? 16 : 1; + + while (nfc_layouts[i].strength) { + if (strength == nfc_layouts[i].strength && page_size == nfc_layouts[i].page_size) { + info->nfullchunks = nfc_layouts[i].nfullchunks; + info->chunk_size = nfc_layouts[i].chunk_size; + info->spare_size = nfc_layouts[i].spare_size; + info->last_chunk_size = nfc_layouts[i].last_chunk_size; + info->last_spare_size = nfc_layouts[i].last_spare_size; + info->ntotalchunks = (info->last_spare_size || info->last_chunk_size) ? + info->nfullchunks + 1 : info->nfullchunks; + info->ecc_size = nfc_layouts[i].ecc_size; + break; + } + ++i; + } + + /* for bch the ecc is calculated per chunk size and for Hamming it is 512 */ + ecc->size = (info->ecc_bch) ? info->chunk_size : 512; + + /* nand_scan_tail func perform validity tests for ECC strength, and it + * assumes that all chunks are with same size. in our case when ecc is 12 + * the chunk size is 704 but the last chunk is with different size so + * we cheat it nand_scan_tail validity tests by set info->ecc_size value to 512 */ - } else if (strength == 4 && ecc_stepsize == 512 && page_size == 2048) { - info->ecc_bch = 1; - info->nfullchunks = 1; - info->ntotalchunks = 1; - info->chunk_size = 2048; - info->spare_size = 32; - info->ecc_size = 32; - ecc->mode = NAND_ECC_HW; - ecc->size = info->chunk_size; - ecc->layout = &ecc_layout_2KB_bch4bit; - ecc->strength = 16; + if (strength == 12) + ecc->size = 512; - } else if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) { - info->ecc_bch = 1; - info->nfullchunks = 2; - info->ntotalchunks = 2; - info->chunk_size = 2048; - info->spare_size = 32; - info->ecc_size = 32; - ecc->mode = NAND_ECC_HW; - ecc->size = info->chunk_size; - ecc->layout = &ecc_layout_4KB_bch4bit; - ecc->strength = 16; - - } else if (strength == 4 && ecc_stepsize == 512 && page_size == 8192) { - info->ecc_bch = 1; - info->nfullchunks = 4; - info->ntotalchunks = 4; - info->chunk_size = 2048; - info->spare_size = 32; - info->ecc_size = 32; - ecc->mode = NAND_ECC_HW; - ecc->size = info->chunk_size; - ecc->layout = &ecc_layout_8KB_bch4bit; - ecc->strength = 16; - - /* - * Required ECC: 8-bit correction per 512 bytes - * Select: 16-bit correction per 1024 bytes - */ - } else if (strength == 8 && ecc_stepsize == 512 && page_size == 2048) { - info->ecc_bch = 1; - info->nfullchunks = 1; - info->ntotalchunks = 2; - info->chunk_size = 1024; - info->spare_size = 0; - info->last_chunk_size = 1024; - info->last_spare_size = 32; - info->ecc_size = 32; - ecc->mode = NAND_ECC_HW; - ecc->size = info->chunk_size; - ecc->layout = &ecc_layout_2KB_bch8bit; - ecc->strength = 16; - - } else if (strength == 8 && ecc_stepsize == 512 && page_size == 4096) { - info->ecc_bch = 1; - info->nfullchunks = 4; - info->ntotalchunks = 5; - info->chunk_size = 1024; - info->spare_size = 0; - info->last_chunk_size = 0; - info->last_spare_size = 64; - info->ecc_size = 32; - ecc->mode = NAND_ECC_HW; - ecc->size = info->chunk_size; - ecc->layout = &ecc_layout_4KB_bch8bit; - ecc->strength = 16; - - } else if (strength == 8 && ecc_stepsize == 512 && page_size == 8192) { - info->ecc_bch = 1; - info->nfullchunks = 8; - info->ntotalchunks = 9; - info->chunk_size = 1024; - info->spare_size = 0; - info->last_chunk_size = 0; - info->last_spare_size = 160; - info->ecc_size = 32; - ecc->mode = NAND_ECC_HW; - ecc->size = info->chunk_size; - ecc->layout = &ecc_layout_8KB_bch8bit; - ecc->strength = 16; - - } else { + if (ecc_stepsize != 512 || !(nfc_layouts[i].strength)) { dev_err(info->controller.active->mtd.dev, "ECC strength %d at page size %d is not supported\n", strength, page_size); -- 2.37.2

3 2

[PATCH] board/km: remove kirkwood boards
by Holger Brunck 06 Oct '22

06 Oct '22

These boards are out of maintenance and can be removed. Signed-off-by: Holger Brunck <holger.brunck(a)hitachienergy.com> --- arch/arm/dts/Makefile | 1 - arch/arm/dts/kirkwood-km_common.dtsi | 48 --- arch/arm/dts/kirkwood-km_kirkwood.dts | 53 --- board/keymile/Kconfig | 1 - board/keymile/km_arm/Kconfig | 86 ----- board/keymile/km_arm/MAINTAINERS | 11 - board/keymile/km_arm/Makefile | 11 - board/keymile/km_arm/fpga_config.c | 255 -------------- board/keymile/km_arm/km_arm.c | 520 ----------------------------- board/keymile/km_arm/kwbimage-memphis.cfg | 179 ---------- board/keymile/km_arm/kwbimage.cfg | 161 --------- board/keymile/km_arm/kwbimage_128M16_1.cfg | 257 -------------- board/keymile/km_arm/kwbimage_256M8_1.cfg | 257 -------------- board/keymile/scripts/develop-common.txt | 2 +- configs/km_kirkwood_128m16_defconfig | 81 ----- configs/km_kirkwood_defconfig | 81 ----- configs/km_kirkwood_pci_defconfig | 81 ----- configs/kmcoge5un_defconfig | 84 ----- configs/kmnusa_defconfig | 85 ----- configs/kmsuse2_defconfig | 85 ----- include/configs/km/km_arm.h | 158 --------- include/configs/km_kirkwood.h | 118 ------- scripts/config_whitelist.txt | 1 - 23 files changed, 1 insertion(+), 2615 deletions(-) delete mode 100644 arch/arm/dts/kirkwood-km_common.dtsi delete mode 100644 arch/arm/dts/kirkwood-km_kirkwood.dts delete mode 100644 board/keymile/km_arm/Kconfig delete mode 100644 board/keymile/km_arm/MAINTAINERS delete mode 100644 board/keymile/km_arm/Makefile delete mode 100644 board/keymile/km_arm/fpga_config.c delete mode 100644 board/keymile/km_arm/km_arm.c delete mode 100644 board/keymile/km_arm/kwbimage-memphis.cfg delete mode 100644 board/keymile/km_arm/kwbimage.cfg delete mode 100644 board/keymile/km_arm/kwbimage_128M16_1.cfg delete mode 100644 board/keymile/km_arm/kwbimage_256M8_1.cfg delete mode 100644 configs/km_kirkwood_128m16_defconfig delete mode 100644 configs/km_kirkwood_defconfig delete mode 100644 configs/km_kirkwood_pci_defconfig delete mode 100644 configs/kmcoge5un_defconfig delete mode 100644 configs/kmnusa_defconfig delete mode 100644 configs/kmsuse2_defconfig delete mode 100644 include/configs/km/km_arm.h delete mode 100644 include/configs/km_kirkwood.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7330121..3f5bfca 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -58,7 +58,6 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += \ kirkwood-ib62x0.dtb \ kirkwood-iconnect.dtb \ kirkwood-is2.dtb \ - kirkwood-km_kirkwood.dtb \ kirkwood-lsxhl.dtb \ kirkwood-lschlv2.dtb \ kirkwood-net2big.dtb \ diff --git a/arch/arm/dts/kirkwood-km_common.dtsi b/arch/arm/dts/kirkwood-km_common.dtsi deleted file mode 100644 index 9d0fc51..0000000 --- a/arch/arm/dts/kirkwood-km_common.dtsi +++ /dev/null @@ -1,48 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/ { - chosen { - bootargs = "console=ttyS0,115200n8 earlyprintk"; - stdout-path = &uart0; - }; - - ocp@f1000000 { - pinctrl: pin-controller@10000 { - pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >; - pinctrl-names = "default"; - - pmx_i2c_gpio_sda: pmx-gpio-sda { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - pmx_i2c_gpio_scl: pmx-gpio-scl { - marvell,pins = "mpp9"; - marvell,function = "gpio"; - }; - }; - - serial@12000 { - status = "okay"; - clock-frequency = <200000000>; - }; - }; - - i2c { - compatible = "i2c-gpio"; - gpios = < &gpio0 8 GPIO_ACTIVE_HIGH /* sda */ - &gpio0 9 GPIO_ACTIVE_HIGH>; /* scl */ - i2c-gpio,delay-us = <2>; /* ~100 kHz */ - }; -}; - -&nand { - status = "okay"; - chip-delay = <25>; -}; - -&pciec { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; diff --git a/arch/arm/dts/kirkwood-km_kirkwood.dts b/arch/arm/dts/kirkwood-km_kirkwood.dts deleted file mode 100644 index b2c0209..0000000 --- a/arch/arm/dts/kirkwood-km_kirkwood.dts +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/dts-v1/; - -#include "kirkwood.dtsi" -#include "kirkwood-98dx4122.dtsi" -#include "kirkwood-km_common.dtsi" - -/ { - model = "Keymile Kirkwood Reference Design"; - compatible = "keymile,km_kirkwood", "marvell,kirkwood-98DX4122", "marvell,kirkwood"; - - memory { - device_type = "memory"; - reg = <0x00000000 0x08000000>; - }; - - aliases { - spi0 = &spi0; - }; -}; - -&mdio { - status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&eth0 { - status = "okay"; - ethernet0-port@0 { - phy-handle = <&ethphy0>; - }; -}; - -&spi0 { - status = "okay"; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p80", "jedec,spi-nor", "spi-flash"; - reg = <0>; - spi-max-frequency = <33000000>; - mode = <3>; - - partition@uboot { - reg = <0x000000 0x0c0000>; - label = "uboot"; - }; - }; -}; diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index f22faee..9f78443 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -167,7 +167,6 @@ config PG_WCOM_UBOOT_UPDATE source "board/keymile/km83xx/Kconfig" source "board/keymile/kmcent2/Kconfig" -source "board/keymile/km_arm/Kconfig" source "board/keymile/pg-wcom-ls102xa/Kconfig" endmenu diff --git a/board/keymile/km_arm/Kconfig b/board/keymile/km_arm/Kconfig deleted file mode 100644 index 9d222d7..0000000 --- a/board/keymile/km_arm/Kconfig +++ /dev/null @@ -1,86 +0,0 @@ -menu "KM ARM Options" - depends on ARM - -config KM_FPGA_CONFIG - bool "FPGA Configuration" - help - Include capability to change FPGA configuration. - -config KM_FPGA_FORCE_CONFIG - bool "FPGA reconfiguration" - help - If yes we force to reconfigure the FPGA always - -config KM_FPGA_NO_RESET - bool "FPGA skip reset" - help - If yes we skip triggering a reset of the FPGA - -config KM_ENV_IS_IN_SPI_NOR - bool "Environment in SPI NOR" - help - Put the U-Boot environment in the SPI NOR flash. - -config KM_PIGGY4_88E6061 - bool "Piggy via Switch 88E6061" - help - The Piggy4 board is connected via a Marvell 88E6061 switch. - -config KM_PIGGY4_88E6352 - bool "Piggy via Switch 88E6352" - help - The Piggy4 board is connected via a Marvell 88E6352 switch. - -endmenu - -if TARGET_KM_KIRKWOOD - -config SYS_BOARD - default "km_arm" - -config SYS_VENDOR - default "keymile" - -config SYS_CONFIG_NAME - default "km_kirkwood" - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select BOARD_LATE_INIT - select DM - select DM_ETH - select DM_SERIAL - select DM_SPI - select DM_SPI_FLASH - select USB - select USB_EHCI_HCD - select USB_EHCI_MARVELL - imply CMD_CRAMFS - imply CMD_DIAG - imply FS_CRAMFS - imply CMD_USB - -choice - prompt "Board model" - -config KM_COGE5UN - bool "Hitachi Power Grids COGE5UN" - -config KM_KIRKWOOD_128M16 - bool "Hitachi Power Grids Kirkwood 128M16" - -config KM_KIRKWOOD - bool "Hitachi Power Grids Kirkwood" - -config KM_KIRKWOOD_PCI - bool "Hitachi Power Grids Kirkwood PCI" - -config KM_NUSA - bool "Hitachi Power Grids Kirkwood (NUSA)" - -config KM_SUSE2 - bool "Hitachi Power Grids Kirkwood (SUSE2)" - -endchoice - -endif diff --git a/board/keymile/km_arm/MAINTAINERS b/board/keymile/km_arm/MAINTAINERS deleted file mode 100644 index bc6858b..0000000 --- a/board/keymile/km_arm/MAINTAINERS +++ /dev/null @@ -1,11 +0,0 @@ -KM_ARM BOARD -M: Holger Brunck <holger.brunck(a)hitachienergy.com> -S: Maintained -F: board/keymile/km_arm/ -F: include/configs/km_kirkwood.h -F: configs/km_kirkwood_defconfig -F: configs/km_kirkwood_128m16_defconfig -F: configs/km_kirkwood_pci_defconfig -F: configs/kmcoge5un_defconfig -F: configs/kmnusa_defconfig -F: configs/kmsuse2_defconfig diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile deleted file mode 100644 index 79ccc76..0000000 --- a/board/keymile/km_arm/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Prafulla Wadaskar <prafulla(a)marvell.com> - -obj-y := km_arm.o ../common/common.o ../common/ivm.o - -ifdef CONFIG_KM_FPGA_CONFIG -obj-y += fpga_config.o -endif diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c deleted file mode 100644 index 839b162..0000000 --- a/board/keymile/km_arm/fpga_config.c +++ /dev/null @@ -1,255 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2012 - * Valentin Lontgchamp, Keymile AG, valentin.longchamp(a)keymile.com - */ - -#include <common.h> -#include <i2c.h> -#include <linux/delay.h> -#include <linux/errno.h> - -/* GPIO Pin from kirkwood connected to PROGRAM_B pin of the xilinx FPGA */ -#define KM_XLX_PROGRAM_B_PIN 39 - -#define BOCO_ADDR 0x10 - -#define ID_REG 0x00 -#define BOCO2_ID 0x5b - -static int check_boco2(void) -{ - int ret; - u8 id; - - ret = i2c_read(BOCO_ADDR, ID_REG, 1, &id, 1); - if (ret) { - printf("%s: error reading the BOCO id !!\n", __func__); - return ret; - } - - return (id == BOCO2_ID); -} - -static int boco_clear_bits(u8 reg, u8 flags) -{ - int ret; - u8 regval; - - /* give access to the EEPROM from FPGA */ - ret = i2c_read(BOCO_ADDR, reg, 1, &regval, 1); - if (ret) { - printf("%s: error reading the BOCO @%#x !!\n", - __func__, reg); - return ret; - } - regval &= ~flags; - ret = i2c_write(BOCO_ADDR, reg, 1, &regval, 1); - if (ret) { - printf("%s: error writing the BOCO @%#x !!\n", - __func__, reg); - return ret; - } - - return 0; -} - -static int boco_set_bits(u8 reg, u8 flags) -{ - int ret; - u8 regval; - - /* give access to the EEPROM from FPGA */ - ret = i2c_read(BOCO_ADDR, reg, 1, &regval, 1); - if (ret) { - printf("%s: error reading the BOCO @%#x !!\n", - __func__, reg); - return ret; - } - regval |= flags; - ret = i2c_write(BOCO_ADDR, reg, 1, &regval, 1); - if (ret) { - printf("%s: error writing the BOCO @%#x !!\n", - __func__, reg); - return ret; - } - - return 0; -} - -#define SPI_REG 0x06 -#define CFG_EEPROM 0x02 -#define FPGA_PROG 0x04 -#define FPGA_INIT_B 0x10 -#define FPGA_DONE 0x20 - -#ifndef CONFIG_KM_FPGA_FORCE_CONFIG -static int fpga_done(void) -{ - int ret = 0; - u8 regval; - - /* this is only supported with the boco2 design */ - if (!check_boco2()) - return 0; - - ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &regval, 1); - if (ret) { - printf("%s: error reading the BOCO @%#x !!\n", - __func__, SPI_REG); - return 0; - } - - return regval & FPGA_DONE ? 1 : 0; -} -#endif /* CONFIG_KM_FPGA_FORCE_CONFIG */ - -static int skip; - -int trigger_fpga_config(void) -{ - int ret = 0; - - skip = 0; -#ifndef CONFIG_KM_FPGA_FORCE_CONFIG - /* if the FPGA is already configured, we do not want to - * reconfigure it - */ - skip = 0; - if (fpga_done()) { - printf("PCIe FPGA config: skipped\n"); - skip = 1; - return 0; - } -#endif /* CONFIG_KM_FPGA_FORCE_CONFIG */ - - if (check_boco2()) { - /* we have a BOCO2, this has to be triggered here */ - - /* make sure the FPGA_can access the EEPROM */ - ret = boco_clear_bits(SPI_REG, CFG_EEPROM); - if (ret) - return ret; - - /* trigger the config start */ - ret = boco_clear_bits(SPI_REG, FPGA_PROG | FPGA_INIT_B); - if (ret) - return ret; - - /* small delay for the pulse */ - udelay(10); - - /* up signal for pulse end */ - ret = boco_set_bits(SPI_REG, FPGA_PROG); - if (ret) - return ret; - - /* finally, raise INIT_B to remove the config delay */ - ret = boco_set_bits(SPI_REG, FPGA_INIT_B); - if (ret) - return ret; - - } else { - /* we do it the old way, with the gpio pin */ - kw_gpio_set_valid(KM_XLX_PROGRAM_B_PIN, 1); - kw_gpio_direction_output(KM_XLX_PROGRAM_B_PIN, 0); - /* small delay for the pulse */ - udelay(10); - kw_gpio_direction_input(KM_XLX_PROGRAM_B_PIN); - } - - return 0; -} - -int wait_for_fpga_config(void) -{ - int ret = 0; - u8 spictrl; - u32 timeout = 20000; - - if (skip) - return 0; - - if (!check_boco2()) { - /* we do not have BOCO2, this is not really used */ - return 0; - } - - printf("PCIe FPGA config:"); - do { - ret = i2c_read(BOCO_ADDR, SPI_REG, 1, &spictrl, 1); - if (ret) { - printf("%s: error reading the BOCO spictrl !!\n", - __func__); - return ret; - } - if (timeout-- == 0) { - printf(" FPGA_DONE timeout\n"); - return -EFAULT; - } - udelay(10); - } while (!(spictrl & FPGA_DONE)); - - printf(" done\n"); - - return 0; -} - -#if defined(CONFIG_KM_FPGA_NO_RESET) -int fpga_reset(void) -{ - /* no dedicated reset pin for FPGA */ - return 0; -} -#else - -#define PRST1 0x4 -#define PCIE_RST 0x10 -#define TRAFFIC_RST 0x04 - -int fpga_reset(void) -{ - int ret = 0; - u8 resets; - - if (!check_boco2()) { - /* we do not have BOCO2, this is not really used */ - return 0; - } - - /* if we have skipped, we only want to reset the PCIe part */ - resets = skip ? PCIE_RST : PCIE_RST | TRAFFIC_RST; - - ret = boco_clear_bits(PRST1, resets); - if (ret) - return ret; - - /* small delay for the pulse */ - udelay(10); - - ret = boco_set_bits(PRST1, resets); - if (ret) - return ret; - - return 0; -} -#endif - -/* the FPGA was configured, we configure the BOCO2 so that the EEPROM - * is available from the Bobcat SPI bus - */ -int toggle_eeprom_spi_bus(void) -{ - int ret = 0; - - if (!check_boco2()) { - /* we do not have BOCO2, this is not really used */ - return 0; - } - - ret = boco_set_bits(SPI_REG, CFG_EEPROM); - if (ret) - return ret; - - return 0; -} diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c deleted file mode 100644 index e9af090..0000000 --- a/board/keymile/km_arm/km_arm.c +++ /dev/null @@ -1,520 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Prafulla Wadaskar <prafulla(a)marvell.com> - * - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr(a)denx.de. - * - * (C) Copyright 2010 - * Heiko Schocher, DENX Software Engineering, hs(a)denx.de. - */ - -#include <common.h> -#include <env.h> -#include <i2c.h> -#include <init.h> -#include <nand.h> -#include <net.h> -#include <netdev.h> -#include <miiphy.h> -#include <spi.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/cpu.h> -#include <asm/arch/soc.h> -#include <asm/arch/mpp.h> - -#include "../common/common.h" - -DECLARE_GLOBAL_DATA_PTR; - -/* - * BOCO FPGA definitions - */ -#define BOCO 0x10 -#define REG_CTRL_H 0x02 -#define MASK_WRL_UNITRUN 0x01 -#define MASK_RBX_PGY_PRESENT 0x40 -#define REG_IRQ_CIRQ2 0x2d -#define MASK_RBI_DEFECT_16 0x01 - -/* - * PHY registers definitions - */ -#define PHY_MARVELL_OUI 0x5043 -#define PHY_MARVELL_88E1118_MODEL 0x0022 -#define PHY_MARVELL_88E1118R_MODEL 0x0024 - -#define PHY_MARVELL_PAGE_REG 0x0016 -#define PHY_MARVELL_DEFAULT_PAGE 0x0000 - -#define PHY_MARVELL_88E1118R_LED_CTRL_PAGE 0x0003 -#define PHY_MARVELL_88E1118R_LED_CTRL_REG 0x0010 - -#define PHY_MARVELL_88E1118R_LED_CTRL_RESERVED 0x1000 -#define PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB (0x7 << 0) -#define PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT (0x3 << 4) -#define PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK (0x0 << 8) - -/* I/O pin to erase flash RGPP09 = MPP43 */ -#define KM_FLASH_ERASE_ENABLE 43 - -/* Multi-Purpose Pins Functionality configuration */ -static const u32 kwmpp_config[] = { - MPP0_NF_IO2, - MPP1_NF_IO3, - MPP2_NF_IO4, - MPP3_NF_IO5, - MPP4_NF_IO6, - MPP5_NF_IO7, - MPP6_SYSRST_OUTn, - MPP7_PEX_RST_OUTn, -#if defined(CONFIG_SYS_I2C_SOFT) - MPP8_GPIO, /* SDA */ - MPP9_GPIO, /* SCL */ -#endif - MPP10_UART0_TXD, - MPP11_UART0_RXD, - MPP12_GPO, /* Reserved */ - MPP13_UART1_TXD, - MPP14_UART1_RXD, - MPP15_GPIO, /* Not used */ - MPP16_GPIO, /* Not used */ - MPP17_GPIO, /* Reserved */ - MPP18_NF_IO0, - MPP19_NF_IO1, - MPP20_GPIO, - MPP21_GPIO, - MPP22_GPIO, - MPP23_GPIO, - MPP24_GPIO, - MPP25_GPIO, - MPP26_GPIO, - MPP27_GPIO, - MPP28_GPIO, - MPP29_GPIO, - MPP30_GPIO, - MPP31_GPIO, - MPP32_GPIO, - MPP33_GPIO, - MPP34_GPIO, /* CDL1 (input) */ - MPP35_GPIO, /* CDL2 (input) */ - MPP36_GPIO, /* MAIN_IRQ (input) */ - MPP37_GPIO, /* BOARD_LED */ - MPP38_GPIO, /* Piggy3 LED[1] */ - MPP39_GPIO, /* Piggy3 LED[2] */ - MPP40_GPIO, /* Piggy3 LED[3] */ - MPP41_GPIO, /* Piggy3 LED[4] */ - MPP42_GPIO, /* Piggy3 LED[5] */ - MPP43_GPIO, /* Piggy3 LED[6] */ - MPP44_GPIO, /* Piggy3 LED[7], BIST_EN_L */ - MPP45_GPIO, /* Piggy3 LED[8] */ - MPP46_GPIO, /* Reserved */ - MPP47_GPIO, /* Reserved */ - MPP48_GPIO, /* Reserved */ - MPP49_GPIO, /* SW_INTOUTn */ - 0 -}; - -static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; - -#if (defined(CONFIG_KM_PIGGY4_88E6061)|defined(CONFIG_KM_PIGGY4_88E6352)) -/* - * All boards with PIGGY4 connected via a simple switch have ethernet always - * present. - */ -int ethernet_present(void) -{ - return 1; -} -#else -int ethernet_present(void) -{ - uchar buf; - int ret = 0; - - if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { - printf("%s: Error reading Boco\n", __func__); - return -1; - } - if ((buf & MASK_RBX_PGY_PRESENT) == MASK_RBX_PGY_PRESENT) - ret = 1; - - return ret; -} -#endif - -static int initialize_unit_leds(void) -{ - /* - * Init the unit LEDs per default they all are - * ok apart from bootstat - */ - uchar buf; - - if (i2c_read(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { - printf("%s: Error reading Boco\n", __func__); - return -1; - } - buf |= MASK_WRL_UNITRUN; - if (i2c_write(BOCO, REG_CTRL_H, 1, &buf, 1) != 0) { - printf("%s: Error writing Boco\n", __func__); - return -1; - } - return 0; -} - -static void set_bootcount_addr(void) -{ - uchar buf[32]; - unsigned int bootcountaddr; - - bootcountaddr = gd->ram_size - BOOTCOUNT_ADDR; - sprintf((char *)buf, "0x%x", bootcountaddr); - env_set("bootcountaddr", (char *)buf); -} - -int misc_init_r(void) -{ - ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN, - CONFIG_PIGGY_MAC_ADDRESS_OFFSET); - - initialize_unit_leds(); - set_km_env(); - set_bootcount_addr(); - return 0; -} - -int board_early_init_f(void) -{ -#if defined(CONFIG_SYS_I2C_SOFT) - u32 tmp; - - /* set the 2 bitbang i2c pins as output gpios */ - tmp = readl(MVEBU_GPIO0_BASE + 4); - writel(tmp & (~KM_KIRKWOOD_SOFT_I2C_GPIOS), MVEBU_GPIO0_BASE + 4); -#endif - /* adjust SDRAM size for bank 0 */ - mvebu_sdram_size_adjust(0); - kirkwood_mpp_conf(kwmpp_config, NULL); - return 0; -} - -int board_init(void) -{ - /* address of boot parameters */ - gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; - - /* - * The KM_FLASH_GPIO_PIN switches between using a - * NAND or a SPI FLASH. Set this pin on start - * to NAND mode. - */ - kw_gpio_set_valid(KM_FLASH_GPIO_PIN, 1); - kw_gpio_direction_output(KM_FLASH_GPIO_PIN, 1); - -#if defined(CONFIG_SYS_I2C_SOFT) - /* - * Reinit the GPIO for I2C Bitbang driver so that the now - * available gpio framework is consistent. The calls to - * direction output in are not necessary, they are already done in - * board_early_init_f - */ - kw_gpio_set_valid(KM_KIRKWOOD_SDA_PIN, 1); - kw_gpio_set_valid(KM_KIRKWOOD_SCL_PIN, 1); -#endif - -#if defined(CONFIG_SYS_EEPROM_WREN) - kw_gpio_set_valid(KM_KIRKWOOD_ENV_WP, 38); - kw_gpio_direction_output(KM_KIRKWOOD_ENV_WP, 1); -#endif - -#if defined(CONFIG_KM_FPGA_CONFIG) - trigger_fpga_config(); -#endif - - return 0; -} - -int board_late_init(void) -{ -#if defined(CONFIG_KM_COGE5UN) - u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); - - /* if pin 1 do full erase */ - if (dip_switch != 0) { - /* start bootloader */ - puts("DIP: Enabled\n"); - env_set("actual_bank", "0"); - } -#endif - -#if defined(CONFIG_KM_FPGA_CONFIG) - wait_for_fpga_config(); - fpga_reset(); - toggle_eeprom_spi_bus(); -#endif - return 0; -} - -static const u32 spi_mpp_config[] = { - MPP1_SPI_MOSI, - MPP2_SPI_SCK, - MPP3_SPI_MISO, - 0 -}; - -static u32 spi_mpp_backup[4]; - -int mvebu_board_spi_claim_bus(struct udevice *dev) -{ - spi_mpp_backup[3] = 0; - - /* set new spi mpp config and save current one */ - kirkwood_mpp_conf(spi_mpp_config, spi_mpp_backup); - - kw_gpio_set_value(KM_FLASH_GPIO_PIN, 0); - - return 0; -} - -int mvebu_board_spi_release_bus(struct udevice *dev) -{ - /* restore saved mpp config */ - kirkwood_mpp_conf(spi_mpp_backup, NULL); - - kw_gpio_set_value(KM_FLASH_GPIO_PIN, 1); - - return 0; -} - -#if (defined(CONFIG_KM_PIGGY4_88E6061)) - -#define PHY_LED_SEL_REG 0x18 -#define PHY_LED0_LINK (0x5) -#define PHY_LED1_ACT (0x8 << 4) -#define PHY_LED2_INT (0xe << 8) -#define PHY_SPEC_CTRL_REG 0x1c -#define PHY_RGMII_CLK_STABLE (0x1 << 10) -#define PHY_CLSA (0x1 << 1) - -/* Configure and enable MV88E3018 PHY */ -void reset_phy(void) -{ - char *name = "egiga0"; - unsigned short reg; - - if (miiphy_set_current_dev(name)) - return; - - /* RGMII clk transition on data stable */ - if (miiphy_read(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, &reg)) - printf("Error reading PHY spec ctrl reg\n"); - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_SPEC_CTRL_REG, - reg | PHY_RGMII_CLK_STABLE | PHY_CLSA)) - printf("Error writing PHY spec ctrl reg\n"); - - /* leds setup */ - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, PHY_LED_SEL_REG, - PHY_LED0_LINK | PHY_LED1_ACT | PHY_LED2_INT)) - printf("Error writing PHY LED reg\n"); - - /* reset the phy */ - miiphy_reset(name, CONFIG_PHY_BASE_ADR); -} -#elif defined(CONFIG_KM_PIGGY4_88E6352) - -#include <mv88e6352.h> - -#if defined(CONFIG_KM_NUSA) -struct mv88e_sw_reg extsw_conf[] = { - /* - * port 0, PIGGY4, autoneg - * first the fix for the 1000Mbits Autoneg, this is from - * a Marvell errata, the regs are undocumented - */ - { PHY(0), PHY_PAGE, AN1000FIX_PAGE }, - { PHY(0), PHY_STATUS, AN1000FIX }, - { PHY(0), PHY_PAGE, 0 }, - /* now the real port and phy configuration */ - { PORT(0), PORT_PHY, NO_SPEED_FOR }, - { PORT(0), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, - { PHY(0), PHY_1000_CTRL, NO_ADV }, - { PHY(0), PHY_SPEC_CTRL, AUTO_MDIX_EN }, - { PHY(0), PHY_CTRL, PHY_100_MBPS | AUTONEG_EN | AUTONEG_RST | - FULL_DUPLEX }, - /* port 1, unused */ - { PORT(1), PORT_CTRL, PORT_DIS }, - { PHY(1), PHY_CTRL, PHY_PWR_DOWN }, - { PHY(1), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, - /* port 2, unused */ - { PORT(2), PORT_CTRL, PORT_DIS }, - { PHY(2), PHY_CTRL, PHY_PWR_DOWN }, - { PHY(2), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, - /* port 3, unused */ - { PORT(3), PORT_CTRL, PORT_DIS }, - { PHY(3), PHY_CTRL, PHY_PWR_DOWN }, - { PHY(3), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, - /* port 4, ICNEV, SerDes, SGMII */ - { PORT(4), PORT_STATUS, NO_PHY_DETECT }, - { PORT(4), PORT_PHY, SPEED_1000_FOR }, - { PORT(4), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, - { PHY(4), PHY_CTRL, PHY_PWR_DOWN }, - { PHY(4), PHY_SPEC_CTRL, SPEC_PWR_DOWN }, - /* port 5, CPU_RGMII */ - { PORT(5), PORT_PHY, RX_RGMII_TIM | TX_RGMII_TIM | FLOW_CTRL_EN | - FLOW_CTRL_FOR | LINK_VAL | LINK_FOR | FULL_DPX | - FULL_DPX_FOR | SPEED_1000_FOR }, - { PORT(5), PORT_CTRL, FORWARDING | EGRS_FLD_ALL }, - /* port 6, unused, this port has no phy */ - { PORT(6), PORT_CTRL, PORT_DIS }, -}; -#else -struct mv88e_sw_reg extsw_conf[] = {}; -#endif - -void reset_phy(void) -{ -#if defined(CONFIG_KM_MVEXTSW_ADDR) - char *name = "egiga0"; - - if (miiphy_set_current_dev(name)) - return; - - mv88e_sw_program(name, CONFIG_KM_MVEXTSW_ADDR, extsw_conf, - ARRAY_SIZE(extsw_conf)); - mv88e_sw_reset(name, CONFIG_KM_MVEXTSW_ADDR); -#endif -} - -#else -/* Configure and enable MV88E1118 PHY on the piggy*/ -void reset_phy(void) -{ - unsigned int oui; - unsigned char model, rev; - - char *name = "egiga0"; - - if (miiphy_set_current_dev(name)) - return; - - /* reset the phy */ - miiphy_reset(name, CONFIG_PHY_BASE_ADR); - - /* get PHY model */ - if (miiphy_info(name, CONFIG_PHY_BASE_ADR, &oui, &model, &rev)) - return; - - /* check for Marvell 88E1118R Gigabit PHY (PIGGY3) */ - if (oui == PHY_MARVELL_OUI && - model == PHY_MARVELL_88E1118R_MODEL) { - /* set page register to 3 */ - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, - PHY_MARVELL_PAGE_REG, - PHY_MARVELL_88E1118R_LED_CTRL_PAGE)) - printf("Error writing PHY page reg\n"); - - /* - * leds setup as printed on PCB: - * LED2 (Link): 0x0 (On Link, Off No Link) - * LED1 (Activity): 0x3 (On Activity, Off No Activity) - * LED0 (Speed): 0x7 (On 1000 MBits, Off Else) - */ - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, - PHY_MARVELL_88E1118R_LED_CTRL_REG, - PHY_MARVELL_88E1118R_LED_CTRL_RESERVED | - PHY_MARVELL_88E1118R_LED_CTRL_LED0_1000MB | - PHY_MARVELL_88E1118R_LED_CTRL_LED1_ACT | - PHY_MARVELL_88E1118R_LED_CTRL_LED2_LINK)) - printf("Error writing PHY LED reg\n"); - - /* set page register back to 0 */ - if (miiphy_write(name, CONFIG_PHY_BASE_ADR, - PHY_MARVELL_PAGE_REG, - PHY_MARVELL_DEFAULT_PAGE)) - printf("Error writing PHY page reg\n"); - } -} -#endif - -#if defined(CONFIG_HUSH_INIT_VAR) -int hush_init_var(void) -{ - ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); - return 0; -} -#endif - -#if defined(CONFIG_SYS_I2C_SOFT) -void set_sda(int state) -{ - I2C_ACTIVE; - I2C_SDA(state); -} - -void set_scl(int state) -{ - I2C_SCL(state); -} - -int get_sda(void) -{ - I2C_TRISTATE; - return I2C_READ; -} - -int get_scl(void) -{ - return kw_gpio_get_value(KM_KIRKWOOD_SCL_PIN) ? 1 : 0; -} -#endif - -#if defined(CONFIG_POST) - -#define KM_POST_EN_L 44 -#define POST_WORD_OFF 8 - -int post_hotkeys_pressed(void) -{ - if (IS_ENABLED(CONFIG_KM_COGE5UN)) - return kw_gpio_get_value(KM_POST_EN_L); - else - return !kw_gpio_get_value(KM_POST_EN_L); -} - -ulong post_word_load(void) -{ - void *addr = (void *)(gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); - - return in_le32(addr); - -} -void post_word_store(ulong value) -{ - void *addr = (void *)(gd->ram_size - BOOTCOUNT_ADDR + POST_WORD_OFF); - - out_le32(addr, value); -} - -int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) -{ - *vstart = CONFIG_SYS_SDRAM_BASE; - - /* we go up to relocation plus a 1 MB margin */ - *size = CONFIG_SYS_TEXT_BASE - (1 << 20); - - return 0; -} -#endif - -#if defined(CONFIG_SYS_EEPROM_WREN) -int eeprom_write_enable(unsigned int dev_addr, int state) -{ - kw_gpio_set_value(KM_KIRKWOOD_ENV_WP, !state); - - return !kw_gpio_get_value(KM_KIRKWOOD_ENV_WP); -} -#endif diff --git a/board/keymile/km_arm/kwbimage-memphis.cfg b/board/keymile/km_arm/kwbimage-memphis.cfg deleted file mode 100644 index d850e10..0000000 --- a/board/keymile/km_arm/kwbimage-memphis.cfg +++ /dev/null @@ -1,179 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2010 -# Heiko Schocher, DENX Software Engineering, hs(a)denx.de. -# -# (C) Copyright 2011 -# Valentin Longchamp, Keymile AG, valentin.longchamp(a)keymile.com -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM spi # Boot from SPI flash - -DATA 0xFFD10000 0x01112222 # MPP Control 0 Register -# bit 3-0: MPPSel0 2, NF_IO[2] -# bit 7-4: MPPSel1 2, NF_IO[3] -# bit 12-8: MPPSel2 2, NF_IO[4] -# bit 15-12: MPPSel3 2, NF_IO[5] -# bit 19-16: MPPSel4 1, NF_IO[6] -# bit 23-20: MPPSel5 1, NF_IO[7] -# bit 27-24: MPPSel6 1, SYSRST_O -# bit 31-28: MPPSel7 0, GPO[7] - -DATA 0xFFD10004 0x03303300 - -DATA 0xFFD10008 0x00001100 # MPP Control 2 Register -# bit 3-0: MPPSel16 0, GPIO[16] -# bit 7-4: MPPSel17 0, GPIO[17] -# bit 12-8: MPPSel18 1, NF_IO[0] -# bit 15-12: MPPSel19 1, NF_IO[1] -# bit 19-16: MPPSel20 0, GPIO[20] -# bit 23-20: MPPSel21 0, GPIO[21] -# bit 27-24: MPPSel22 0, GPIO[22] -# bit 31-28: MPPSel23 0, GPIO[23] - -DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register -DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register -DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register - -# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! -# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage - -#Dram initalization -DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register -# bit13-0: 0x4E0 (DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x38543000 # DDR Controller Control Low -# bit 3-0: 0 reserved -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 5=recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 8= CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay - -DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1) -# bit3-0: TRAS lsbs -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP - -DATA 0xFFD0140C 0x00000A3E # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required - -DATA 0xFFD01410 0x00000001 # DDR Address Control -# bit1-0: 01, Cs0width=x16 -# bit3-2: 00, Cs0size=2Gb -# bit5-4: 00, Cs2width=nonexistent -# bit7-6: 00, Cs1size =nonexistent -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required - -DATA 0xFFD0141C 0x00000652 # DDR Mode -DATA 0xFFD01420 0x00000006 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 1, DDR drive strenght reduced -# bit2: 1, DDR ODT control lsd disabled -# bit5-3: 000, required -# bit6: 0, DDR ODT control msb disabled -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required - -DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 0 -# bit8 : 1 , add a sample stage -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required - -DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low -# bit3-0 : 0000, required -# bit7-4 : 0010, M_ODT assertion 2 cycles after read -# bit11-8 : 0101, M_ODT de-assertion 5 cycles after read -# bit15-12: 0100, internal ODT assertion 4 cycles after read -# bit19-16: 1000, internal ODT de-assertion 8 cycles after read -# bit31-20: 0 , required - -DATA 0xFFD0147c 0x00008451 # DDR2 SDRAM Timing High -# bit3-0 : 0001, M_ODT assertion same cycle as write -# bit7-4 : 0101, M_ODT de-assertion x cycles after write -# bit11-8 : 0100, internal ODT assertion x cycles after write -# bit15-12: 1000, internal ODT de-assertion x cycles after write - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x0F, Size (i.e. 256MB) - -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) -# bit3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 -# bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 - -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above -# bit3-2: 00, ODT1 controlled by register -# bit31-4: zero, required - -DATA 0xFFD0149C 0x0000F801 # CPU ODT Control -# bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 -# bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0 -# bit9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr -# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm -# bit13-12:3, STARTBURST ODT buffer selected, 50 ohm -# bit14 :1, STARTBURST ODT enabled -# bit15 :1, Use ODT Block - -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -# bit0=1, enable DDR init upon this register write - -# End of Header extension -DATA 0x0 0x0 diff --git a/board/keymile/km_arm/kwbimage.cfg b/board/keymile/km_arm/kwbimage.cfg deleted file mode 100644 index 6b62ce0..0000000 --- a/board/keymile/km_arm/kwbimage.cfg +++ /dev/null @@ -1,161 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2010 -# Heiko Schocher, DENX Software Engineering, hs(a)denx.de. -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM spi # Boot from SPI flash - -DATA 0xFFD10000 0x01112222 # MPP Control 0 Register -# bit 3-0: MPPSel0 2, NF_IO[2] -# bit 7-4: MPPSel1 2, NF_IO[3] -# bit 12-8: MPPSel2 2, NF_IO[4] -# bit 15-12: MPPSel3 2, NF_IO[5] -# bit 19-16: MPPSel4 1, NF_IO[6] -# bit 23-20: MPPSel5 1, NF_IO[7] -# bit 27-24: MPPSel6 1, SYSRST_O -# bit 31-28: MPPSel7 0, GPO[7] - -DATA 0xFFD10004 0x03303300 - -DATA 0xFFD10008 0x00001100 # MPP Control 2 Register -# bit 3-0: MPPSel16 0, GPIO[16] -# bit 7-4: MPPSel17 0, GPIO[17] -# bit 12-8: MPPSel18 1, NF_IO[0] -# bit 15-12: MPPSel19 1, NF_IO[1] -# bit 19-16: MPPSel20 0, GPIO[20] -# bit 23-20: MPPSel21 0, GPIO[21] -# bit 27-24: MPPSel22 0, GPIO[22] -# bit 31-28: MPPSel23 0, GPIO[23] - -DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register -DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register -DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register - -# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! -# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage - -#Dram initalization -DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register -# bit13-0: 0x400 (DDR2 clks refresh rate) -# bit23-14: zero -# bit24: 1= enable exit self refresh mode on DDR access -# bit25: 1 required -# bit29-26: zero -# bit31-30: 01 - -DATA 0xFFD01404 0x39543000 # DDR Controller Control Low -# bit 3-0: 0 reserved -# bit 4: 0=addr/cmd in smame cycle -# bit 5: 0=clk is driven during self refresh, we don't care for APX -# bit 6: 0=use recommended falling edge of clk for addr/cmd -# bit14: 0=input buffer always powered up -# bit18: 1=cpu lock transaction enabled -# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0 -# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM -# bit30-28: 3 required -# bit31: 0=no additional STARTBURST delay - -DATA 0xFFD01408 0x34136552 # DDR Timing (Low) (active cycles value +1) -# bit3-0: TRAS lsbs -# bit7-4: TRCD -# bit11- 8: TRP -# bit15-12: TWR -# bit19-16: TWTR -# bit20: TRAS msb -# bit23-21: 0x0 -# bit27-24: TRRD -# bit31-28: TRTP - -DATA 0xFFD0140C 0x00000033 # DDR Timing (High) -# bit6-0: TRFC -# bit8-7: TR2R -# bit10-9: TR2W -# bit12-11: TW2W -# bit31-13: zero required - -DATA 0xFFD01410 0x0000000D # DDR Address Control -# bit1-0: 01, Cs0width=x16 -# bit3-2: 11, Cs0size=1Gb -# bit5-4: 00, Cs2width=nonexistent -# bit7-6: 00, Cs1size =nonexistent -# bit9-8: 00, Cs2width=nonexistent -# bit11-10: 00, Cs2size =nonexistent -# bit13-12: 00, Cs3width=nonexistent -# bit15-14: 00, Cs3size =nonexistent -# bit16: 0, Cs0AddrSel -# bit17: 0, Cs1AddrSel -# bit18: 0, Cs2AddrSel -# bit19: 0, Cs3AddrSel -# bit31-20: 0 required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit0: 0, OpenPage enabled -# bit31-1: 0 required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit3-0: 0x0, DDR cmd -# bit31-4: 0 required - -DATA 0xFFD0141C 0x00000652 # DDR Mode -DATA 0xFFD01420 0x00000044 # DDR Extended Mode -# bit0: 0, DDR DLL enabled -# bit1: 0, DDR drive strenght normal -# bit2: 1, DDR ODT control lsd disabled -# bit5-3: 000, required -# bit6: 1, DDR ODT control msb, enabled -# bit9-7: 000, required -# bit10: 0, differential DQS enabled -# bit11: 0, required -# bit12: 0, DDR output buffer enabled -# bit31-13: 0 required - -DATA 0xFFD01424 0x0000F07F # DDR Controller Control High -# bit2-0: 111, required -# bit3 : 1 , MBUS Burst Chop disabled -# bit6-4: 111, required -# bit7 : 0 -# bit8 : 0 , no sample stage -# bit9 : 0 , no half clock cycle addition to dataout -# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals -# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh -# bit15-12: 1111 required -# bit31-16: 0 required -DATA 0xFFD01428 0x00074510 -DATA 0xFFD0147c 0x00007451 - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size -# bit0: 1, Window enabled -# bit1: 0, Write Protect disabled -# bit3-2: 00, CS0 hit selected -# bit23-4: ones, required -# bit31-24: 0x07, Size (i.e. 128MB) - -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low) -# bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0 -# bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0 - -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit1-0: 00, ODT0 controlled by ODT Control (low) register above -# bit3-2: 00, ODT1 controlled by register -# bit31-4: zero, required - -DATA 0xFFD0149C 0x0000FC11 # CPU ODT Control -# bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0 -# bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0 -# bit9-8: 1, ODTEn, never active -# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm - -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -# bit0=1, enable DDR init upon this register write - -# End of Header extension -DATA 0x0 0x0 diff --git a/board/keymile/km_arm/kwbimage_128M16_1.cfg b/board/keymile/km_arm/kwbimage_128M16_1.cfg deleted file mode 100644 index e30c0fe..0000000 --- a/board/keymile/km_arm/kwbimage_128M16_1.cfg +++ /dev/null @@ -1,257 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2010 -# Heiko Schocher, DENX Software Engineering, hs(a)denx.de. -# -# (C) Copyright 2012 -# Valentin Longchamp, Keymile AG, valentin.longchamp(a)keymile.com -# Stefan Bigler, Keymile AG, stefan.bigler(a)keymile.com -# -# (C) Copyright 2012 -# -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM spi # Boot from SPI flash - -DATA 0xFFD10000 0x01112222 # MPP Control 0 Register -# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) -# bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3]) -# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) -# bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5]) -# bit 19-16: 1, MPPSel4 NF_IO[6] -# bit 23-20: 1, MPPSel5 NF_IO[7] -# bit 27-24: 1, MPPSel6 SYSRST_O -# bit 31-28: 0, MPPSel7 GPO[7] - -DATA 0xFFD10004 0x03303300 # MPP Control 1 Register -# bit 3-0: 0, MPPSel8 GPIO[8] -# bit 7-4: 0, MPPSel9 GPIO[9] -# bit 12-8: 3, MPPSel10 UA0_TXD -# bit 15-12: 3, MPPSel11 UA0_RXD -# bit 19-16: 0, MPPSel12 not connected -# bit 23-20: 3, MPPSel13 UA1_TXD -# bit 27-24: 3, MPPSel14 UA1_RXD -# bit 31-28: 0, MPPSel15 GPIO[15] - -DATA 0xFFD10008 0x00001100 # MPP Control 2 Register -# bit 3-0: 0, MPPSel16 GPIO[16] -# bit 7-4: 0, MPPSel17 not connected -# bit 12-8: 1, MPPSel18 NF_IO[0] -# bit 15-12: 1, MPPSel19 NF_IO[1] -# bit 19-16: 0, MPPSel20 GPIO[20] -# bit 23-20: 0, MPPSel21 GPIO[21] -# bit 27-24: 0, MPPSel22 GPIO[22] -# bit 31-28: 0, MPPSel23 GPIO[23] - -# MPP Control 3-6 Register untouched (MPP24-49) - -DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register -# bit 2-0: 3, Reserved -# bit 5-3: 3, Reserved -# bit 6: 0, Reserved -# bit 7: 0, RGMII-pads voltage = 3.3V -# bit 10-8: 3, Reserved -# bit 13-11: 3, Reserved -# bit 14: 0, Reserved -# bit 15: 0, MPP RGMII-pads voltage = 3.3V -# bit 31-16 0x1B1B, Reserved - -DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register -# bit 0-1: 2, Tag RAM RTC RAM0 -# bit 3-2: 1, Tag RAM WTC RAM0 -# bit 7-4: 6, Reserve -# bit 9-8: 2, Valid RAM RTC RAM -# bit 11-10: 1, Valid RAM WTC RAM -# bit 13-12: 2, Dirty RAM RTC RAM -# bit 15-14: 1, Dirty RAM WTC RAM -# bit 17-16: 2, Data RAM RTC RAM0 -# bit 19-18: 1, Data RAM WTC RAM0 -# bit 21-20: 2, Data RAM RTC RAM1 -# bit 23-22: 1, Data RAM WTC RAM1 -# bit 25-24: 2, Data RAM RTC RAM2 -# bit 27-26: 1, Data RAM WTC RAM2 -# bit 29-28: 2, Data RAM RTC RAM3 -# bit 31-30: 1, Data RAM WTC RAM4 - -DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register -# bit 15-0: ???, Reserve -# bit 17-16: 2, ECC RAM RTC RAM0 -# bit 19-18: 1, ECC RAM WTC RAM0 -# bit 31-20: ???,Reserve - -# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! -# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage - -# SDRAM initalization -DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register -# bit 13-0: 0x4E0, DDR2 clks refresh rate -# bit 14: 0, reserved -# bit 15: 0, reserved -# bit 16: 0, CPU to Dram Write buffer policy -# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic -# bit 19-18: 0, reserved -# bit 23-20: 0, reserved -# bit 24: 1, enable exit self refresh mode on DDR access -# bit 25: 1, required -# bit 29-26: 0, reserved -# bit 31-30: 1, reserved - -DATA 0xFFD01404 0x36543000 # DDR Controller Control Low -# bit 3-0: 0, reserved -# bit 4: 0, 2T mode =addr/cmd in same cycle -# bit 5: 0, clk is driven during self refresh, we don't care for APX -# bit 6: 0, use recommended falling edge of clk for addr/cmd -# bit 7-11: 0, reserved -# bit 12-13: 1, reserved, required 1 -# bit 14: 0, input buffer always powered up -# bit 17-15: 0, reserved -# bit 18: 1, cpu lock transaction enabled -# bit 19: 0, reserved -# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 -# bit 27-24: 6, CL+1, STARTBURST sample stages, for freqs 200-399MHz, unbuffered DIMM -# bit 30-28: 3, required -# bit 31: 0,no additional STARTBURST delay - -DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1) -# bit 3-0: 0xE, TRAS, 15 clk (45 ns) -# bit 7-4: 0x4, TRCD, 5 clk (15 ns) -# bit 11-8: 0x4, TRP, 5 clk (15 ns) -# bit 15-12: 0x4, TWR, 5 clk (15 ns) -# bit 19-16: 0x2, TWTR, 3 clk (7.5 ns) -# bit 20: 0, extended TRAS msb -# bit 23-21: 0, reserved -# bit 27-24: 0x3, TRRD, 4 clk (10 ns) -# bit 31-28: 0x2, TRTP, 3 clk (7.5 ns) - -DATA 0xFFD0140C 0x0000003e # DDR Timing (High) -# bit 6-0: 0x3E, TRFC, 63 clk (195 ns) -# bit 8-7: 0, TR2R -# bit 10-9: 0, TR2W -# bit 12-11: 0, TW2W -# bit 31-13: 0, reserved - -DATA 0xFFD01410 0x00000001 # DDR Address Control -# bit 1-0: 1, Cs0width=x16 -# bit 3-2: 0, Cs0size=2Gb -# bit 5-4: 0, Cs1width=nonexistent -# bit 7-6: 0, Cs1size =nonexistent -# bit 9-8: 0, Cs2width=nonexistent -# bit 11-10: 0, Cs2size =nonexistent -# bit 13-12: 0, Cs3width=nonexistent -# bit 15-14: 0, Cs3size =nonexistent -# bit 16: 0, Cs0AddrSel -# bit 17: 0, Cs1AddrSel -# bit 18: 0, Cs2AddrSel -# bit 19: 0, Cs3AddrSel -# bit 31-20: 0, required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit 0: 0, OpenPage enabled -# bit 31-1: 0, required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit 3-0: 0, DDR cmd -# bit 31-4: 0, required - -DATA 0xFFD0141C 0x00000652 # DDR Mode -# bit 2-0: 2, Burst Length = 4 -# bit 3: 0, Burst Type -# bit 6-4: 5, CAS Latency = 5 -# bit 7: 0, Test mode -# bit 8: 0, DLL Reset -# bit 11-9: 3, Write recovery for auto-precharge must be 3 -# bit 12: 0, Active power down exit time, fast exit -# bit 14-13: 0, reserved -# bit 31-15: 0, reserved - -DATA 0xFFD01420 0x00000006 # DDR Extended Mode -# bit 0: 0, DDR DLL enabled -# bit 1: 1, DDR drive strength reduced -# bit 2: 1, DDR ODT control lsb, 75 ohm termination [RTT0] -# bit 5-3: 0, required -# bit 6: 0, DDR ODT control msb, 75 ohm termination [RTT1] -# bit 9-7: 0, required -# bit 10: 0, differential DQS enabled -# bit 11: 0, required -# bit 12: 0, DDR output buffer enabled -# bit 31-13: 0 required - -DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit 2-0: 7, required -# bit 3: 1, MBUS Burst Chop disabled -# bit 6-4: 7, required -# bit 7: 0, reserved -# bit 8: 1, add sample stage required for f > 266 MHz -# bit 9: 0, no half clock cycle addition to dataout -# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals -# bit 11: 0, 1/4 clock cycle skew disabled for write mesh -# bit 15-12:0xf, required -# bit 31-16: 0, required - -DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low -# bit 3-0: 0, required -# bit 7-4: 2, M_ODT assertion 2 cycles after read start command -# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command -# (ODT turn off delay 2,5 clk cycles) -# bit 15-12: 4, internal ODT time based on bit 7-4 -# with the considered SDRAM internal delay -# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 -# with the considered SDRAM internal delay -# bit 31-20: 0, required - -DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High -# bit 3-0: 2, M_ODT assertion same as bit 11-8 -# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 -# bit 11-8: 4, internal ODT assertion 2 cycles after write start command -# with the considered SDRAM internal delay -# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command -# with the considered SDRAM internal delay - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -# bit 23-0: 0, reserved -# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24] - -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size -# bit 0: 1, Window enabled -# bit 1: 0, Write Protect disabled -# bit 3-2: 0, CS0 hit selected -# bit 23-4:ones, required -# bit 31-24: 0x0F, Size (i.e. 256MB) - -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) -# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 -# bit 7-4: 0, ODT0Rd, MODT[1] not asserted -# bit 11-8: 0, required -# big 15-11: 0, required -# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 -# bit 23-20: 0, ODT0Wr, MODT[1] not asserted -# bit 27-24: 0, required -# bit 31-28: 0, required - -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above -# bit 3-2: 0, ODT1 controlled by register -# bit 31-4: 0, required - -DATA 0xFFD0149C 0x0000E801 # CPU ODT Control -# bit 3-0: 1, ODTRd, Internal ODT asserted during read from DRAM bank0 -# bit 7-4: 0, ODTWr, Internal ODT not asserted during write to DRAM -# bit 9-8: 0, ODTEn, controlled by ODTRd and ODTWr -# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm -# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm -# bit 14: 1, STARTBURST ODT enabled -# bit 15: 1, Use ODT Block - -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -# bit 0: 1, enable DDR init upon this register write -# bit 31-1: 0, reserved - -# End of Header extension -DATA 0x0 0x0 diff --git a/board/keymile/km_arm/kwbimage_256M8_1.cfg b/board/keymile/km_arm/kwbimage_256M8_1.cfg deleted file mode 100644 index 91ea5f0..0000000 --- a/board/keymile/km_arm/kwbimage_256M8_1.cfg +++ /dev/null @@ -1,257 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2012 -# Stefan Bigler, Keymile AG, stefan.bigler(a)keymile.com -# Norbert Mayer, Keymile AG, norbert.mayer(a)keymile.com -# Deepak Patel, XENTECH Limited, deepak.patel(a)xentech.co.uk -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# -# This configuration applies to COGE5 design (ARM-part) -# Two 8-Bit devices are connected on the 16-Bit bus on the same -# chip-select. The supported devices are -# MT47H256M8EB-3IT:C -# MT47H256M8EB-25EIT:C - -# Boot Media configurations -BOOT_FROM spi # Boot from SPI flash - -DATA 0xFFD10000 0x01112222 # MPP Control 0 Register -# bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2]) -# bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3]) -# bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4]) -# bit 15-12: 2, MPPSel3 SPI_MISO (1=NF_IO[5]) -# bit 19-16: 1, MPPSel4 NF_IO[6] -# bit 23-20: 1, MPPSel5 NF_IO[7] -# bit 27-24: 1, MPPSel6 SYSRST_O -# bit 31-28: 0, MPPSel7 GPO[7] - -DATA 0xFFD10004 0x03303300 # MPP Control 1 Register -# bit 3-0: 0, MPPSel8 GPIO[8] CPU_SDA bitbanged -# bit 7-4: 0, MPPSel9 GPIO[9] CPU_SCL bitbanged -# bit 12-8: 3, MPPSel10 UA0_TXD -# bit 15-12: 3, MPPSel11 UA0_RXD -# bit 19-16: 0, MPPSel12 not connected -# bit 23-20: 3, MPPSel13 GPIO[14] -# bit 27-24: 3, MPPSel14 GPIO[15] -# bit 31-28: 0, MPPSel15 GPIO[16] BOOT_FL_SEL (SPI-MUX Signal) - -DATA 0xFFD10008 0x00001100 # MPP Control 2 Register -# bit 3-0: 0, MPPSel16 GPIO[16] -# bit 7-4: 0, MPPSel17 not connected -# bit 11-8: 1, MPPSel18 NF_IO[0] -# bit 15-12: 1, MPPSel19 NF_IO[1] -# bit 19-16: 0, MPPSel20 GPIO[20] -# bit 23-20: 0, MPPSel21 GPIO[21] -# bit 27-24: 0, MPPSel22 GPIO[22] -# bit 31-28: 0, MPPSel23 GPIO[23] - -# MPP Control 3-6 Register untouched (MPP24-49) - -DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register -# bit 2-0: 3, Reserved -# bit 5-3: 3, Reserved -# bit 6: 0, Reserved -# bit 7: 0, RGMII-pads voltage = 3.3V -# bit 10-8: 3, Reserved -# bit 13-11: 3, Reserved -# bit 14: 0, Reserved -# bit 15: 0, MPP RGMII-pads voltage = 3.3V -# bit 31-16 0x1B1B, Reserved - -DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register -# bit 0-1: 2, Tag RAM RTC RAM0 -# bit 3-2: 1, Tag RAM WTC RAM0 -# bit 7-4: 6, Reserved -# bit 9-8: 2, Valid RAM RTC RAM -# bit 11-10: 1, Valid RAM WTC RAM -# bit 13-12: 2, Dirty RAM RTC RAM -# bit 15-14: 1, Dirty RAM WTC RAM -# bit 17-16: 2, Data RAM RTC RAM0 -# bit 19-18: 1, Data RAM WTC RAM0 -# bit 21-20: 2, Data RAM RTC RAM1 -# bit 23-22: 1, Data RAM WTC RAM1 -# bit 25-24: 2, Data RAM RTC RAM2 -# bit 27-26: 1, Data RAM WTC RAM2 -# bit 29-28: 2, Data RAM RTC RAM3 -# bit 31-30: 1, Data RAM WTC RAM4 - -DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register -# bit 15-0: ?, Reserved -# bit 17-16: 2, ECC RAM RTC RAM0 -# bit 19-18: 1, ECC RAM WTC RAM0 -# bit 31-20: ?,Reserved - -# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched! -# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage - -# SDRAM initalization -DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register -# bit 13-0: 0x4E0, DDR2 clks refresh rate -# bit 14: 0, reserved -# bit 15: 0, reserved -# bit 16: 0, CPU to Dram Write buffer policy -# bit 17: 0, Enable Registered DIMM or Equivalent Sampling Logic -# bit 19-18: 0, reserved -# bit 23-20: 0, reserved -# bit 24: 1, enable exit self refresh mode on DDR access -# bit 25: 1, required -# bit 29-26: 0, reserved -# bit 31-30: 1, reserved - -DATA 0xFFD01404 0x36543000 # DDR Controller Control Low -# bit 3-0: 0, reserved -# bit 4: 0, 2T mode =addr/cmd in same cycle -# bit 5: 0, clk is driven during self refresh, we don't care for APX -# bit 6: 0, use recommended falling edge of clk for addr/cmd -# bit 7-11: 0, reserved -# bit 12-13: 1, reserved, required 1 -# bit 14: 0, input buffer always powered up -# bit 17-15: 0, reserved -# bit 18: 1, cpu lock transaction enabled -# bit 19: 0, reserved -# bit 23-20: 5, recommended value for CL=4 and STARTBURST_DEL disabled bit31=0 -# bit 27-24: 6, CL+1, STARTBURST sample stages, freq 200-399MHz, unbuffer DIMM -# bit 30-28: 3, required -# bit 31: 0, no additional STARTBURST delay - -DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1) -# bit 3-0: 0xe, TRAS = 45ns -> 15 clk cycles -# bit 7-4: 0x4, TRCD = 15ns -> 5 clk cycles -# bit 11-8: 0x4, TRP = 15ns -> 5 clk cycles -# bit 15-12: 0x4, TWR = 15ns -> 5 clk cycles -# bit 19-16: 0x2, TWTR = 7,5ns -> 3 clk cycles -# bit 20: 0, extended TRAS msb -# bit 23-21: 0, reserved -# bit 27-24: 0x2, TRRD = 7,5ns -> 3 clk cycles -# bit 31-28: 0x2, TRTP = 7,5ns -> 3 clk cycles - -DATA 0xFFD0140C 0x0000003E # DDR Timing (High) -# bit 6-0: 0x3E, TRFC = 195ns -> 63 clk cycles -# bit 8-7: 0, TR2R -# bit 10-9: 0, TR2W -# bit 12-11: 0, TW2W -# bit 31-13: 0, reserved - -DATA 0xFFD01410 0x00000000 # DDR Address Control -# bit 1-0: 0, Cs0width=x8 (2 devices) -# bit 3-2: 0, Cs0size=2Gb -# bit 5-4: 0, Cs1width=nonexistent -# bit 7-6: 0, Cs1size =nonexistent -# bit 9-8: 0, Cs2width=nonexistent -# bit 11-10: 0, Cs2size =nonexistent -# bit 13-12: 0, Cs3width=nonexistent -# bit 15-14: 0, Cs3size =nonexistent -# bit 16: 0, Cs0AddrSel -# bit 17: 0, Cs1AddrSel -# bit 18: 0, Cs2AddrSel -# bit 19: 0, Cs3AddrSel -# bit 31-20: 0, required - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control -# bit 0: 0, OpenPage enabled -# bit 31-1: 0, required - -DATA 0xFFD01418 0x00000000 # DDR Operation -# bit 3-0: 0, DDR cmd -# bit 31-4: 0, required - -DATA 0xFFD0141C 0x00000652 # DDR Mode -# bit 2-0: 2, Burst Length = 4 -# bit 3: 0, Burst Type -# bit 6-4: 5, CAS Latency = 5 -# bit 7: 0, Test mode -# bit 8: 0, DLL Reset -# bit 11-9: 3, Write recovery for auto-precharge must be 3 -# bit 12: 0, Active power down exit time, fast exit -# bit 14-13: 0, reserved -# bit 31-15: 0, reserved - -DATA 0xFFD01420 0x00000006 # DDR Extended Mode -# bit 0: 0, DDR DLL enabled -# bit 1: 1, DDR drive strenght reduced -# bit 2: 1, DDR ODT control lsb, 75ohm termination [RTT0] -# bit 5-3: 0, required -# bit 6: 0, DDR ODT control msb, 75ohm termination [RTT1] -# bit 9-7: 0, required -# bit 10: 0, differential DQS enabled -# bit 11: 0, required -# bit 12: 0, DDR output buffer enabled -# bit 31-13: 0 required - -DATA 0xFFD01424 0x0000F17F # DDR Controller Control High -# bit 2-0: 7, required -# bit 3: 1, MBUS Burst Chop disabled -# bit 6-4: 7, required -# bit 7: 0, reserved -# bit 8: 1, add sample stage required for > 266Mhz -# bit 9: 0, no half clock cycle addition to dataout -# bit 10: 0, 1/4 clock cycle skew enabled for addr/ctl signals -# bit 11: 0, 1/4 clock cycle skew disabled for write mesh -# bit 15-12:0xf, required -# bit 31-16: 0, required - -DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low -# bit 3-0: 0, required -# bit 7-4: 2, M_ODT assertion 2 cycles after read start command -# bit 11-8: 5, M_ODT de-assertion 5 cycles after read start command -# (ODT turn off delay 2,5 clk cycles) -# bit 15-12: 4, internal ODT time based on bit 7-4 -# with the considered SDRAM internal delay -# bit 19-16: 8, internal ODT de-assertion based on bit 11-8 -# with the considered SDRAM internal delay -# bit 31-20: 0, required - -DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High -# bit 3-0: 2, M_ODT assertion same as bit 11-8 -# bit 7-4: 5, M_ODT de-assertion same as bit 15-12 -# bit 11-8: 4, internal ODT assertion 2 cycles after write start command -# with the considered SDRAM internal delay -# bit 15-12: 8, internal ODT de-assertion 5 cycles after write start command -# with the considered SDRAM internal delay - -DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 -# bit 23-0: 0, reserved -# bit 31-24: 0, CPU CS Window0 Base Address, addr bits [31:24] - -DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size -# bit 0: 1, Window enabled -# bit 1: 0, Write Protect disabled -# bit 3-2: 0, CS0 hit selected -# bit 23-4:ones, required -# bit 31-24:0x1F, Size (i.e. 512MB) - -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled - -DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low) -# bit 3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0 -# bit 7-4: 0, ODT0Rd, MODT[1] not asserted -# bit 11-8: 0, required -# big 15-11: 0, required -# bit 19-16: 1, ODT0Wr, MODT[0] asserted during write to DRAM CS0 -# bit 23-20: 0, ODT0Wr, MODT[1] not asserted -# bit 27-24: 0, required -# bit 31-28: 0, required - -DATA 0xFFD01498 0x00000004 # DDR ODT Control (High) -# bit 1-0: 0, ODT0 controlled by ODT Control (low) register above -# bit 3-2: 1, ODT1 never active -# bit 31-4: 0, required - -DATA 0xFFD0149C 0x0000E801 # CPU ODT Control -# bit 3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0 -# bit 7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0 -# bit 9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr -# bit 11-10: 2, DQ_ODTSel. ODT select turned on, 75 ohm -# bit 13-12: 2, STARTBURST ODT buffer selected, 75 ohm -# bit 14: 1, STARTBURST ODT enabled -# bit 15: 1, Use ODT Block - -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -# bit 0: 1, enable DDR init upon this register write -# bit 31-1: 0, reserved - -# End of Header extension -DATA 0x0 0x0 diff --git a/board/keymile/scripts/develop-common.txt b/board/keymile/scripts/develop-common.txt index 4384c0d..1bdff2f 100644 --- a/board/keymile/scripts/develop-common.txt +++ b/board/keymile/scripts/develop-common.txt @@ -8,5 +8,5 @@ tftpkernel=tftpboot ${load_addr_r} ${tftppath}/${uimage} toolchain=/opt/eldk rootfssize=0 set_uimage=printenv uimage || setenv uimage uImage -set_tftppath=if test ${hostname} = kmcoge5un; then setenv tftppath CI5UN; else if test ${hostname} = kmcoge5ne; then setenv tftppath CI5NE; else setenv tftppath ${IVM_Symbol}; fi; fi +set_tftppath=if test ${hostname} = kmcoge5ne; then setenv tftppath CI5NE; else setenv tftppath ${IVM_Symbol}; fi try_import_nfs_path=if tftpboot ${load_addr_r} ${tftppath}/nfs-path.txt; then env import -t ${load_addr_r} ${filesize}; else echo no auto nfs path imported; echo you can set nfsargs in /tftpboot/${tftppath}/nfs-path.txt and rerun develop; fi diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig deleted file mode 100644 index 054038f..0000000 --- a/configs/km_kirkwood_128m16_defconfig +++ /dev/null @@ -1,81 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage_128M16_1.cfg" -CONFIG_SYS_TEXT_BASE=0x07d00000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_TARGET_KM_KIRKWOOD=y -# CONFIG_KIRKWOOD_PCIE_INIT is not set -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_ENV_OFFSET_REDUND=0x2000 -CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood 128M16" -CONFIG_SYS_LOAD_ADDR=0x800000 -CONFIG_KM_KIRKWOOD_128M16=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_RESET_PHY_R=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_SYS_CBSIZE=512 -CONFIG_SYS_PBSIZE=532 -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -CONFIG_SYS_BOOTM_LEN=0x2000000 -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_EEPROM=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_RAM=y -CONFIG_KIRKWOOD_GPIO=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SOFT=y -CONFIG_SYS_I2C_SOFT_SLAVE=0x0 -CONFIG_SYS_I2C_MVTWSI=y -CONFIG_SYS_I2C_SLAVE=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SF_DEFAULT_SPEED=8100000 -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_BCH=y diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig deleted file mode 100644 index ac2deeb..0000000 --- a/configs/km_kirkwood_defconfig +++ /dev/null @@ -1,81 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage.cfg" -CONFIG_SYS_TEXT_BASE=0x07d00000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_TARGET_KM_KIRKWOOD=y -# CONFIG_KIRKWOOD_PCIE_INIT is not set -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_ENV_OFFSET_REDUND=0x2000 -CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood" -CONFIG_SYS_LOAD_ADDR=0x800000 -CONFIG_KM_KIRKWOOD=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_RESET_PHY_R=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_SYS_CBSIZE=512 -CONFIG_SYS_PBSIZE=532 -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -CONFIG_SYS_BOOTM_LEN=0x2000000 -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_EEPROM=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_RAM=y -CONFIG_KIRKWOOD_GPIO=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SOFT=y -CONFIG_SYS_I2C_SOFT_SLAVE=0x0 -CONFIG_SYS_I2C_MVTWSI=y -CONFIG_SYS_I2C_SLAVE=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SF_DEFAULT_SPEED=8100000 -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_BCH=y diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig deleted file mode 100644 index 8074679..0000000 --- a/configs/km_kirkwood_pci_defconfig +++ /dev/null @@ -1,81 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage.cfg" -CONFIG_SYS_TEXT_BASE=0x07d00000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_TARGET_KM_KIRKWOOD=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_ENV_OFFSET_REDUND=0x2000 -CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood PCI" -CONFIG_SYS_LOAD_ADDR=0x800000 -CONFIG_KM_FPGA_CONFIG=y -CONFIG_KM_KIRKWOOD_PCI=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_RESET_PHY_R=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_SYS_CBSIZE=512 -CONFIG_SYS_PBSIZE=532 -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -CONFIG_SYS_BOOTM_LEN=0x2000000 -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_EEPROM=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_RAM=y -CONFIG_KIRKWOOD_GPIO=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SOFT=y -CONFIG_SYS_I2C_SOFT_SLAVE=0x0 -CONFIG_SYS_I2C_MVTWSI=y -CONFIG_SYS_I2C_SLAVE=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SF_DEFAULT_SPEED=8100000 -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_BCH=y diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig deleted file mode 100644 index 5766f49..0000000 --- a/configs/kmcoge5un_defconfig +++ /dev/null @@ -1,84 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage_256M8_1.cfg" -CONFIG_SYS_TEXT_BASE=0x07d00000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_TARGET_KM_KIRKWOOD=y -# CONFIG_KIRKWOOD_PCIE_INIT is not set -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_ENV_OFFSET_REDUND=0xD0000 -CONFIG_IDENT_STRING="\nHitachi Power Grids COGE5UN" -CONFIG_SYS_LOAD_ADDR=0x800000 -CONFIG_PIGGY_MAC_ADDRESS_OFFSET=3 -CONFIG_KM_ENV_IS_IN_SPI_NOR=y -CONFIG_KM_PIGGY4_88E6352=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_RESET_PHY_R=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_SYS_CBSIZE=512 -CONFIG_SYS_PBSIZE=532 -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -CONFIG_SYS_BOOTM_LEN=0x2000000 -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_RAM=y -CONFIG_KIRKWOOD_GPIO=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SOFT=y -CONFIG_SYS_I2C_SOFT_SLAVE=0x0 -CONFIG_SYS_I2C_MVTWSI=y -CONFIG_SYS_I2C_SLAVE=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SF_DEFAULT_SPEED=8100000 -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_BCH=y diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig deleted file mode 100644 index a309aca..0000000 --- a/configs/kmnusa_defconfig +++ /dev/null @@ -1,85 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage_128M16_1.cfg" -CONFIG_SYS_TEXT_BASE=0x07d00000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_TARGET_KM_KIRKWOOD=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_ENV_OFFSET_REDUND=0xD0000 -CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood" -CONFIG_SYS_LOAD_ADDR=0x800000 -CONFIG_KM_FPGA_CONFIG=y -CONFIG_KM_ENV_IS_IN_SPI_NOR=y -CONFIG_KM_PIGGY4_88E6352=y -CONFIG_KM_NUSA=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_RESET_PHY_R=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_SYS_CBSIZE=512 -CONFIG_SYS_PBSIZE=532 -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -CONFIG_SYS_BOOTM_LEN=0x2000000 -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_RAM=y -CONFIG_KIRKWOOD_GPIO=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SOFT=y -CONFIG_SYS_I2C_SOFT_SLAVE=0x0 -CONFIG_SYS_I2C_MVTWSI=y -CONFIG_SYS_I2C_SLAVE=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SF_DEFAULT_SPEED=8100000 -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_MV88E6352_SWITCH=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_BCH=y diff --git a/configs/kmsuse2_defconfig b/configs/kmsuse2_defconfig deleted file mode 100644 index de44deb..0000000 --- a/configs/kmsuse2_defconfig +++ /dev/null @@ -1,85 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_SYS_DCACHE_OFF=y -CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_KIRKWOOD=y -CONFIG_SYS_KWD_CONFIG="board/keymile/km_arm/kwbimage_128M16_1.cfg" -CONFIG_SYS_TEXT_BASE=0x07d00000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_TARGET_KM_KIRKWOOD=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="kirkwood-km_kirkwood" -CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_ENV_OFFSET_REDUND=0xD0000 -CONFIG_IDENT_STRING="\nHitachi Power Grids Kirkwood" -CONFIG_SYS_LOAD_ADDR=0x800000 -CONFIG_KM_FPGA_CONFIG=y -CONFIG_KM_FPGA_FORCE_CONFIG=y -CONFIG_KM_FPGA_NO_RESET=y -CONFIG_KM_ENV_IS_IN_SPI_NOR=y -CONFIG_KM_SUSE2=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" -CONFIG_AUTOBOOT_STOP_STR=" " -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_RESET_PHY_R=y -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=32 -CONFIG_SYS_CBSIZE=512 -CONFIG_SYS_PBSIZE=532 -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -CONFIG_SYS_BOOTM_LEN=0x2000000 -CONFIG_CMD_ASKENV=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_EEPROM=y -CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 -CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6 -CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_BOOTP_BOOTFILESIZE=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=orion_nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:-(ubi0);" -CONFIG_CMD_UBI=y -# CONFIG_CMD_UBIFS is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NETCONSOLE=y -CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y -CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_BOOTCOUNT_RAM=y -CONFIG_KIRKWOOD_GPIO=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SOFT=y -CONFIG_SYS_I2C_SOFT_SLAVE=0x0 -CONFIG_SYS_I2C_MVTWSI=y -CONFIG_SYS_I2C_SLAVE=0x0 -CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SF_DEFAULT_SPEED=8100000 -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_MVGBE=y -CONFIG_MII=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_KIRKWOOD_SPI=y -CONFIG_BCH=y diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h deleted file mode 100644 index a91e5e8..0000000 --- a/include/configs/km/km_arm.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Prafulla Wadaskar <prafulla(a)marvell.com> - * - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr(a)denx.de. - * - * (C) Copyright 2010-2011 - * Heiko Schocher, DENX Software Engineering, hs(a)denx.de. - */ - -/* - * for linking errors see - * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html - */ - -#ifndef _CONFIG_KM_ARM_H -#define _CONFIG_KM_ARM_H - -#define CONFIG_NAND_ECC_BCH - -/* include common defines/options for all Keymile boards */ -#include "keymile-common.h" - -/* Increase max size of compressed kernel */ - -#include "asm/arch/config.h" - -/* architecture specific default bootargs */ -#define CONFIG_KM_DEF_BOOT_ARGS_CPU \ - "bootcountaddr=${bootcountaddr} ${mtdparts}" \ - " boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}" - -#define CONFIG_KM_DEF_ENV_CPU \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.kwb\0" \ - CONFIG_KM_UPDATE_UBOOT \ - "set_fdthigh=setenv fdt_high ${kernelmem}\0" \ - "checkfdt=" \ - "if cramfsls fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb; " \ - "then true; else setenv cramfsloadfdt true; " \ - "setenv boot bootm ${load_addr_r}; " \ - "echo No FDT found, booting with the kernel " \ - "appended one; fi\0" \ - "" - -/* - * NAND Flash configuration - */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* - * Other required minimal configurations - */ - -/* - * Ethernet Driver configuration - */ -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer autoneg timeout */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 - -/* - * I2C related stuff - */ -#undef CONFIG_I2C_MVTWSI -#define CONFIG_SYS_I2C_INIT_BOARD - -#define CONFIG_SYS_NUM_I2C_BUSES 6 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \ - } - -#ifndef __ASSEMBLY__ -#include <asm/arch/gpio.h> -#include <linux/delay.h> -#include <linux/stringify.h> -extern void __set_direction(unsigned pin, int high); -#define KM_KIRKWOOD_SDA_PIN 8 -#define KM_KIRKWOOD_SCL_PIN 9 -#define KM_KIRKWOOD_SOFT_I2C_GPIOS 0x0300 -#define KM_KIRKWOOD_ENV_WP 38 - -#define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0) -#define I2C_TRISTATE __set_direction(KM_KIRKWOOD_SDA_PIN, 1) -#define I2C_READ (kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0) -#define I2C_SDA(bit) kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit) -#define I2C_SCL(bit) kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit) -#endif - -#define I2C_DELAY udelay(1) -#define I2C_SOFT_DECLARATIONS - -/* - * Environment variables configurations - */ -#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR -#define CONFIG_ENV_TOTAL_SIZE 0x20000 /* no bracets! */ -#else -#define CONFIG_SYS_EEPROM_WREN -#define CONFIG_I2C_ENV_EEPROM_BUS 5 /* I2C2 (Mux-Port 5) */ -#endif - -#define KM_FLASH_GPIO_PIN 16 - -#define CONFIG_KM_UPDATE_UBOOT \ - "update=" \ - "sf probe 0;sf erase 0 +${filesize};" \ - "sf write ${load_addr_r} 0 ${filesize};\0" - -#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR -#define CONFIG_KM_NEW_ENV \ - "newenv=sf probe 0;" \ - "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \ - __stringify(CONFIG_ENV_TOTAL_SIZE)"\0" -#else -#define CONFIG_KM_NEW_ENV \ - "newenv=setenv addr 0x100000 && " \ - "i2c dev " __stringify(CONFIG_I2C_ENV_EEPROM_BUS) "; " \ - "mw.b ${addr} 0 4 && " \ - "eeprom write " __stringify(CONFIG_SYS_I2C_EEPROM_ADDR) \ - " ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && " \ - "eeprom write " __stringify(CONFIG_SYS_I2C_EEPROM_ADDR) \ - " ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0" -#endif - -#ifndef CONFIG_KM_BOARD_EXTRA_ENV -#define CONFIG_KM_BOARD_EXTRA_ENV "" -#endif - -/* - * Default environment variables - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_BOARD_EXTRA_ENV \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_NEW_ENV \ - "arch=arm\0" \ - "" - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* address for the bootcount (taken from end of RAM) */ -#define BOOTCOUNT_ADDR (CONFIG_KM_RESERVED_PRAM) - -/* enable POST tests */ -#define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS) -#define CONFIG_POST_SKIP_ENV_FLAGS -#define CONFIG_POST_EXTERNAL_WORD_FUNCS - -#endif /* _CONFIG_KM_ARM_H */ diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h deleted file mode 100644 index 01482d5..0000000 --- a/include/configs/km_kirkwood.h +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Prafulla Wadaskar <prafulla(a)marvell.com> - * - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr(a)denx.de. - * - * (C) Copyright 2011-2012 - * Holger Brunck, Keymile GmbH Hannover, holger.brunck(a)keymile.com - * Valentin Longchamp, Keymile AG, valentin.longchamp(a)keymile.com - */ - -/* - * for linking errors see - * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html - */ - -#ifndef _CONFIG_KM_KIRKWOOD_H -#define _CONFIG_KM_KIRKWOOD_H - -/* KM_KIRKWOOD */ -#if defined(CONFIG_KM_KIRKWOOD) -#define CONFIG_HOSTNAME "km_kirkwood" - -/* KM_KIRKWOOD_PCI */ -#elif defined(CONFIG_KM_KIRKWOOD_PCI) -#define CONFIG_HOSTNAME "km_kirkwood_pci" -#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" -#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE - -/* KM_KIRKWOOD_128M16 */ -#elif defined(CONFIG_KM_KIRKWOOD_128M16) -#define CONFIG_HOSTNAME "km_kirkwood_128m16" - -/* KM_NUSA */ -#elif defined(CONFIG_KM_NUSA) - -#define CONFIG_HOSTNAME "kmnusa" - -/* KMCOGE5UN */ -#elif defined(CONFIG_KM_COGE5UN) -#define CONFIG_HOSTNAME "kmcoge5un" - -/* KM_SUSE2 */ -#elif defined(CONFIG_KM_SUSE2) -#define CONFIG_HOSTNAME "kmsuse2" -#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" -#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE -#else -#error ("Board unsupported") -#endif - -/* include common defines/options for all arm based Keymile boards */ -#include "km/km_arm.h" - -#if defined(CONFIG_KM_PIGGY4_88E6352) -/* - * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via - * an Marvell 88E6352 simple switch. - * In this case we have to change the default settings for the etherent mac. - * There is NO ethernet phy. The ARM and Switch are conencted directly over - * RGMII in MAC-MAC mode - * In this case 1GBit full duplex and autoneg off - */ -#define PORT_SERIAL_CONTROL_VALUE ( \ - MVGBE_FORCE_LINK_PASS | \ - MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ - MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ - MVGBE_ADV_NO_FLOW_CTRL | \ - MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - MVGBE_FORCE_BP_MODE_NO_JAM | \ - (1 << 9) /* Reserved bit has to be 1 */ | \ - MVGBE_DO_NOT_FORCE_LINK_FAIL | \ - MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ - MVGBE_DTE_ADV_0 | \ - MVGBE_MIIPHY_MAC_MODE | \ - MVGBE_AUTO_NEG_NO_CHANGE | \ - MVGBE_MAX_RX_PACKET_1552BYTE | \ - MVGBE_CLR_EXT_LOOPBACK | \ - MVGBE_SET_FULL_DUPLEX_MODE | \ - MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ - MVGBE_SET_GMII_SPEED_TO_1000 |\ - MVGBE_SET_MII_SPEED_TO_100) - -#endif - -#ifdef CONFIG_KM_PIGGY4_88E6061 -/* - * Some keymile boards like mgcoge5un have their PIGGY4 connected via - * an Marvell 88E6061 simple switch. - * In this case we have to change the default settings for the - * ethernet phy connected to the kirkwood. - * In this case 100MB full duplex and autoneg off - */ -#define PORT_SERIAL_CONTROL_VALUE ( \ - MVGBE_FORCE_LINK_PASS | \ - MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ - MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ - MVGBE_ADV_NO_FLOW_CTRL | \ - MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - MVGBE_FORCE_BP_MODE_NO_JAM | \ - (1 << 9) /* Reserved bit has to be 1 */ | \ - MVGBE_DO_NOT_FORCE_LINK_FAIL | \ - MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ - MVGBE_DTE_ADV_0 | \ - MVGBE_MIIPHY_MAC_MODE | \ - MVGBE_AUTO_NEG_NO_CHANGE | \ - MVGBE_MAX_RX_PACKET_1552BYTE | \ - MVGBE_CLR_EXT_LOOPBACK | \ - MVGBE_SET_FULL_DUPLEX_MODE | \ - MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ - MVGBE_SET_GMII_SPEED_TO_10_100 |\ - MVGBE_SET_MII_SPEED_TO_100) -#endif - -#endif /* _CONFIG_KM_KIRKWOOD */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 4f628e0..648b91e 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -238,7 +238,6 @@ CONFIG_IRAM_BASE CONFIG_IRAM_END CONFIG_IRAM_SIZE CONFIG_IRAM_TOP -CONFIG_KM_BOARD_EXTRA_ENV CONFIG_KM_DEF_ARCH CONFIG_KM_DEF_BOOT_ARGS_CPU CONFIG_KM_DEF_ENV -- 1.8.3.1

2 2

[PATCH v4] imx: support i.MX8QM DMSSE20 a1 board
by Oliver Graute 06 Oct '22

06 Oct '22

Add i.MX8QM DMSSE20 a1 board support U-Boot 2022.07-00033-g2a5cf8e9e7 (Jul 12 2022 - 11:29:05 +0200) Model: Advantech iMX8QM DMSSE20 Board: DMS-SE20A1 8GB Build: SCFW 549b1e18, SECO-FW c9de51c0, ATF 5782363 Boot: USB DRAM: 8 GiB Core: 100 devices, 19 uclasses, devicetree: separate MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... OK In: serial@5a060000 Out: serial@5a060000 Err: serial@5a060000 Net: eth0: ethernet@5b040000 Warning: ethernet@5b050000 (eth1) using random MAC address - aa:a2:be:5b:81:4a , eth1: ethernet@5b050000 Hit any key to stop autoboot: 0 Signed-off-by: Oliver Graute <oliver.graute(a)kococonnector.com> --- Changes for v4 -update atf fw version -update seco fw version -update scfw version -move CONFIG_IMX_SMMU to imx8qm_dmsse20a1_defconfig -move CONFIG_LOADADDR to imx8qm_dmsse20a1_defconfig -move CONFIG_SYS_LOAD_ADDR to imx8qm_dmsse20a1_defconfig -move CONFIG_SYS_MALLOC_LEN to imx8qm_dmsse20a1_defconfig -move CONFIG_SYS_MMC_IMG_LOAD_PART to imx8qm_dmsse20a1_defconfig -move CONFIG_FSL_USDHC to imx8qm_dmsse20a1_defconfig -replaced CONFIG_SPL_MMC_SUPPORT with CONFIG_SPL_MMC -replaced CONFIG_SPL_SERIAL_SUPPORT with CONFIG_SPL_SERIAL -drop CONFIG_FEC_XCV_TYPE Changes for v3 -Remove addr parameter from reset_cpu() -moved some configs into defconfig Changes for v2 -replaced bd_t with struct bd_info -added missing DTS in MAINTAINERS -replaced README with imx8qm-dmsse20-a1.rst -move CMD_FUSE to Kconfig -removed fdt_high -added i2c support -added rtc support arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8qm-dmsse20-a1.dts | 407 ++++++++++++++++++ arch/arm/mach-imx/imx8/Kconfig | 7 + board/advantech/imx8qm_dmsse20_a1/Kconfig | 17 + board/advantech/imx8qm_dmsse20_a1/MAINTAINERS | 7 + board/advantech/imx8qm_dmsse20_a1/Makefile | 8 + .../imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c | 188 ++++++++ .../advantech/imx8qm_dmsse20_a1/imximage.cfg | 21 + board/advantech/imx8qm_dmsse20_a1/spl.c | 224 ++++++++++ common/Kconfig | 2 +- configs/imx8qm_dmsse20a1_defconfig | 105 +++++ doc/board/advantech/imx8qm-dmsse20-a1.rst | 59 +++ doc/board/advantech/index.rst | 1 + include/configs/imx8qm_dmsse20.h | 164 +++++++ 14 files changed, 1210 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx8qm-dmsse20-a1.dts create mode 100644 board/advantech/imx8qm_dmsse20_a1/Kconfig create mode 100644 board/advantech/imx8qm_dmsse20_a1/MAINTAINERS create mode 100644 board/advantech/imx8qm_dmsse20_a1/Makefile create mode 100644 board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c create mode 100644 board/advantech/imx8qm_dmsse20_a1/imximage.cfg create mode 100644 board/advantech/imx8qm_dmsse20_a1/spl.c create mode 100644 configs/imx8qm_dmsse20a1_defconfig create mode 100644 doc/board/advantech/imx8qm-dmsse20-a1.rst create mode 100644 include/configs/imx8qm_dmsse20.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a7e0d9f6c0..50bc76289f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -920,6 +920,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qm-apalis.dtb \ fsl-imx8qm-mek.dtb \ imx8qm-cgtqmx8.dtb \ + imx8qm-dmsse20-a1.dtb \ imx8qm-rom7720-a1.dtb \ fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ diff --git a/arch/arm/dts/imx8qm-dmsse20-a1.dts b/arch/arm/dts/imx8qm-dmsse20-a1.dts new file mode 100644 index 0000000000..81ef7fb2ce --- /dev/null +++ b/arch/arm/dts/imx8qm-dmsse20-a1.dts @@ -0,0 +1,407 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017 NXP + */ + +/dts-v1/; + +/* First 128KB is for PSCI ATF. */ +/memreserve/ 0x80000000 0x00020000; + +#include "fsl-imx8qm.dtsi" + +/ { + model = "Advantech iMX8QM DMSSE20"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + aliases { + mmc0 = &usdhc1; + mmc2 = &usdhc3; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + busfreq { + status = "disabled"; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx8qm-mek { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + SC_P_ENET1_MDC_CONN_ENET1_MDC 0x06000020 + SC_P_ENET1_MDIO_CONN_ENET1_MDIO 0x06000020 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c + SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + SC_P_GPT1_CLK_DMA_I2C2_SCL 0xc600004c + SC_P_GPT1_CAPTURE_DMA_I2C2_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_rtc_mc_8803: rtc_mc_8803_grp{ + fsl,pins = < + SC_P_SIM0_POWER_EN_DMA_I2C3_SDA 0xc600004c + SC_P_SIM0_PD_DMA_I2C3_SCL 0xc600004c + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000020 + SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08 0x00000020 + >; + }; + + pinctrl_usdhc3_gpio: usdhc3grpgpio { + fsl,pins = < + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + >; + }; + }; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&reg_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default","state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + no-1-8-v; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <&ethphy0>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-id"; + phy-handle = <&ethphy1>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; + fsl,mii-exclusive; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; +}; + +&i2c2 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc_mc_8803>; + status = "okay"; + + rv8803@32 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; + + 24c02@50 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,24c04"; + reg = <0x50>; + }; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 5e1b20a422..bcb60b1e90 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -84,6 +84,12 @@ config TARGET_IMX8QM_ROM7720_A1 select SUPPORT_SPL select IMX8QM +config TARGET_IMX8QM_DMSSE20_A1 + bool "Support i.MX8QM DMS-SE20-A1 board" + select BOARD_LATE_INIT + select SUPPORT_SPL + select IMX8QM + config TARGET_IMX8QXP_MEK bool "Support i.MX8QXP MEK board" select BOARD_LATE_INIT @@ -97,6 +103,7 @@ endchoice source "board/freescale/imx8qm_mek/Kconfig" source "board/freescale/imx8qxp_mek/Kconfig" source "board/congatec/cgtqmx8/Kconfig" +source "board/advantech/imx8qm_dmsse20_a1/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" source "board/toradex/apalis-imx8/Kconfig" source "board/toradex/colibri-imx8x/Kconfig" diff --git a/board/advantech/imx8qm_dmsse20_a1/Kconfig b/board/advantech/imx8qm_dmsse20_a1/Kconfig new file mode 100644 index 0000000000..f491462ea0 --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/Kconfig @@ -0,0 +1,17 @@ +if TARGET_IMX8QM_DMSSE20_A1 + +config SYS_BOARD + default "imx8qm_dmsse20_a1" + +config SYS_VENDOR + default "advantech" + +config SYS_CONFIG_NAME + default "imx8qm_dmsse20" + +config IMX_CONFIG + default "board/advantech/imx8qm_dmsse20_a1/imximage.cfg" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS b/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS new file mode 100644 index 0000000000..8292c6ba71 --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS @@ -0,0 +1,7 @@ +i.MX8QM ROM DMSSE20 a1 BOARD +M: Oliver Graute <oliver.graute(a)kococonnector.com> +S: Maintained +F: board/advantech/imx8qm_dmsse20_a1/ +F: arch/arm/dts/imx8qm-dmsse20-a1.dtb +F: include/configs/imx8qm_dmsse20.h +F: configs/imx8qm_dmsse20a1_defconfig diff --git a/board/advantech/imx8qm_dmsse20_a1/Makefile b/board/advantech/imx8qm_dmsse20_a1/Makefile new file mode 100644 index 0000000000..262ffcd683 --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qm_dmsse20_a1.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c new file mode 100644 index 0000000000..c3bc26f80d --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + * Copyright (C) 2020 Oliver Graute <oliver.graute(a)kococonnector.com> + */ + +#include <common.h> +#include <errno.h> +#include <linux/libfdt.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> +#include <asm/arch/sys_proto.h> +/* #include <power-domain.h> */ + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + sc_pm_clock_rate_t rate = SC_80MHZ; + int ret; + + /* Set UART0 clock root to 80 MHz */ + ret = sc_pm_setup_uart(SC_R_UART_0, rate); + if (ret) + return ret; + + setup_iomux_uart(); + + /* This is needed to because Kernel do not Power Up DC_0 */ + sc_pm_set_resource_power_mode(-1, SC_R_DC_0, SC_PM_PW_MODE_ON); + sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON); + + return 0; +} + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include <miiphy.h> + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_GPIO + +#define LVDS_ENABLE IMX_GPIO_NR(1, 6) +#define MIPI_ENABLE IMX_GPIO_NR(1, 7) + +#define BB_GPIO_3V3_1 IMX_GPIO_NR(4, 20) +#define BB_GPIO_3V3_2 IMX_GPIO_NR(4, 24) +#define BB_GPIO_3V3_3 IMX_GPIO_NR(4, 23) + +static void board_gpio_init(void) +{ + /* Enable BB 3V3 */ + gpio_request(BB_GPIO_3V3_1, "bb_3v3_1"); + gpio_direction_output(BB_GPIO_3V3_1, 1); + gpio_request(BB_GPIO_3V3_2, "bb_3v3_2"); + gpio_direction_output(BB_GPIO_3V3_2, 1); + gpio_request(BB_GPIO_3V3_3, "bb_3v3_3"); + gpio_direction_output(BB_GPIO_3V3_3, 1); + + /* enable LVDS SAS boards */ + gpio_request(LVDS_ENABLE, "lvds_enable"); + gpio_direction_output(LVDS_ENABLE, 1); + + /* enable MIPI SAS boards */ + gpio_request(MIPI_ENABLE, "mipi_enable"); + gpio_direction_output(MIPI_ENABLE, 1); +} +#endif + +int checkboard(void) +{ + puts("Board: DMS-SE20A1 8GB\n"); + build_info(); + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + +#ifdef CONFIG_MXC_GPIO + board_gpio_init(); +#endif + + return 0; +} + +void board_quiesce_devices(void) +{ + if (IS_ENABLED(CONFIG_XEN)) { + /* Clear magic number to let xen know uboot is over */ + writel(0x0, (void __iomem *)0x80000000); + return; + } +} + +void detail_board_ddr_info(void) +{ + puts("\nDDR "); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(void) +{ + puts("SCI reboot request"); + + while (1) + putc('.'); +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + /* Use EMMC */ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + + return devno; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + /* Use EMMC */ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + + return dev_no; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "DMS-SE20A1"); + env_set("board_rev", "iMX8QM"); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + + return 0; +} diff --git a/board/advantech/imx8qm_dmsse20_a1/imximage.cfg b/board/advantech/imx8qm_dmsse20_a1/imximage.cfg new file mode 100644 index 0000000000..e324c7ca37 --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/imximage.cfg @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8QM */ +SOC_TYPE IMX8QM +/* Append seco container image */ +APPEND mx8qm-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qm-val-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 bl31.bin 0x80000000 +/* Add U-Boot image with load attribute */ +DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/board/advantech/imx8qm_dmsse20_a1/spl.c b/board/advantech/imx8qm_dmsse20_a1/spl.c new file mode 100644 index 0000000000..06bb049c3a --- /dev/null +++ b/board/advantech/imx8qm_dmsse20_a1/spl.c @@ -0,0 +1,224 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + */ +#include <common.h> +#include <dm.h> +#include <spl.h> +#include <fsl_esdhc.h> + +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/sci/sci.h> +#include <asm/arch/imx8-pins.h> +#include <asm/arch/iomux.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) +#ifdef CONFIG_FSL_ESDHC_IMX + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22) +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12) + +static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC3_BASE_ADDR, 0, 4}, +}; + +static iomux_cfg_t emmc0[] = { + SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +static iomux_cfg_t usdhc2_sd[] = { + SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL), + SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_WP | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), + SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL), +}; + +void init_clk_usdhc(u32 index); +int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg); +int arch_cpu_init(void); +int board_early_init_f(void); +int timer_init(void); +void board_init_r(gd_t *id, ulong dest_addr); + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + * mmc2 USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + + imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0)); + init_clk_usdhc(0); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return ret; + + imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd)); + init_clk_usdhc(2); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gpio_request(USDHC2_CD_GPIO, "sd2_cd"); + gpio_direction_input(USDHC2_CD_GPIO); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + } + + return ret; +} + +#endif /* CONFIG_FSL_ESDHC_IMX */ + +void spl_board_init(void) +{ +#if defined(CONFIG_SPL_SPI_SUPPORT) + if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) { + if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) + puts("Warning: failed to initialize FSPI0\n"); + } +#endif + + puts("Normal Boot\n"); +} + +void spl_board_prepare_for_boot(void) +{ +#if defined(CONFIG_SPL_SPI_SUPPORT) + if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) { + if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) + puts("Warning: failed to turn off FSPI0\n"); + } +#endif +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} diff --git a/common/Kconfig b/common/Kconfig index a96842a5c1..894733a26e 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -528,7 +528,7 @@ config BOARD_TYPES config DISPLAY_CPUINFO bool "Display information about the CPU during start up" - default y if ARC|| ARM || NIOS2 || X86 || XTENSA || M68K + default y if ARC || ARM || NIOS2 || X86 || XTENSA || M68K help Display information about the CPU that U-Boot is running on when U-Boot starts up. The function print_cpuinfo() is called diff --git a/configs/imx8qm_dmsse20a1_defconfig b/configs/imx8qm_dmsse20a1_defconfig new file mode 100644 index 0000000000..569401cf56 --- /dev/null +++ b/configs/imx8qm_dmsse20a1_defconfig @@ -0,0 +1,105 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_LEN=0x2800000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_SYS_MMC_IMG_LOAD_PART=0 +CONFIG_TARGET_IMX8QM_DMSSE20_A1=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_ENV_OFFSET=0x80000 +CONFIG_SPL=y +CONFIG_SYS_LOAD_ADDR=0x80280000 +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_CONTROL=y +CONFIG_CI_UDC=y +CONFIG_DM_PCA953X=y +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_IMX_BOOTAUX=y +CONFIG_FS_FAT=y +CONFIG_FS_EXT4=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_BROKEN_CD=y +CONFIG_CMD_SF=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FUSE=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8qm-dmsse20-a1" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +# CONFIG_EFI_LOADER is not set +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_FEC1_ENET_DEV=0 +CONFIG_ETHPRIME="eth0" +CONFIG_FEC1_MXC_PHYADDR=0x4 +CONFIG_FEC2_ENET_DEV=1 +CONFIG_ETHPRIME1="eth1" +CONFIG_FEC2_MXC_PHYADDR=0x4 +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_IMX_SMMU=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_MISC=y +CONFIG_SMC_FUSE=y +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_TINY_MEMSET=y +CONFIG_AHAB_BOOT=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_DM_RTC=y +CONFIG_RTC_RV8803=y +CONFIG_CMD_DATE=y +# CONFIG_CMD_DEKBLOB is not set diff --git a/doc/board/advantech/imx8qm-dmsse20-a1.rst b/doc/board/advantech/imx8qm-dmsse20-a1.rst new file mode 100644 index 0000000000..bb116fa374 --- /dev/null +++ b/doc/board/advantech/imx8qm-dmsse20-a1.rst @@ -0,0 +1,59 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +NXP i.MX8QM DMSSE20-a1 board +============================ + +Quick Start +----------- + +- Build the ARM Trusted firmware binary +- Get scfw_tcm.bin and ahab-container.img +- Get imx-mkimage +- Build U-Boot +- Flash the binary into the SD card +- Boot + +Get and Build the ARM Trusted Firmware +-------------------------------------- + +.. code-block:: bash + + $ git clone https://source.codeaurora.org/external/imx/imx-atf + $ cd imx-atf/ + $ git checkout lf-5.10.72-2.2.0 -b lf-5.10.72-2.2.0 + $ make PLAT=imx8qm bl31 + $ cp build/imx8qm/release/bl31.bin $(builddir) + +Get scfw_tcm.bin and ahab-container.img +--------------------------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.11.0.bin + $ chmod +x imx-sc-firmware-1.11.0.bin + $ ./imx-sc-firmware-1.11.0.bin + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-3.8.5.bin + $ chmod +x imx-seco-3.8.5.bin + $ ./imx-seco-3.8.5.bin + +Or use this to avoid running random scripts from the internet, +but note that you must agree to the license the script displays: + +.. code-block:: bash + + $ dd if=imx-sc-firmware-1.11.0.bin of=imx-sc-firmware-1.11.0.tar.bz2 bs=42757 skip=1 + $ tar -xf imx-sc-firmware-1.11.0.tar.bz2 + $ cp imx-sc-firmware-1.11.0/mx8qm-val-scfw-tcm.bin $(builddir) + $ dd if=imx-seco-3.8.5.bin of=imx-seco-3.8.5.tar.bz2 bs=43978 skip=1 + $ tar -xf imx-seco-3.8.5.tar.bz2 + $ cp imx-seco-3.8.5/firmware/seco/mx8qmb0-ahab-container.img $(builddir) + +Build U-Boot +------------ +.. code-block:: bash + + $ export ATF_LOAD_ADDR=0x80000000 + $ export BL33_LOAD_ADDR=0x80020000 + $ make imx8qm_dmsse20a1_defconfig + $ make u-boot.bin + $ make flash.bin diff --git a/doc/board/advantech/index.rst b/doc/board/advantech/index.rst index e9b198c5c3..125b98c1f7 100644 --- a/doc/board/advantech/index.rst +++ b/doc/board/advantech/index.rst @@ -7,3 +7,4 @@ Advantech :maxdepth: 2 imx8qm-rom7720-a1.rst + imx8qm-dmsse20-a1.rst diff --git a/include/configs/imx8qm_dmsse20.h b/include/configs/imx8qm_dmsse20.h new file mode 100644 index 0000000000..3050f79fa7 --- /dev/null +++ b/include/configs/imx8qm_dmsse20.h @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017-2019 NXP + */ + +#ifndef __IMX8QM_DMSSE20_H +#define __IMX8QM_DMSSE20_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> +#define CONFIG_REMAKE_ELF + +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ + +#define CONFIG_NR_DRAM_BANKS 4 + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_BOOTM_NETBSD + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define USDHC3_BASE_ADDR 0x5B030000 + +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE /* Support for 1000BASE-X */ + +#define IMX_FEC_BASE 0x5B040000 +/* FEC1 */ +#define IMX_FEC1_BASE 0x5B040000 +/* FEC2 */ +#define IMX_FEC2_BASE 0x5B050000 + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0\0" \ + "earlycon=lpuart32,0x5a060000\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "fdt_file=imx8qm-dmsse20-a1.dtb\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp mac=${ethaddr} nfsroot=${serverip}:${nfsroot},v3,tcp rw\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +/* Default environment is in SD */ + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#else +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#endif + +#define CONFIG_SYS_MMC_ENV_DEV 2 /* USDHC3 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_SYS_SDRAM_BASE 0x080000000 +#define PHYS_SDRAM_1 0x080000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x080000000 /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x180000000 /* 6 GB */ + +#define CONFIG_SYS_MEMTEST_START 0xA0000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2)) + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +/* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */ +#ifdef CONFIG_FSL_FSPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define FSL_FSPI_FLASH_SIZE SZ_64M +#define FSL_FSPI_FLASH_NUM 1 +#define FSPI0_BASE_ADDR 0x5d120000 +#define FSPI0_AMBA_BASE 0 +#define CONFIG_SYS_FSL_FSPI_AHB +#endif + +/* #define CONFIG_OF_SYSTEM_SETUP */ + +#endif /* __IMX8QM_DMSSE20_H */ -- 2.17.1

3 3

[PATCH v1 0/4] phy: Add generic_{setup,shutdown}_phy() helpers
by Patrice Chotard 05 Oct '22

05 Oct '22

In drivers ehci-generic.c and ohci-generic.c, specific phy helpers has been added and shared 95% of common code. Factorize this code in generic_{setup,shutdown}_phy() helpers and update all consumers. Patrice Chotard (4): phy: Add generic_{setup,shutdown}_phy() helpers usb: ohci: Make usage of generic_{setup,shutdown}_phy() helpers usb: ehci: Make usage of generic_{setup,shutdown}_phy() helpers usb: ehci: Remove unused ehci_{setup,shutdown}_phy() helpers drivers/phy/phy-uclass.c | 42 +++++++++++++++++++++ drivers/usb/host/ehci-generic.c | 6 +-- drivers/usb/host/ehci-hcd.c | 66 --------------------------------- drivers/usb/host/ehci-msm.c | 4 +- drivers/usb/host/ehci-mx6.c | 6 +-- drivers/usb/host/ehci-pci.c | 4 +- drivers/usb/host/ehci.h | 4 -- drivers/usb/host/ohci-generic.c | 56 ++-------------------------- include/generic-phy.h | 30 +++++++++++++++ 9 files changed, 85 insertions(+), 133 deletions(-) -- 2.25.1

3 7

[PATCH] xilinx: zynqmp: Load pmufw configuration before checking access
by Michal Simek 05 Oct '22

05 Oct '22

Before this patch you could see in the log: U-Boot SPL 2022.10-rc5 (Sep 29 2022 - 15:29:27 +0200) PMUFW: v1.1 Loading new PMUFW cfg obj (32 bytes) PMUFW: No permission to change config object Loading new PMUFW cfg obj (2032 bytes) where it is visible that permission is check before sending PMUFW configuration (big size). When this patch is applied it is visible that order is correct. U-Boot SPL 2022.10-rc5 (Sep 29 2022 - 15:47:08 +0200) Loading new PMUFW cfg obj (2032 bytes) PMUFW: v1.1 Loading new PMUFW cfg obj (32 bytes) Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- board/xilinx/zynqmp/zynqmp.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 0b30dd048eb5..f1eb4ff38908 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -227,6 +227,14 @@ int board_init(void) char name[SOC_MAX_STR_SIZE]; int ret; #endif + + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + /* Check *at build time* if the filename is an non-empty string */ + if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1) + zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj, + zynqmp_pm_cfg_obj_size); + } + #if defined(CONFIG_ZYNQMP_FIRMWARE) struct udevice *dev; @@ -236,10 +244,6 @@ int board_init(void) #endif #if defined(CONFIG_SPL_BUILD) - /* Check *at build time* if the filename is an non-empty string */ - if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1) - zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj, - zynqmp_pm_cfg_obj_size); printf("Silicon version:\t%d\n", zynqmp_get_silicon_version()); /* the CSU disables the JTAG interface when secure boot is enabled */ -- 2.36.1

2 2

[PATCH 00/10] bootstage: Migrate from timer_get_boot_us() to timer_get_us()
by Stefan Roese 05 Oct '22

05 Oct '22

While working on the bootstage support for Armada XP (orion-timer) I noticed, that we currently have two API's supporting early timer functionality. These are: a) timer_early_get_rate() & timer_early_get_count() which integrates into the "normal" timer functions like timer_get() & timer_get_us() in the early boot phase, if CONFIG_TIMER_EARLY is enabled b) timer_get_boot_us(), which was introduced with bootstage IIUTC IMHO it makes more sense to not introduce a new API for this early timer functionality but re-use the "normal" API instead. This patchset migrates the timer_get_boot_us() implementations to the timer_early functions. This is done by: - Implementing the timer_early functions in the drivers currently supporting timer_get_boot_us() - Migrating bootcount to using timer_get_us() instead of timer_get_boot_us() - Completely removing timer_get_boot_us() With some minor tweaks in board_r/f for the dm_timer_init() and timer_init() call. I've tested this on Armada XP and sandbox. Thanks, Stefan Stefan Roese (10): arm: arch_timer: Add timer_early functions arm: imx: syscounter: Add timer_early functions arm: armv8: generic_timer: Add timer_early functions timer: cadence-ttc: Add timer_early functions timer: omap-timer: Add timer_early functions timer: rockchip_timer: Add timer_early functions board_f/r: Allow selection of CONFIG_TIMER_EARLY w/o CONFIG_TIMER board_f/r: Don't call timer_init() when TIMER is enabled bootstage: Migrate from timer_get_boot_us() to timer_get_us() bootstage/timer: Treewide remove timer_get_boot_us() arch/arm/cpu/armv7/arch_timer.c | 15 ++++++++--- arch/arm/cpu/armv8/generic_timer.c | 9 ++++--- arch/arm/mach-imx/syscounter.c | 12 +++++++-- arch/sandbox/cpu/cpu.c | 11 -------- boot/Kconfig | 1 + common/board_f.c | 4 +-- common/board_r.c | 5 ++-- common/bootstage.c | 26 +++++++++--------- drivers/timer/Kconfig | 1 - drivers/timer/cadence-ttc.c | 9 ++++--- drivers/timer/omap-timer.c | 9 ++++--- drivers/timer/orion-timer.c | 8 ------ drivers/timer/rockchip_timer.c | 42 ++++++++++++++++-------------- drivers/timer/tsc_timer.c | 5 ---- include/bootstage.h | 17 ++++-------- lib/time.c | 20 -------------- 16 files changed, 87 insertions(+), 107 deletions(-) -- 2.37.3

5 32

[PATCH v2 1/3] net: emaclite: fix broken build
by samuel.obuch＠codasip.com 05 Oct '22

05 Oct '22

From: Samuel Obuch <samuel.obuch(a)codasip.com> Function ioremap_nocache seems to be defined only for mips and microblaze architectures. Therefore, the function call in the emaclite driver causes this driver to be unusable with other architectures, for example riscv. v2: Use ioremap function instead of ioremap_nocache. Switch to linux/io.h which automatically creates ioremap if not defined by the architecture. Signed-off-by: Samuel Obuch <samuel.obuch(a)codasip.com> --- drivers/net/xilinx_emaclite.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 6c9f1f7c27..2e152bf873 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -20,8 +20,8 @@ #include <fdtdec.h> #include <linux/delay.h> #include <linux/errno.h> +#include <linux/io.h> #include <linux/kernel.h> -#include <asm/io.h> #include <eth_phy.h> DECLARE_GLOBAL_DATA_PTR; @@ -615,8 +615,8 @@ static int emaclite_of_to_plat(struct udevice *dev) int offset = 0; pdata->iobase = dev_read_addr(dev); - emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase, - 0x10000); + emaclite->regs = (struct emaclite_regs *)ioremap(pdata->iobase, + 0x10000); emaclite->phyaddr = -1; -- 2.31.1

3 5

net: emaclite: Fixes, enable driver for other archs
by Samuel Obuch 05 Oct '22

05 Oct '22

These patches solve a few issues with the driver observed on a RISC-V platform.

5 19

[PATCH v3 0/6] arm: mvebu: Support for 98DX25xx/98DX35xx (AlleyCat5)
by Chris Packham 05 Oct '22

05 Oct '22

These patches are based on Marvell's bootloader for the AlleyCat5/5X which was based on u-boot 2018.03. I've split that code into consumable chunks and dropped as much unnecessary stuff as I can. I've also tried to sync the device trees as much as possible with the support that will land in Linux 6.0 although there are still some differences Changes in v3: - Remove unnecessary changes to RX descriptor handling - Use dev_get_dma_range() to parse dma-ranges property from parent device. - None. Note some changes related to this have been requested and will be looked into I just wanted to get v3 out so the other changes could be reviewed. - Remove unnecessary dma-ranges property from ethernet nodes (mvneta now correctly parses the property from the parent node). - Keep soc_print_clock_info and soc_print_device_info local to alleycat5. - Remove MMC and UBIFS distroboot options (MMC driver is not currently functional, NAND is not populated on the RD-AC5X board) - Remove unnecessary Ethernet configuration - Remove unnecessary NAND configuration - Remove memory node from dts so the value passed by the DDR FW will be used Changes in v2: - Use distro boot by default - remove unnecessary SPI-NOR partitions Chris Packham (6): net: mvneta: Add support for AlleyCat5 usb: ehci: ehci-marvell: Support for marvell,ac5-ehci pinctrl: mvebu: Add AlleyCat5 support misc: mvebu: Add sample at reset driver arm: mvebu: Support for 98DX25xx/98DX35xx SoC arm: mvebu: Add RD-AC5X board arch/arm/dts/Makefile | 3 +- arch/arm/dts/ac5-98dx25xx.dtsi | 290 +++++++++++++++++++++ arch/arm/dts/ac5-98dx35xx-rd.dts | 135 ++++++++++ arch/arm/dts/ac5-98dx35xx.dtsi | 17 ++ arch/arm/mach-mvebu/Kconfig | 13 +- arch/arm/mach-mvebu/Makefile | 1 + arch/arm/mach-mvebu/alleycat5/Makefile | 9 + arch/arm/mach-mvebu/alleycat5/clock.c | 49 ++++ arch/arm/mach-mvebu/alleycat5/clock.h | 11 + arch/arm/mach-mvebu/alleycat5/cpu.c | 129 +++++++++ arch/arm/mach-mvebu/alleycat5/soc.c | 229 ++++++++++++++++ arch/arm/mach-mvebu/alleycat5/soc.h | 6 + arch/arm/mach-mvebu/arm64-common.c | 5 + arch/arm/mach-mvebu/include/mach/cpu.h | 4 + board/Marvell/mvebu_alleycat-5/MAINTAINERS | 6 + board/Marvell/mvebu_alleycat-5/Makefile | 3 + board/Marvell/mvebu_alleycat-5/board.c | 35 +++ configs/mvebu_ac5_rd_defconfig | 88 +++++++ drivers/misc/Kconfig | 6 + drivers/misc/Makefile | 1 + drivers/misc/mvebu_sar/Makefile | 4 + drivers/misc/mvebu_sar/ac5_sar.c | 119 +++++++++ drivers/misc/mvebu_sar/sar-uclass.c | 146 +++++++++++ drivers/net/Kconfig | 2 +- drivers/net/mvneta.c | 43 ++- drivers/pinctrl/mvebu/Kconfig | 2 +- drivers/usb/host/Kconfig | 1 + drivers/usb/host/ehci-marvell.c | 57 +++- include/configs/mvebu_alleycat-5.h | 57 ++++ include/dm/uclass-id.h | 1 + include/fdtdec.h | 4 + include/mvebu/mvebu_chip_sar.h | 73 ++++++ include/mvebu/sar.h | 57 ++++ include/mvebu/var.h | 28 ++ include/sar-uclass.h | 23 ++ lib/fdtdec.c | 6 +- 36 files changed, 1647 insertions(+), 16 deletions(-) create mode 100644 arch/arm/dts/ac5-98dx25xx.dtsi create mode 100644 arch/arm/dts/ac5-98dx35xx-rd.dts create mode 100644 arch/arm/dts/ac5-98dx35xx.dtsi create mode 100644 arch/arm/mach-mvebu/alleycat5/Makefile create mode 100644 arch/arm/mach-mvebu/alleycat5/clock.c create mode 100644 arch/arm/mach-mvebu/alleycat5/clock.h create mode 100644 arch/arm/mach-mvebu/alleycat5/cpu.c create mode 100644 arch/arm/mach-mvebu/alleycat5/soc.c create mode 100644 arch/arm/mach-mvebu/alleycat5/soc.h create mode 100644 board/Marvell/mvebu_alleycat-5/MAINTAINERS create mode 100644 board/Marvell/mvebu_alleycat-5/Makefile create mode 100644 board/Marvell/mvebu_alleycat-5/board.c create mode 100644 configs/mvebu_ac5_rd_defconfig create mode 100644 drivers/misc/mvebu_sar/Makefile create mode 100644 drivers/misc/mvebu_sar/ac5_sar.c create mode 100644 drivers/misc/mvebu_sar/sar-uclass.c create mode 100644 include/configs/mvebu_alleycat-5.h create mode 100644 include/mvebu/mvebu_chip_sar.h create mode 100644 include/mvebu/sar.h create mode 100644 include/mvebu/var.h create mode 100644 include/sar-uclass.h -- 2.37.3

4 18