September 2022 - U-Boot

[PATCH v1 0/2] Add support for Nuvoton NPCM845 BMC
by Jim Liu 07 Oct '22

07 Oct '22

The Nuvoton Arbel NPCM8XX SoC is a fourth-generation BMC. The NPCM8XX computing subsystem comprises a quadcore ARM Cortex A35 ARM-V8 architecture. Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX. This patchset was tested on the Arbel NPCM8XX evaluation board. And DTS is base on linux upstream Jim Liu (2): arm: nuvoton: Add support for Nuvoton NPCM845 BMC clk: nuvoton: Add support for NPCM845 arch/arm/dts/Makefile | 1 + arch/arm/dts/nuvoton-common-npcm8xx.dtsi | 170 ++++++++++++++++++ arch/arm/dts/nuvoton-npcm845-evb.dts | 30 ++++ arch/arm/dts/nuvoton-npcm845.dtsi | 77 ++++++++ arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi | 136 ++++++++++++++ arch/arm/include/asm/arch-npcm8xx/gcr.h | 140 +++++++++++++++ arch/arm/include/asm/arch-npcm8xx/rst.h | 26 +++ arch/arm/mach-npcm/Kconfig | 8 + arch/arm/mach-npcm/Makefile | 1 + arch/arm/mach-npcm/npcm8xx/Kconfig | 18 ++ arch/arm/mach-npcm/npcm8xx/Makefile | 1 + arch/arm/mach-npcm/npcm8xx/cpu.c | 135 ++++++++++++++ arch/arm/mach-npcm/npcm8xx/reset.c | 37 ++++ board/nuvoton/arbel_evb/Kconfig | 18 ++ board/nuvoton/arbel_evb/MAINTAINERS | 7 + board/nuvoton/arbel_evb/Makefile | 1 + board/nuvoton/arbel_evb/arbel_evb.c | 29 +++ configs/arbel_evb_defconfig | 66 +++++++ drivers/clk/nuvoton/Makefile | 1 + drivers/clk/nuvoton/clk_npcm8xx.c | 98 ++++++++++ include/configs/arbel.h | 35 ++++ .../dt-bindings/clock/nuvoton,npcm845-clk.h | 52 ++++++ .../dt-bindings/reset/nuvoton,npcm8xx-reset.h | 124 +++++++++++++ 23 files changed, 1211 insertions(+) create mode 100644 arch/arm/dts/nuvoton-common-npcm8xx.dtsi create mode 100644 arch/arm/dts/nuvoton-npcm845-evb.dts create mode 100644 arch/arm/dts/nuvoton-npcm845.dtsi create mode 100644 arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi create mode 100644 arch/arm/include/asm/arch-npcm8xx/gcr.h create mode 100644 arch/arm/include/asm/arch-npcm8xx/rst.h create mode 100644 arch/arm/mach-npcm/npcm8xx/Kconfig create mode 100644 arch/arm/mach-npcm/npcm8xx/Makefile create mode 100644 arch/arm/mach-npcm/npcm8xx/cpu.c create mode 100644 arch/arm/mach-npcm/npcm8xx/reset.c create mode 100644 board/nuvoton/arbel_evb/Kconfig create mode 100644 board/nuvoton/arbel_evb/MAINTAINERS create mode 100644 board/nuvoton/arbel_evb/Makefile create mode 100644 board/nuvoton/arbel_evb/arbel_evb.c create mode 100644 configs/arbel_evb_defconfig create mode 100644 drivers/clk/nuvoton/clk_npcm8xx.c create mode 100644 include/configs/arbel.h create mode 100644 include/dt-bindings/clock/nuvoton,npcm845-clk.h create mode 100644 include/dt-bindings/reset/nuvoton,npcm8xx-reset.h -- 2.17.1

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[PATCH 0/2] Implement workaround for errata i2329
by Ravi Gunasekaran 07 Oct '22

07 Oct '22

This patch series adds the MDIO workaround for the errata i2329. On certain TI SoC's CPSW and ICSS peripherals, there is a possibility that the MDIO interface returns corrupt data on MDIO reads or writes incorrect data on MDIO writes. There is also a possibility for the MDIO interface to become unavailable until the next peripheral reset. The workaround is to configure the MDIO in manual mode and disable the MDIO state machine and emulate the MDIO protocol by reading and writing appropriate fields in MDIO_MANUAL_IF_REG register of the MDIO controller to manipulate the MDIO clock and data pins. Ravi Gunasekaran (2): net: ti: cpsw-mdio: Add workaround for errata i2329 net: ti: am65-cpsw-nuss: Enable MDIO manual mode drivers/net/ti/am65-cpsw-nuss.c | 24 ++- drivers/net/ti/cpsw.c | 3 +- drivers/net/ti/cpsw_mdio.c | 255 +++++++++++++++++++++++++++++++- drivers/net/ti/cpsw_mdio.h | 2 +- drivers/net/ti/keystone_net.c | 3 +- 5 files changed, 279 insertions(+), 8 deletions(-) -- 2.17.1

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[PATCH] dma: ti: k3-udma: Fix 'SZ_64K’ undeclared error
by Dhruva Gole 07 Oct '22

07 Oct '22

Include linux/sizes.h because it defines SZ_64K which is used in many places inside k3-udma.c This fixes the error: ‘SZ_64K’ undeclared which appears during build time Signed-off-by: Dhruva Gole <d-gole(a)ti.com> --- I came across this error while trying to build upstream u-boot for the AM62x. I needed to enable udma for xSPI boot and I got the following build errors: ../drivers/dma/ti/k3-udma.c: In function ‘udma_prep_dma_memcpy’: ../drivers/dma/ti/k3-udma.c:1849:12: error: ‘SZ_64K’ undeclared (first use in this function) 1849 | if (len < SZ_64K) { | ^~~~~~ This probably went unnoticed until now because it was being included in all the include/config/xx_evm.h files. However it being absent from upstream am62_evm.h landed me this error and I think it makes sense to actually add the include sizes.h here itself rather than rely that some other included file that is included in k3-udma will include it in itself. Thanks and Regards, Dhruva Gole drivers/dma/ti/k3-udma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c index 86603d43f14f..1a9197bfc820 100644 --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c @@ -14,6 +14,7 @@ #include <malloc.h> #include <linux/bitops.h> #include <linux/dma-mapping.h> +#include <linux/sizes.h> #include <dm.h> #include <dm/device_compat.h> #include <dm/devres.h> -- 2.25.1

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[PATCH] armv8: cache_v8: Fix pgtables setup when MMU is already enabled
by Pali Rohár 07 Oct '22

07 Oct '22

When MMU is already enabled then dcache_enable() does not call mmu_setup() and so setup_all_pgtables() is also never called. In this situation when some driver calls mmu_set_region_dcache_behaviour() function then U-Boot crashes with error message: Emergency page table not setup. Fix this issue by explicitly calling setup_all_pgtables() in dcache_enable() function near condition for mmu_setup(). This change fixes chainloading U-Boot from U-Boot on Turris Mox board which uses mvneta ethernet driver which calls mmu_set_region_dcache_behaviour(). Signed-off-by: Pali Rohár <pali(a)kernel.org> --- arch/arm/cpu/armv8/cache_v8.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index e4736e564366..2a226fd0633d 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -503,6 +503,10 @@ void dcache_enable(void) mmu_setup(); } + /* Set up page tables only once (it is done also by mmu_setup()) */ + if (!gd->arch.tlb_fillptr) + setup_all_pgtables(); + set_sctlr(get_sctlr() | CR_C); } -- 2.20.1

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[PATCH 2/2] board: developerbox: move mem_map setup later
by jassisinghbrar＠gmail.com 07 Oct '22

07 Oct '22

From: Jassi Brar <jaswinder.singh(a)linaro.org> dram_init() can't modify global/static variables, so move the mem_map setup later when bss is available. Signed-off-by: Jassi Brar <jaswinder.singh(a)linaro.org> --- board/socionext/developerbox/developerbox.c | 57 ++++++++++++--------- 1 file changed, 34 insertions(+), 23 deletions(-) diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c index b680f77d80..412c811c12 100644 --- a/board/socionext/developerbox/developerbox.c +++ b/board/socionext/developerbox/developerbox.c @@ -56,8 +56,6 @@ struct draminfo { struct draminfo_entry entry[3]; }; -struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE; - DECLARE_GLOBAL_DATA_PTR; #define LOAD_OFFSET 0x100 @@ -104,21 +102,44 @@ int ft_board_setup(void *blob, struct bd_info *bd) int dram_init(void) { + struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE; + struct draminfo_entry *ent = synquacer_draminfo->entry; + + gd->ram_size = ent[0].size; + gd->ram_base = ent[0].base; + + return 0; +} + +int dram_init_banksize(void) +{ + struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE; + struct draminfo_entry *ent = synquacer_draminfo->entry; + int i; + + for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) { + if (i < synquacer_draminfo->nr_regions) { + debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base); + gd->bd->bi_dram[i].start = ent[i].base; + gd->bd->bi_dram[i].size = ent[i].size; + } + } + + return 0; +} + +void build_mem_map(void) +{ + struct draminfo *synquacer_draminfo = (void *)SQ_DRAMINFO_BASE; struct draminfo_entry *ent = synquacer_draminfo->entry; struct mm_region *mr; int i, ri; if (synquacer_draminfo->nr_regions < 1) { log_err("Failed to get correct DRAM information\n"); - return -1; + return; } - /* - * U-Boot RAM size must be under the first DRAM region so that it doesn't - * access secure memory which is at the end of the first DRAM region. - */ - gd->ram_size = ent[0].size; - /* Update memory region maps */ for (i = 0; i < synquacer_draminfo->nr_regions; i++) { if (i >= MAX_DDR_REGIONS) @@ -134,24 +155,14 @@ int dram_init(void) mr = &mem_map[DDR_REGION_INDEX(0)]; mem_map[ri].attrs = mr->attrs; } - - return 0; } -int dram_init_banksize(void) +void enable_caches(void) { - struct draminfo_entry *ent = synquacer_draminfo->entry; - int i; - - for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) { - if (i < synquacer_draminfo->nr_regions) { - debug("%s: dram[%d] = %llx@%llx\n", __func__, i, ent[i].size, ent[i].base); - gd->bd->bi_dram[i].start = ent[i].base; - gd->bd->bi_dram[i].size = ent[i].size; - } - } + build_mem_map(); - return 0; + icache_enable(); + dcache_enable(); } int print_cpuinfo(void) -- 2.25.1

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[PATCH 1/2] board: developerbox: use identity mapping for >4GB
by jassisinghbrar＠gmail.com 07 Oct '22

07 Oct '22

From: Jassi Brar <jaswinder.singh(a)linaro.org> Identity-map the second and later memory banks which are located >4GB. Signed-off-by: Jassi Brar <jaswinder.singh(a)linaro.org> --- board/socionext/developerbox/developerbox.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c index 9552bfcdc3..b680f77d80 100644 --- a/board/socionext/developerbox/developerbox.c +++ b/board/socionext/developerbox/developerbox.c @@ -127,11 +127,11 @@ int dram_init(void) ri = DDR_REGION_INDEX(i); mem_map[ri].phys = ent[i].base; mem_map[ri].size = ent[i].size; + mem_map[ri].virt = mem_map[ri].phys; if (i == 0) continue; mr = &mem_map[DDR_REGION_INDEX(0)]; - mem_map[ri].virt = mr->virt + mr->size; mem_map[ri].attrs = mr->attrs; } -- 2.25.1

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[PATCH] power: fan53555: Fix missing newline in error message
by Michal Suchanek 07 Oct '22

07 Oct '22

Avoid concatenation with following message. Signed-off-by: Michal Suchanek <msuchanek(a)suse.de> --- drivers/power/pmic/fan53555.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/pmic/fan53555.c b/drivers/power/pmic/fan53555.c index 4d1e686d27..0d91628f57 100644 --- a/drivers/power/pmic/fan53555.c +++ b/drivers/power/pmic/fan53555.c @@ -23,7 +23,7 @@ static int pmic_fan53555_read(struct udevice *dev, uint reg, u8 *buff, int len) { if (dm_i2c_read(dev, reg, buff, len)) { - pr_err("%s: read error for register: %#x!", dev->name, reg); + pr_err("%s: read error for register: %#x!\n", dev->name, reg); return -EIO; } -- 2.37.3

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[PATCH v3 1/5] imx8m: USDHC3 base address definition for i.MX8MP
by Martyn Welch 07 Oct '22

07 Oct '22

From: Martyn Welch <martyn.welch(a)collabora.com> The i.MX8MP also has USDHC3, allow access to the relvant base address definition. Signed-off-by: Martyn Welch <martyn.welch(a)collabora.com> --- Changes in v2: - None Changes in v3: - None arch/arm/include/asm/arch-imx8m/imx-regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 6969cde26c..d8952342e0 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -46,7 +46,7 @@ #define USDHC1_BASE_ADDR 0x30B40000 #define USDHC2_BASE_ADDR 0x30B50000 #define QSPI0_AMBA_BASE 0x08000000 -#ifdef CONFIG_IMX8MM +#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MP) #define USDHC3_BASE_ADDR 0x30B60000 #endif #define UART_BASE_ADDR(n) ( \ -- 2.35.1

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[PATCH 1/2] configs: mediatek: define default variables
by Julien STEPHAN 07 Oct '22

07 Oct '22

From: Jerome Brunet <jbrunet(a)baylibre.com> define some default addresses and variables to help distro boot Signed-off-by: Jerome Brunet <jbrunet(a)baylibre.com> Signed-off-by: Alexandre Mergnat <amergnat(a)baylibre.com> Signed-off-by: Julien STEPHAN <jstephan(a)baylibre.com> --- include/configs/mt8183.h | 5 +++++ include/configs/mt8516.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/include/configs/mt8183.h b/include/configs/mt8183.h index c93d70ddf1..f2a0d71556 100644 --- a/include/configs/mt8183.h +++ b/include/configs/mt8183.h @@ -26,6 +26,11 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "scriptaddr=0x40000000\0" \ + "fdt_addr_r=0x44000000\0" \ + "fdtoverlay_addr_r=0x44c00000\0" \ + "kernel_addr_r=0x45000000\0" \ + "ramdisk_addr_r=0x46000000\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE ".dtb\0" \ BOOTENV #endif diff --git a/include/configs/mt8516.h b/include/configs/mt8516.h index 7228f3e428..a9041aed46 100644 --- a/include/configs/mt8516.h +++ b/include/configs/mt8516.h @@ -26,6 +26,11 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "scriptaddr=0x40000000\0" \ + "fdt_addr_r=0x44000000\0" \ + "fdtoverlay_addr_r=0x44c00000\0" \ + "kernel_addr_r=0x45000000\0" \ + "ramdisk_addr_r=0x46000000\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE ".dtb\0" \ BOOTENV #endif -- 2.37.1

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[PATCH 1/2] arm: mvebu: Remove timer.c
by Stefan Roese 06 Oct '22

06 Oct '22

Since the move to CONFIG_TIMER with support for CONFIG_TIMER_EARLY, this platform specific init_timer() function is not needed any more. Let's remove it completely. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Michael Walle <michael(a)walle.cc> Cc: Pali Rohár <pali(a)kernel.org> --- arch/arm/mach-mvebu/Makefile | 5 ----- arch/arm/mach-mvebu/spl.c | 2 -- arch/arm/mach-mvebu/timer.c | 41 ------------------------------------ 3 files changed, 48 deletions(-) delete mode 100644 arch/arm/mach-mvebu/timer.c diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 103e64cf2047..406a9ee8f686 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -16,10 +16,6 @@ obj-y = dram.o obj-y += gpio.o obj-y += mbus.o -ifndef CONFIG_TIMER -obj-y += timer.o -endif - else # CONFIG_ARCH_KIRKWOOD obj-y = cpu.o @@ -97,7 +93,6 @@ $(obj)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ endif # CONFIG_SPL_BUILD obj-y += gpio.o obj-y += mbus.o -obj-y += timer.o obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_SPL_BUILD) += lowlevel_spl.o diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index ca2d5a59d773..424599286e5e 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -340,8 +340,6 @@ void board_init_f(ulong dummy) preloader_console_init(); - timer_init(); - /* Armada 375 does not support SerDes and DDR3 init yet */ #if !defined(CONFIG_ARMADA_375) /* First init the serdes PHY's */ diff --git a/arch/arm/mach-mvebu/timer.c b/arch/arm/mach-mvebu/timer.c deleted file mode 100644 index 557a378776d7..000000000000 --- a/arch/arm/mach-mvebu/timer.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) Marvell International Ltd. and its affiliates - * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> - * - * Copyright (C) 2015 Stefan Roese <sr(a)denx.de> - */ - -#include <common.h> -#include <init.h> -#include <asm/io.h> -#include <asm/arch/soc.h> -#include <linux/bitops.h> - -#define TIMER_LOAD_VAL 0xffffffff - -static int init_done __section(".data") = 0; - -/* - * Timer initialization - */ -int timer_init(void) -{ - /* Only init the timer once */ - if (init_done) - return 0; - init_done = 1; - - /* load value into timer */ - writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x10); - writel(TIMER_LOAD_VAL, MVEBU_TIMER_BASE + 0x14); - -#if defined(CONFIG_ARCH_MVEBU) - /* On Armada XP / 38x ..., the 25MHz clock source needs to be enabled */ - setbits_le32(MVEBU_TIMER_BASE + 0x00, BIT(11)); -#endif - /* enable timer in auto reload mode */ - setbits_le32(MVEBU_TIMER_BASE + 0x00, 0x3); - - return 0; -} -- 2.37.3

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