September 2022 - U-Boot

[PATCH 0/2] ke-am62x-sk_evm: add ospi support
by Dhruva Gole 20 Oct '22

20 Oct '22

There's a S28HS512T Flash (by Cypress) on the AM625 SK EVM. - Add necessary DT nodes to enable OSPI interface with this flash. - Enable all configs that enable the OSPI related drivers and commands like SF probe. Tested on my AM62 SK EVM, attaching logs below. Logs: ------------------------------------------------------------------------ U-Boot SPL 2022.10-rc5-00012-g435596d57f8b-dirty (Sep 26 2022 - 16:27:48 +0530) SYSFW ABI: 3.1 (firmware rev 0x0008 '8.4.6--v08.04.06 (Jolly Jellyfi') Trying to boot from MMC2 Starting ATF on ARM64 core... NOTICE: BL31: v2.7(release):v2.7.0-dirty NOTICE: BL31: Built : 14:30:02, Aug 27 2022 U-Boot SPL 2022.10-rc5-00012-g435596d57f8b-dirty (Sep 26 2022 - 17:51:27 +0530) SYSFW ABI: 3.1 (firmware rev 0x0008 '8.4.6--v08.04.06 (Jolly Jellyfi') Trying to boot from MMC2 U-Boot 2022.10-rc5-00012-g435596d57f8b-dirty (Sep 26 2022 - 17:51:27 +0530) SoC: AM62X SR1.0 GP Model: Texas Instruments AM625 SK DRAM: 2 GiB Core: 37 devices, 18 uclasses, devicetree: separate MMC: mmc@fa10000: 2, mmc@fa00000: 1, mmc@fa20000: 3 Loading Environment from nowhere... OK In: serial@2800000 Out: serial@2800000 Err: serial@2800000 Net: No ethernet found. Hit any key to stop autoboot: 0 => sf probe SF: Detected s28hs512t with page size 256 Bytes, erase size 256 KiB, total 64 MiB => fatload mmc 1 $loadaddr tiboot3.bin 285482 bytes read in 17 ms (16 MiB/s) => sf update $loadaddr 0x0 $filesize device 0 offset 0x0, size 0x45b2a 285482 bytes written, 0 bytes skipped in 2.623s, speed 111322 B/s => sf read 0x90000000 0x0 $filesize device 0 offset 0x0, size 0x45b2a SF: 285482 bytes @ 0x0 Read: OK => md $loadaddr 82000000: 94048230 fd038230 010203a0 64140202 0...0..........d 82000010: 3f829a45 85bb6dd8 232b5568 f8f4176f E..?.m..hU+#o... 82000020: 309fb7ff 2a09060d f7864886 0d01010d ...0...*.H...... 82000030: 81300005 300b319d 55030609 02130604 ..0..1.0...U.... 82000040: 0b315355 03060930 0c080455 31585402 US1.0...U....TX1 82000050: 060d300f 07045503 6144060c 73616c6c .0...U....Dallas 82000060: 25302731 04550306 541e0c0a 73617865 1'0%..U....Texas 82000070: 736e4920 6d757274 73746e65 636e4920 Instruments Inc 82000080: 6f70726f 65746172 30133164 55030611 orporated1.0...U 82000090: 0a0c0b04 636f7250 6f737365 13317372 ....Processors1. 820000a0: 03061130 0c030455 2049540a 70707553 0...U....TI Supp 820000b0: 3174726f 061b301d 48862a09 010df786 ort1.0...*.H.... 820000c0: 0e160109 70707573 4074726f 632e6974 ....support(a)ti.c 820000d0: 1e306d6f 32320d17 36323930 38353031 om0...2209261058 820000e0: 175a3331 3132320d 31363230 31383530 13Z..22102610581 820000f0: 81305a33 300b319d 55030609 02130604 3Z0..1.0...U.... => md 0x90000000 90000000: 94048230 fd038230 010203a0 64140202 0...0..........d 90000010: 3f829a45 85bb6dd8 232b5568 f8f4176f E..?.m..hU+#o... 90000020: 309fb7ff 2a09060d f7864886 0d01010d ...0...*.H...... 90000030: 81300005 300b319d 55030609 02130604 ..0..1.0...U.... 90000040: 0b315355 03060930 0c080455 31585402 US1.0...U....TX1 90000050: 060d300f 07045503 6144060c 73616c6c .0...U....Dallas 90000060: 25302731 04550306 541e0c0a 73617865 1'0%..U....Texas 90000070: 736e4920 6d757274 73746e65 636e4920 Instruments Inc 90000080: 6f70726f 65746172 30133164 55030611 orporated1.0...U 90000090: 0a0c0b04 636f7250 6f737365 13317372 ....Processors1. 900000a0: 03061130 0c030455 2049540a 70707553 0...U....TI Supp 900000b0: 3174726f 061b301d 48862a09 010df786 ort1.0...*.H.... 900000c0: 0e160109 70707573 4074726f 632e6974 ....support(a)ti.c 900000d0: 1e306d6f 32320d17 36323930 38353031 om0...2209261058 900000e0: 175a3331 3132320d 31363230 31383530 13Z..22102610581 900000f0: 81305a33 300b319d 55030609 02130604 3Z0..1.0...U.... => cmp.b $loadaddr 0x90000000 $filesize Total of 285482 byte(s) were the same ------------------------------------------------------------------------ Thus tested read, write and probe flash from u-boot prompt Dhruva Gole (2): arm: dts: k3-am625-sk: Add OSPI support configs: am62x_evm_a53: Enable OSPI Flash support arch/arm/dts/k3-am625-sk-u-boot.dtsi | 24 +++++++++ arch/arm/dts/k3-am625-sk.dts | 77 ++++++++++++++++++++++++++++ configs/am62x_evm_a53_defconfig | 13 +++++ 3 files changed, 114 insertions(+) -- 2.25.1

2 6

[PATCH v2] clk: update clk_clean_rate_cache to use private clk struct
by Patrick Delaunay 20 Oct '22

20 Oct '22

In clk_clean_rate_cache, clk->rate should update the private clock struct, in particular when CCF is activated, to save the cached rate value. When clk_get_parent_rate is called, the cached information is read from pclk->rate, with pclk = clk_get_parent(clk). As the cached is read from private clk data, the update should be done also on it. Fixes: 6b7fd3128f7 ("clk: fix set_rate to clean up cached rates for the hierarchy") Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- Changes in v2: - set *clkp = clk when CCF is not activated and when the clock is not found drivers/clk/clk-uclass.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index b89c77bf794..5cfa022a6dc 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -544,6 +544,19 @@ ulong clk_round_rate(struct clk *clk, ulong rate) return ops->round_rate(clk, rate); } +static void clk_get_priv(struct clk *clk, struct clk **clkp) +{ + *clkp = clk; + + /* get private clock struct associated to the provided clock */ + if (CONFIG_IS_ENABLED(CLK_CCF)) { + /* Take id 0 as a non-valid clk, such as dummy */ + if (clk->id) + clk_get_by_id(clk->id, clkp); + } +} + +/* clean cache, called with private clock struct */ static void clk_clean_rate_cache(struct clk *clk) { struct udevice *child_dev; @@ -563,6 +576,7 @@ static void clk_clean_rate_cache(struct clk *clk) ulong clk_set_rate(struct clk *clk, ulong rate) { const struct clk_ops *ops; + struct clk *clkp; debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate); if (!clk_valid(clk)) @@ -572,8 +586,10 @@ ulong clk_set_rate(struct clk *clk, ulong rate) if (!ops->set_rate) return -ENOSYS; + /* get private clock struct used for cache */ + clk_get_priv(clk, &clkp); /* Clean up cached rates for us and all child clocks */ - clk_clean_rate_cache(clk); + clk_clean_rate_cache(clkp); return ops->set_rate(clk, rate); } -- 2.25.1

3 2

[PATCH] rockchip: clk: pll: Fix constant typo
by Michal Suchanek 20 Oct '22

20 Oct '22

Fixes: bbda2ed584 ("rockchip: clk: pll: add common pll setting funcs") Signed-off-by: Michal Suchanek <msuchanek(a)suse.de> --- drivers/clk/rockchip/clk_pll.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c index 8d2aaf5b84..09b97cf57a 100644 --- a/drivers/clk/rockchip/clk_pll.c +++ b/drivers/clk/rockchip/clk_pll.c @@ -31,7 +31,7 @@ static struct rockchip_pll_rate_table rockchip_auto_table; #define RK3036_PLLCON1_DSMPD_SHIFT 12 #define RK3036_PLLCON2_FRAC_MASK 0xffffff #define RK3036_PLLCON2_FRAC_SHIFT 0 -#define RK3036_PLLCON1_PWRDOWN_SHIT 13 +#define RK3036_PLLCON1_PWRDOWN_SHIFT 13 #define MHZ 1000000 #define KHZ 1000 @@ -207,7 +207,7 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, /* Power down */ rk_setreg(base + pll->con_offset + 0x4, - 1 << RK3036_PLLCON1_PWRDOWN_SHIT); + 1 << RK3036_PLLCON1_PWRDOWN_SHIFT); rk_clrsetreg(base + pll->con_offset, (RK3036_PLLCON0_POSTDIV1_MASK | @@ -231,7 +231,7 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, /* Power Up */ rk_clrreg(base + pll->con_offset + 0x4, - 1 << RK3036_PLLCON1_PWRDOWN_SHIT); + 1 << RK3036_PLLCON1_PWRDOWN_SHIFT); /* waiting for pll lock */ while (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) -- 2.37.3

2 1

[PATCH] clk: change return type of clk_get_parent_rate from long long to ulong
by Michal Suchanek 20 Oct '22

20 Oct '22

All functions getting and setting clock rate use ulong for rate, only clk_get_parent_rate is an exception. Change the return value to match other clock rate funcrions. Most users directly assign the rate to unsigned long anyway, and the few users that use u64 (not s64) multiply the rate so they may need the extra bits for the result in their use case. Fixes: 4aa78300a0 ("dm: clk: Define clk_get_parent_rate() for clk operations") Signed-off-by: Michal Suchanek <msuchanek(a)suse.de> --- drivers/clk/clk-uclass.c | 2 +- include/clk.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index b89c77bf79..4678ed43af 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -505,7 +505,7 @@ struct clk *clk_get_parent(struct clk *clk) return pclk; } -long long clk_get_parent_rate(struct clk *clk) +ulong clk_get_parent_rate(struct clk *clk) { const struct clk_ops *ops; struct clk *pclk; diff --git a/include/clk.h b/include/clk.h index 76bb64bb5e..41a8fb3419 100644 --- a/include/clk.h +++ b/include/clk.h @@ -444,7 +444,7 @@ struct clk *clk_get_parent(struct clk *clk); * * Return: clock rate in Hz, or -ve error code. */ -long long clk_get_parent_rate(struct clk *clk); +ulong clk_get_parent_rate(struct clk *clk); /** * clk_round_rate() - Adjust a rate to the exact rate a clock can provide @@ -577,7 +577,7 @@ static inline struct clk *clk_get_parent(struct clk *clk) return ERR_PTR(-ENOSYS); } -static inline long long clk_get_parent_rate(struct clk *clk) +static inline ulong clk_get_parent_rate(struct clk *clk) { return -ENOSYS; } -- 2.37.3

3 3

[PATCH v17 0/2] add TCP and HTTP for downloading images
by Ying-Chun Liu (PaulLiu) 19 Oct '22

19 Oct '22

From: "Ying-Chun Liu (PaulLiu)" <paul.liu(a)linaro.org> This patch is a refresh from previous patches made by Duncan Hare <DuncanCHare at yahoo.com>. I've contacted him and continue to work on this patch. This patch introduce a TCP stack with SACK. And a simple wget command to download images from http server. v1-v12: Made by Duncan, didn't tracked. v13: Fix some issues which is reviewed by Christian v14: Add options to enable/disable SACK. v15: Fix various syntax errors reviewed by Michal. Remove magic numbers. Use kernel-doc format. v16: Add more kernel-doc. Fix more double spaces. v17: Fix wget with address timeout issue reported by Ramon. Ying-Chun Liu (PaulLiu) (2): net: Add TCP protocol net: Add wget application cmd/Kconfig | 7 + cmd/net.c | 13 + include/net.h | 38 ++- include/net/tcp.h | 312 ++++++++++++++++++++ include/net/wget.h | 22 ++ net/Kconfig | 16 + net/Makefile | 2 + net/net.c | 36 +++ net/tcp.c | 720 +++++++++++++++++++++++++++++++++++++++++++++ net/wget.c | 428 +++++++++++++++++++++++++++ 10 files changed, 1584 insertions(+), 10 deletions(-) create mode 100644 include/net/tcp.h create mode 100644 include/net/wget.h create mode 100644 net/tcp.c create mode 100644 net/wget.c -- 2.35.1

4 7

[PATCH v2 3/3] arm: dts: rockchip: rk3288: partial sync from Linux
by Johan Jonker 19 Oct '22

19 Oct '22

Partial sync of rk3288.dtsi from Linux version 5.18 Changed: only properties and functions that are not yet included swap some clocks positions fix some irq numbers style and sort nodes Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- Changed V2: rebase --- arch/arm/dts/rk3288-veyron-jerry.dts | 6 - arch/arm/dts/rk3288-veyron.dtsi | 4 - arch/arm/dts/rk3288.dtsi | 352 ++++++++++++++++++++++----- 3 files changed, 296 insertions(+), 66 deletions(-) diff --git a/arch/arm/dts/rk3288-veyron-jerry.dts b/arch/arm/dts/rk3288-veyron-jerry.dts index ff7669eb..40fee55c 100644 --- a/arch/arm/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/dts/rk3288-veyron-jerry.dts @@ -137,12 +137,6 @@ }; }; - edp { - edp_hpd: edp_hpd { - rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>; - }; - }; - emmc { /* Make sure eMMC is not in reset */ emmc_deassert_reset: emmc-deassert-reset { diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi index 4a9c27a4..35db8827 100644 --- a/arch/arm/dts/rk3288-veyron.dtsi +++ b/arch/arm/dts/rk3288-veyron.dtsi @@ -560,10 +560,6 @@ status = "okay"; }; -&hdmi_audio { - status = "okay"; -}; - &gpu { status = "okay"; }; diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index f473691c..8c394c1e 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -15,6 +15,7 @@ interrupt-parent = <&gic>; aliases { + ethernet0 = &gmac; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -35,6 +36,15 @@ spi2 = &spi2; }; + arm-pmu { + compatible = "arm,cortex-a12-pmu"; + interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -141,6 +151,26 @@ }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* + * The rk3288 cannot use the memory area above 0xfe000000 + * for dma operations for some reason. While there is + * probably a better solution available somewhere, we + * haven't found it yet and while devices with 2GB of ram + * are not affected, this issue prevents 4GB from booting. + * So to make these devices at least bootable, block + * this area for the time being until the real solution + * is found. + */ + dma-unusable@fe000000 { + reg = <0xfe000000 0x1000000>; + }; + }; + xin24m: oscillator { compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -149,14 +179,22 @@ }; timer { - arm,use-physical-timer; compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; clock-frequency = <24000000>; - always-on; + arm,no-tick-in-suspend; + }; + + timer: timer@ff810000 { + compatible = "rockchip,rk3288-timer"; + reg = <0x0 0xff810000 0x0 0x20>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; }; display-subsystem { @@ -173,6 +211,8 @@ fifo-depth = <0x100>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; reg = <0xff0c0000 0x4000>; + resets = <&cru SRST_MMC0>; + reset-names = "reset"; status = "disabled"; }; @@ -185,6 +225,8 @@ fifo-depth = <0x100>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; reg = <0xff0d0000 0x4000>; + resets = <&cru SRST_SDIO0>; + reset-names = "reset"; status = "disabled"; }; @@ -197,6 +239,8 @@ fifo-depth = <0x100>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; reg = <0xff0e0000 0x4000>; + resets = <&cru SRST_SDIO1>; + reset-names = "reset"; status = "disabled"; }; @@ -209,6 +253,8 @@ fifo-depth = <0x100>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; reg = <0xff0f0000 0x4000>; + resets = <&cru SRST_EMMC>; + reset-names = "reset"; status = "disabled"; }; @@ -219,6 +265,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; }; @@ -318,6 +366,7 @@ pinctrl-0 = <&i2c5_xfer>; status = "disabled"; }; + uart0: serial@ff180000 { compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; reg = <0xff180000 0x100>; @@ -326,6 +375,8 @@ reg-io-width = <4>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac_peri 1>, <&dmac_peri 2>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>; status = "disabled"; @@ -339,6 +390,8 @@ reg-io-width = <4>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac_peri 3>, <&dmac_peri 4>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart1_xfer>; status = "disabled"; @@ -356,6 +409,7 @@ pinctrl-0 = <&uart2_xfer>; status = "disabled"; }; + uart3: serial@ff1b0000 { compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart"; reg = <0xff1b0000 0x100>; @@ -364,6 +418,8 @@ reg-io-width = <4>; clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac_peri 7>, <&dmac_peri 8>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart3_xfer>; status = "disabled"; @@ -377,6 +433,8 @@ reg-io-width = <4>; clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac_peri 9>, <&dmac_peri 10>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&uart4_xfer>; status = "disabled"; @@ -388,7 +446,8 @@ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; - broken-no-flushp; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMAC2>; clock-names = "apb_pclk"; }; @@ -503,6 +562,8 @@ "mac_clk_rx", "mac_clk_tx", "clk_mac_ref", "clk_mac_refout", "aclk_mac", "pclk_mac"; + resets = <&cru SRST_MAC>; + reset-names = "stmmaceth"; }; usb_host0_ehci: usb@ff500000 { @@ -516,7 +577,7 @@ status = "disabled"; }; - /* NOTE: doesn't work on RK3288, but fixed on RK3288W */ + /* NOTE: doesn't work on RK3288, but was fixed on RK3288W */ usb_host0_ohci: usb@ff520000 { compatible = "generic-ohci"; reg = <0x0 0xff520000 0x0 0x100>; @@ -534,8 +595,10 @@ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_USBHOST1>; clock-names = "otg"; + dr_mode = "host"; phys = <&usbphy2>; phy-names = "usb2-phy"; + snps,reset-phy-on-wake; status = "disabled"; }; @@ -547,6 +610,9 @@ clocks = <&cru HCLK_OTG0>; clock-names = "otg"; dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <275>; + g-tx-fifo-size = <256 128 128 64 64 32>; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; @@ -567,7 +633,8 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; - broken-no-flushp; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMAC1>; clock-names = "apb_pclk"; status = "disabled"; @@ -647,7 +714,7 @@ status = "disabled"; }; - bus_intmem: bus_intmem@ff700000 { + bus_intmem: sram@ff700000 { compatible = "mmio-sram"; reg = <0xff700000 0x18000>; #address-cells = <1>; @@ -659,7 +726,7 @@ }; }; - sram@ff720000 { + pmu_sram: sram@ff720000 { compatible = "rockchip,rk3288-pmu-sram", "mmio-sram"; reg = <0xff720000 0x1000>; }; @@ -701,7 +768,7 @@ compatible = "rockchip,rk3288-wdt", "snps,dw-wdt"; reg = <0xff800000 0x100>; clocks = <&cru PCLK_WDT>; - interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -709,11 +776,11 @@ compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; reg = <0xff8b0000 0x10000>; #sound-dai-cells = <0>; - clock-names = "hclk", "mclk"; - clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; + clocks = <&cru SCLK_SPDIF8CH>, <&cru HCLK_SPDIF8CH>; + clock-names = "mclk", "hclk"; dmas = <&dmac_bus_s 3>; dma-names = "tx"; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&spdif_tx>; rockchip,grf = <&grf>; @@ -723,50 +790,97 @@ i2s: i2s@ff890000 { compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; reg = <0xff890000 0x10000>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - #sound-dai-cells = <1>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0>; + clock-names = "i2s_clk", "i2s_hclk"; dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; dma-names = "tx", "rx"; - clock-names = "i2s_hclk", "i2s_clk"; - clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <2>; + status = "disabled"; + }; + + crypto: crypto@ff8a0000 { + compatible = "rockchip,rk3288-crypto"; + reg = <0xff8a0000 0x4000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, + <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>; + clock-names = "aclk", "hclk", "sclk", "apb_pclk"; + resets = <&cru SRST_CRYPTO>; + reset-names = "crypto-rst"; + }; + + iep_mmu: iommu@ff900800 { + compatible = "rockchip,iommu"; + reg = <0xff900800 0x40>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; status = "disabled"; }; + isp_mmu: iommu@ff914000 { + compatible = "rockchip,iommu"; + reg = <0xff914000 0x100>, <0xff915000 0x100>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + rga: rga@ff920000 { + compatible = "rockchip,rk3288-rga"; + reg = <0xff920000 0x180>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; + clock-names = "aclk", "hclk", "sclk"; + power-domains = <&power RK3288_PD_VIO>; + resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>; + reset-names = "core", "axi", "ahb"; + }; + vopb: vop@ff930000 { compatible = "rockchip,rk3288-vop"; reg = <0xff930000 0x19c>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3288_PD_VIO>; resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; reset-names = "axi", "ahb", "dclk"; iommus = <&vopb_mmu>; - power-domains = <&power RK3288_PD_VIO>; status = "disabled"; + vopb_out: port { #address-cells = <1>; #size-cells = <0>; + vopb_out_edp: endpoint@0 { reg = <0>; remote-endpoint = <&edp_in_vopb>; }; + vopb_out_hdmi: endpoint@1 { reg = <1>; remote-endpoint = <&hdmi_in_vopb>; }; + vopb_out_lvds: endpoint@2 { reg = <2>; remote-endpoint = <&lvds_in_vopb>; }; + vopb_out_mipi: endpoint@3 { reg = <3>; remote-endpoint = <&mipi_in_vopb>; }; - }; }; @@ -774,7 +888,8 @@ compatible = "rockchip,iommu"; reg = <0xff930300 0x100>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vopb_mmu"; + clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; + clock-names = "aclk", "iface"; power-domains = <&power RK3288_PD_VIO>; #iommu-cells = <0>; status = "disabled"; @@ -786,31 +901,35 @@ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK3288_PD_VIO>; resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; reset-names = "axi", "ahb", "dclk"; iommus = <&vopl_mmu>; - power-domains = <&power RK3288_PD_VIO>; status = "disabled"; + vopl_out: port { #address-cells = <1>; #size-cells = <0>; + vopl_out_edp: endpoint@0 { reg = <0>; remote-endpoint = <&edp_in_vopl>; }; + vopl_out_hdmi: endpoint@1 { reg = <1>; remote-endpoint = <&hdmi_in_vopl>; }; + vopl_out_lvds: endpoint@2 { reg = <2>; remote-endpoint = <&lvds_in_vopl>; }; + vopl_out_mipi: endpoint@3 { reg = <3>; remote-endpoint = <&mipi_in_vopl>; }; - }; }; @@ -818,7 +937,8 @@ compatible = "rockchip,iommu"; reg = <0xff940300 0x100>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vopl_mmu"; + clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk", "iface"; power-domains = <&power RK3288_PD_VIO>; #iommu-cells = <0>; status = "disabled"; @@ -827,16 +947,14 @@ mipi_dsi: mipi@ff960000 { compatible = "rockchip,rk3288_mipi_dsi"; reg = <0xff960000 0x4000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_MIPI_DSI0>; clock-names = "pclk_mipi"; - /*pinctrl-names = "default"; - pinctrl-0 = <&lcdc0_ctl>;*/ + power-domains = <&power RK3288_PD_VIO>; rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; + ports { - reg = <1>; mipi_in: port { #address-cells = <1>; #size-cells = <0>; @@ -858,16 +976,21 @@ clocks = <&cru PCLK_LVDS_PHY>; clock-names = "pclk_lvds"; pinctrl-names = "default"; - pinctrl-0 = <&lcdc0_ctl>; + pinctrl-0 = <&lcdc_ctl>; + power-domains = <&power RK3288_PD_VIO>; rockchip,grf = <&grf>; status = "disabled"; + ports { #address-cells = <1>; #size-cells = <0>; + lvds_in: port@0 { reg = <0>; + #address-cells = <1>; #size-cells = <0>; + lvds_in_vopb: endpoint@0 { reg = <0>; remote-endpoint = <&vopb_out_lvds>; @@ -885,12 +1008,13 @@ reg = <0xff970000 0x4000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>; - rockchip,grf = <&grf>; clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; - resets = <&cru 111>; + resets = <&cru SRST_EDP>; reset-names = "edp"; + rockchip,grf = <&grf>; power-domains = <&power RK3288_PD_VIO>; status = "disabled"; + ports { edp_in: port { #address-cells = <1>; @@ -911,12 +1035,14 @@ compatible = "rockchip,rk3288-dw-hdmi"; reg = <0xff980000 0x20000>; reg-io-width = <4>; - ddc-i2c-bus = <&i2c5>; + #sound-dai-cells = <0>; rockchip,grf = <&grf>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; clock-names = "iahb", "isfr"; + power-domains = <&power RK3288_PD_VIO>; status = "disabled"; + ports { hdmi_in: port { #address-cells = <1>; @@ -933,31 +1059,36 @@ }; }; - hdmi_audio: hdmi_audio { - compatible = "rockchip,rk3288-hdmi-audio"; - i2s-controller = <&i2s>; - status = "disable"; - }; - vpu: video-codec@ff9a0000 { compatible = "rockchip,rk3288-vpu"; reg = <0xff9a0000 0x800>; interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "vepu", "vdpu"; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; - clock-names = "aclk_vcodec", "hclk_vcodec"; - power-domains = <&power RK3288_PD_VIDEO>; + clock-names = "aclk", "hclk"; iommus = <&vpu_mmu>; + power-domains = <&power RK3288_PD_VIDEO>; }; vpu_mmu: iommu@ff9a0800 { compatible = "rockchip,iommu"; reg = <0xff9a0800 0x100>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; power-domains = <&power RK3288_PD_VIDEO>; + }; + + hevc_mmu: iommu@ff9c0440 { + compatible = "rockchip,iommu"; + reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; + clock-names = "aclk", "iface"; #iommu-cells = <0>; + status = "disabled"; }; gpu: gpu@ffa30000 { @@ -999,13 +1130,84 @@ }; }; + qos_gpu_r: qos@ffaa0000 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0xffaa0000 0x20>; + }; + + qos_gpu_w: qos@ffaa0080 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0xffaa0080 0x20>; + }; + + qos_vio1_vop: qos@ffad0000 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0xffad0000 0x20>; + }; + + qos_vio1_isp_w0: qos@ffad0100 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0xffad0100 0x20>; + }; + + qos_vio1_isp_w1: qos@ffad0180 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0x0 0xffad0180 0x0 0x20>; + }; + + qos_vio0_vop: qos@ffad0400 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0x0 0xffad0400 0x0 0x20>; + }; + + qos_vio0_vip: qos@ffad0480 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0xffad0480 0x20>; + }; + + qos_vio0_iep: qos@ffad0500 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0xffad0500 0x20>; + }; + + qos_vio2_rga_r: qos@ffad0800 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0xffad0800 0x20>; + }; + + qos_vio2_rga_w: qos@ffad0880 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0xffad0880 0x20>; + }; + + qos_vio1_isp_r: qos@ffad0900 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0xffad0900 0x20>; + }; + + qos_video: qos@ffae0000 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0xffae0000 0x20>; + }; + + qos_hevc_r: qos@ffaf0000 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0xffaf0000 0x20>; + }; + + qos_hevc_w: qos@ffaf0080 { + compatible = "rockchip,rk3288-qos", "syscon"; + reg = <0xffaf0080 0x20>; + }; + dmac_bus_s: dma-controller@ffb20000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xffb20000 0x4000>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; - broken-no-flushp; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; clocks = <&cru ACLK_DMAC1>; clock-names = "apb_pclk"; }; @@ -1013,7 +1215,17 @@ efuse: efuse@ffb40000 { compatible = "rockchip,rk3288-efuse"; reg = <0xffb40000 0x10000>; - status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE256>; + clock-names = "pclk_efuse"; + + cpu_id: cpu-id@7 { + reg = <0x07 0x10>; + }; + cpu_leakage: cpu_leakage@17 { + reg = <0x17 0x1>; + }; }; gic: interrupt-controller@ffc01000 { @@ -1072,7 +1284,7 @@ gpio0: gpio0@ff750000 { compatible = "rockchip,gpio-bank"; - reg = <0xff750000 0x100>; + reg = <0xff750000 0x100>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru PCLK_GPIO0>; @@ -1191,6 +1403,24 @@ hdmi_cec_c0: hdmi-cec-c0 { rockchip,pins = <7 RK_PC0 2 &pcfg_pull_none>; }; + + hdmi_cec_c7: hdmi-cec-c7 { + rockchip,pins = <7 RK_PC7 4 &pcfg_pull_none>; + }; + + hdmi_ddc: hdmi-ddc { + rockchip,pins = <7 RK_PC3 2 &pcfg_pull_none>, + <7 RK_PC4 2 &pcfg_pull_none>; + }; + + hdmi_ddc_unwedge: hdmi-ddc-unwedge { + rockchip,pins = <7 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>, + <7 RK_PC4 2 &pcfg_pull_none>; + }; + }; + + pcfg_output_low: pcfg-output-low { + output-low; }; pcfg_pull_up: pcfg-pull-up { @@ -1210,7 +1440,7 @@ drive-strength = <12>; }; - sleep { + suspend { global_pwroff: global-pwroff { rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>; }; @@ -1228,6 +1458,12 @@ }; }; + edp { + edp_hpd: edp-hpd { + rockchip,pins = <7 RK_PB3 2 &pcfg_pull_down>; + }; + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>, @@ -1281,8 +1517,8 @@ }; }; - lcdc0 { - lcdc0_ctl: lcdc0-ctl { + lcdc { + lcdc_ctl: lcdc-ctl { rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, <1 RK_PD1 1 &pcfg_pull_none>, <1 RK_PD2 1 &pcfg_pull_none>, @@ -1299,7 +1535,7 @@ rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>; }; - sdmmc_cd: sdmcc-cd { + sdmmc_cd: sdmmc-cd { rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>; }; @@ -1490,7 +1726,7 @@ }; uart0_cts: uart0-cts { - rockchip,pins = <4 RK_PC2 1 &pcfg_pull_none>; + rockchip,pins = <4 RK_PC2 1 &pcfg_pull_up>; }; uart0_rts: uart0-rts { @@ -1505,7 +1741,7 @@ }; uart1_cts: uart1-cts { - rockchip,pins = <5 RK_PB2 1 &pcfg_pull_none>; + rockchip,pins = <5 RK_PB2 1 &pcfg_pull_up>; }; uart1_rts: uart1-rts { @@ -1528,7 +1764,7 @@ }; uart3_cts: uart3-cts { - rockchip,pins = <7 RK_PB1 1 &pcfg_pull_none>; + rockchip,pins = <7 RK_PB1 1 &pcfg_pull_up>; }; uart3_rts: uart3-rts { @@ -1538,20 +1774,24 @@ uart4 { uart4_xfer: uart4-xfer { - rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>, - <5 RK_PB5 3 &pcfg_pull_none>; + rockchip,pins = <5 RK_PB7 3 &pcfg_pull_up>, + <5 RK_PB6 3 &pcfg_pull_none>; }; uart4_cts: uart4-cts { - rockchip,pins = <5 RK_PB6 3 &pcfg_pull_none>; + rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>; }; uart4_rts: uart4-rts { - rockchip,pins = <5 RK_PB7 3 &pcfg_pull_none>; + rockchip,pins = <5 RK_PB5 3 &pcfg_pull_none>; }; }; tsadc { + otp_pin: otp-pin { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + otp_out: otp-out { rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>; }; -- 2.20.1

3 8

[PATCH 1/2] arm: dts: k3-am64-sk: EMIF tool update to v0.08.40 and move to 1600MT/s LPDDR4
by Anand Gadiyar 19 Oct '22

19 Oct '22

From: Dave Gerlach <d-gerlach(a)ti.com> Move k3-am64-sk to use 1600MT/s LPDDR4 configuration and update to latest EMIF tool v0.08.40. Signed-off-by: Dave Gerlach <d-gerlach(a)ti.com> Signed-off-by: Anand Gadiyar <gadiyar(a)ti.com> --- ...33MTs.dtsi => k3-am64-sk-lp4-1600MTs.dtsi} | 371 +++++++++--------- arch/arm/dts/k3-am642-r5-sk.dts | 2 +- 2 files changed, 186 insertions(+), 187 deletions(-) rename arch/arm/dts/{k3-am64-sk-lp4-1333MTs.dtsi => k3-am64-sk-lp4-1600MTs.dtsi} (91%) diff --git a/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi b/arch/arm/dts/k3-am64-sk-lp4-1600MTs.dtsi similarity index 91% rename from arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi rename to arch/arm/dts/k3-am64-sk-lp4-1600MTs.dtsi index dde5ab150d..f225c1f067 100644 --- a/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi +++ b/arch/arm/dts/k3-am64-sk-lp4-1600MTs.dtsi @@ -1,18 +1,17 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ * This file was generated with the - * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.00 - * Wed Oct 13 2021 10:08:29 GMT-0500 (Central Daylight Time) + * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.40 + * Wed Feb 02 2022 16:59:34 GMT-0600 (Central Standard Time) * DDR Type: LPDDR4 - * F0 = 50MHz F1 = 666.7MHz F2 = 666.7MHz + * F0 = 50MHz F1 = 800MHz F2 = 800MHz * Density (per channel): 16Gb * Number of Ranks: 1 -*/ + */ #define DDRSS_PLL_FHS_CNT 6 -#define DDRSS_PLL_FREQUENCY_1 333350000 -#define DDRSS_PLL_FREQUENCY_2 333350000 +#define DDRSS_PLL_FREQUENCY_1 400000000 +#define DDRSS_PLL_FREQUENCY_2 400000000 #define DDRSS_CTL_0_DATA 0x00000B00 #define DDRSS_CTL_1_DATA 0x00000000 @@ -25,14 +24,14 @@ #define DDRSS_CTL_8_DATA 0x000186A0 #define DDRSS_CTL_9_DATA 0x00000005 #define DDRSS_CTL_10_DATA 0x00000064 -#define DDRSS_CTL_11_DATA 0x000208D6 -#define DDRSS_CTL_12_DATA 0x00145856 +#define DDRSS_CTL_11_DATA 0x00027100 +#define DDRSS_CTL_12_DATA 0x00186A00 #define DDRSS_CTL_13_DATA 0x00000005 -#define DDRSS_CTL_14_DATA 0x00000536 -#define DDRSS_CTL_15_DATA 0x000208D6 -#define DDRSS_CTL_16_DATA 0x00145856 +#define DDRSS_CTL_14_DATA 0x00000640 +#define DDRSS_CTL_15_DATA 0x00027100 +#define DDRSS_CTL_16_DATA 0x00186A00 #define DDRSS_CTL_17_DATA 0x00000005 -#define DDRSS_CTL_18_DATA 0x00000536 +#define DDRSS_CTL_18_DATA 0x00000640 #define DDRSS_CTL_19_DATA 0x01010100 #define DDRSS_CTL_20_DATA 0x01010100 #define DDRSS_CTL_21_DATA 0x01000110 @@ -48,8 +47,8 @@ #define DDRSS_CTL_31_DATA 0x00000000 #define DDRSS_CTL_32_DATA 0x00000000 #define DDRSS_CTL_33_DATA 0x00000000 -#define DDRSS_CTL_34_DATA 0x02000010 -#define DDRSS_CTL_35_DATA 0x00001B1B +#define DDRSS_CTL_34_DATA 0x08000010 +#define DDRSS_CTL_35_DATA 0x00002020 #define DDRSS_CTL_36_DATA 0x00000000 #define DDRSS_CTL_37_DATA 0x00000000 #define DDRSS_CTL_38_DATA 0x0000040C @@ -62,64 +61,64 @@ #define DDRSS_CTL_45_DATA 0x00000700 #define DDRSS_CTL_46_DATA 0x09090004 #define DDRSS_CTL_47_DATA 0x00000203 -#define DDRSS_CTL_48_DATA 0x00290006 -#define DDRSS_CTL_49_DATA 0x0909001D -#define DDRSS_CTL_50_DATA 0x0000150C -#define DDRSS_CTL_51_DATA 0x00290006 -#define DDRSS_CTL_52_DATA 0x0909001D -#define DDRSS_CTL_53_DATA 0x0900150C +#define DDRSS_CTL_48_DATA 0x00320007 +#define DDRSS_CTL_49_DATA 0x09090023 +#define DDRSS_CTL_50_DATA 0x0000190F +#define DDRSS_CTL_51_DATA 0x00320007 +#define DDRSS_CTL_52_DATA 0x09090023 +#define DDRSS_CTL_53_DATA 0x0900190F #define DDRSS_CTL_54_DATA 0x000A0A09 #define DDRSS_CTL_55_DATA 0x040006DB #define DDRSS_CTL_56_DATA 0x09092004 -#define DDRSS_CTL_57_DATA 0x00000A0A -#define DDRSS_CTL_58_DATA 0x05005B68 -#define DDRSS_CTL_59_DATA 0x09092005 -#define DDRSS_CTL_60_DATA 0x00000A0A -#define DDRSS_CTL_61_DATA 0x05005B68 -#define DDRSS_CTL_62_DATA 0x03042005 +#define DDRSS_CTL_57_DATA 0x00000C0A +#define DDRSS_CTL_58_DATA 0x06006DB0 +#define DDRSS_CTL_59_DATA 0x09092006 +#define DDRSS_CTL_60_DATA 0x00000C0A +#define DDRSS_CTL_61_DATA 0x06006DB0 +#define DDRSS_CTL_62_DATA 0x03042006 #define DDRSS_CTL_63_DATA 0x04050002 -#define DDRSS_CTL_64_DATA 0x0E0D0E0D +#define DDRSS_CTL_64_DATA 0x100F100F #define DDRSS_CTL_65_DATA 0x01010008 -#define DDRSS_CTL_66_DATA 0x041A1A07 -#define DDRSS_CTL_67_DATA 0x030E0E03 -#define DDRSS_CTL_68_DATA 0x00000E0E +#define DDRSS_CTL_66_DATA 0x041F1F07 +#define DDRSS_CTL_67_DATA 0x03111103 +#define DDRSS_CTL_68_DATA 0x00001111 #define DDRSS_CTL_69_DATA 0x00000101 #define DDRSS_CTL_70_DATA 0x00000000 #define DDRSS_CTL_71_DATA 0x01000000 #define DDRSS_CTL_72_DATA 0x00130803 #define DDRSS_CTL_73_DATA 0x000000BB -#define DDRSS_CTL_74_DATA 0x000000FE -#define DDRSS_CTL_75_DATA 0x00000A20 -#define DDRSS_CTL_76_DATA 0x000000FE -#define DDRSS_CTL_77_DATA 0x00000A20 +#define DDRSS_CTL_74_DATA 0x00000130 +#define DDRSS_CTL_75_DATA 0x00000C28 +#define DDRSS_CTL_76_DATA 0x00000130 +#define DDRSS_CTL_77_DATA 0x00000C28 #define DDRSS_CTL_78_DATA 0x00000005 #define DDRSS_CTL_79_DATA 0x0000000A #define DDRSS_CTL_80_DATA 0x00000010 -#define DDRSS_CTL_81_DATA 0x0000007F -#define DDRSS_CTL_82_DATA 0x0000013D -#define DDRSS_CTL_83_DATA 0x0000007F -#define DDRSS_CTL_84_DATA 0x0000013D +#define DDRSS_CTL_81_DATA 0x00000098 +#define DDRSS_CTL_82_DATA 0x0000017E +#define DDRSS_CTL_83_DATA 0x00000098 +#define DDRSS_CTL_84_DATA 0x0000017E #define DDRSS_CTL_85_DATA 0x03004000 #define DDRSS_CTL_86_DATA 0x00001201 -#define DDRSS_CTL_87_DATA 0x00050005 -#define DDRSS_CTL_88_DATA 0x00000005 +#define DDRSS_CTL_87_DATA 0x00060005 +#define DDRSS_CTL_88_DATA 0x00000006 #define DDRSS_CTL_89_DATA 0x00000000 -#define DDRSS_CTL_90_DATA 0x05101008 +#define DDRSS_CTL_90_DATA 0x05121208 #define DDRSS_CTL_91_DATA 0x05030A05 -#define DDRSS_CTL_92_DATA 0x05030A05 -#define DDRSS_CTL_93_DATA 0x01030A05 +#define DDRSS_CTL_92_DATA 0x05030C06 +#define DDRSS_CTL_93_DATA 0x01030C06 #define DDRSS_CTL_94_DATA 0x02010201 #define DDRSS_CTL_95_DATA 0x00001401 -#define DDRSS_CTL_96_DATA 0x01030014 -#define DDRSS_CTL_97_DATA 0x01030103 -#define DDRSS_CTL_98_DATA 0x00000103 +#define DDRSS_CTL_96_DATA 0x01360014 +#define DDRSS_CTL_97_DATA 0x01360136 +#define DDRSS_CTL_98_DATA 0x00000136 #define DDRSS_CTL_99_DATA 0x00000000 #define DDRSS_CTL_100_DATA 0x05010303 -#define DDRSS_CTL_101_DATA 0x0A040505 -#define DDRSS_CTL_102_DATA 0x05050203 -#define DDRSS_CTL_103_DATA 0x030A0505 -#define DDRSS_CTL_104_DATA 0x05050502 -#define DDRSS_CTL_105_DATA 0x03030305 +#define DDRSS_CTL_101_DATA 0x0C040505 +#define DDRSS_CTL_102_DATA 0x06050203 +#define DDRSS_CTL_103_DATA 0x030C0605 +#define DDRSS_CTL_104_DATA 0x05060502 +#define DDRSS_CTL_105_DATA 0x03030306 #define DDRSS_CTL_106_DATA 0x03010000 #define DDRSS_CTL_107_DATA 0x00010000 #define DDRSS_CTL_108_DATA 0x00000000 @@ -140,20 +139,20 @@ #define DDRSS_CTL_123_DATA 0x00002EC0 #define DDRSS_CTL_124_DATA 0x00000000 #define DDRSS_CTL_125_DATA 0x0000051D -#define DDRSS_CTL_126_DATA 0x00028800 -#define DDRSS_CTL_127_DATA 0x00028800 -#define DDRSS_CTL_128_DATA 0x00028800 -#define DDRSS_CTL_129_DATA 0x00028800 -#define DDRSS_CTL_130_DATA 0x00028800 +#define DDRSS_CTL_126_DATA 0x00030A00 +#define DDRSS_CTL_127_DATA 0x00030A00 +#define DDRSS_CTL_128_DATA 0x00030A00 +#define DDRSS_CTL_129_DATA 0x00030A00 +#define DDRSS_CTL_130_DATA 0x00030A00 #define DDRSS_CTL_131_DATA 0x00000000 -#define DDRSS_CTL_132_DATA 0x000046E0 -#define DDRSS_CTL_133_DATA 0x00028800 -#define DDRSS_CTL_134_DATA 0x00028800 -#define DDRSS_CTL_135_DATA 0x00028800 -#define DDRSS_CTL_136_DATA 0x00028800 -#define DDRSS_CTL_137_DATA 0x00028800 +#define DDRSS_CTL_132_DATA 0x00005518 +#define DDRSS_CTL_133_DATA 0x00030A00 +#define DDRSS_CTL_134_DATA 0x00030A00 +#define DDRSS_CTL_135_DATA 0x00030A00 +#define DDRSS_CTL_136_DATA 0x00030A00 +#define DDRSS_CTL_137_DATA 0x00030A00 #define DDRSS_CTL_138_DATA 0x00000000 -#define DDRSS_CTL_139_DATA 0x000046E0 +#define DDRSS_CTL_139_DATA 0x00005518 #define DDRSS_CTL_140_DATA 0x00000000 #define DDRSS_CTL_141_DATA 0x00000000 #define DDRSS_CTL_142_DATA 0x00000000 @@ -209,12 +208,12 @@ #define DDRSS_CTL_192_DATA 0x0005000A #define DDRSS_CTL_193_DATA 0x0404000D #define DDRSS_CTL_194_DATA 0x0000000D -#define DDRSS_CTL_195_DATA 0x00430086 -#define DDRSS_CTL_196_DATA 0x050500A7 -#define DDRSS_CTL_197_DATA 0x000000A7 -#define DDRSS_CTL_198_DATA 0x00430086 -#define DDRSS_CTL_199_DATA 0x050500A7 -#define DDRSS_CTL_200_DATA 0x000000A7 +#define DDRSS_CTL_195_DATA 0x005000A0 +#define DDRSS_CTL_196_DATA 0x060600C8 +#define DDRSS_CTL_197_DATA 0x000000C8 +#define DDRSS_CTL_198_DATA 0x005000A0 +#define DDRSS_CTL_199_DATA 0x060600C8 +#define DDRSS_CTL_200_DATA 0x000000C8 #define DDRSS_CTL_201_DATA 0x00000000 #define DDRSS_CTL_202_DATA 0x00000000 #define DDRSS_CTL_203_DATA 0x00000000 @@ -239,11 +238,11 @@ #define DDRSS_CTL_222_DATA 0x00000000 #define DDRSS_CTL_223_DATA 0x00000000 #define DDRSS_CTL_224_DATA 0x00000031 -#define DDRSS_CTL_225_DATA 0x00000031 -#define DDRSS_CTL_226_DATA 0x00000031 +#define DDRSS_CTL_225_DATA 0x000000B1 +#define DDRSS_CTL_226_DATA 0x000000B1 #define DDRSS_CTL_227_DATA 0x00000031 -#define DDRSS_CTL_228_DATA 0x00000031 -#define DDRSS_CTL_229_DATA 0x00000031 +#define DDRSS_CTL_228_DATA 0x000000B1 +#define DDRSS_CTL_229_DATA 0x000000B1 #define DDRSS_CTL_230_DATA 0x00000000 #define DDRSS_CTL_231_DATA 0x00000000 #define DDRSS_CTL_232_DATA 0x00000000 @@ -323,12 +322,12 @@ #define DDRSS_CTL_306_DATA 0x00400100 #define DDRSS_CTL_307_DATA 0x00080032 #define DDRSS_CTL_308_DATA 0x01000200 -#define DDRSS_CTL_309_DATA 0x029B0040 -#define DDRSS_CTL_310_DATA 0x00020014 +#define DDRSS_CTL_309_DATA 0x03200040 +#define DDRSS_CTL_310_DATA 0x00020018 #define DDRSS_CTL_311_DATA 0x00400100 -#define DDRSS_CTL_312_DATA 0x0014029B +#define DDRSS_CTL_312_DATA 0x00180320 #define DDRSS_CTL_313_DATA 0x00030000 -#define DDRSS_CTL_314_DATA 0x00220022 +#define DDRSS_CTL_314_DATA 0x00280028 #define DDRSS_CTL_315_DATA 0x00000100 #define DDRSS_CTL_316_DATA 0x01010000 #define DDRSS_CTL_317_DATA 0x00000000 @@ -344,9 +343,9 @@ #define DDRSS_CTL_327_DATA 0x00000C01 #define DDRSS_CTL_328_DATA 0x01000100 #define DDRSS_CTL_329_DATA 0x00000000 -#define DDRSS_CTL_330_DATA 0x01000000 +#define DDRSS_CTL_330_DATA 0x00000000 #define DDRSS_CTL_331_DATA 0x01030303 -#define DDRSS_CTL_332_DATA 0x00000000 +#define DDRSS_CTL_332_DATA 0x00000001 #define DDRSS_CTL_333_DATA 0x00000000 #define DDRSS_CTL_334_DATA 0x00000000 #define DDRSS_CTL_335_DATA 0x00000000 @@ -390,14 +389,14 @@ #define DDRSS_CTL_373_DATA 0x00010101 #define DDRSS_CTL_374_DATA 0x01050503 #define DDRSS_CTL_375_DATA 0x05020201 -#define DDRSS_CTL_376_DATA 0x08080B0B +#define DDRSS_CTL_376_DATA 0x08080C0C #define DDRSS_CTL_377_DATA 0x00080308 -#define DDRSS_CTL_378_DATA 0x000C030E -#define DDRSS_CTL_379_DATA 0x000C0310 -#define DDRSS_CTL_380_DATA 0x0C0C0810 +#define DDRSS_CTL_378_DATA 0x000B030E +#define DDRSS_CTL_379_DATA 0x000B0310 +#define DDRSS_CTL_380_DATA 0x0B0B0810 #define DDRSS_CTL_381_DATA 0x01000000 -#define DDRSS_CTL_382_DATA 0x03010301 -#define DDRSS_CTL_383_DATA 0x04000101 +#define DDRSS_CTL_382_DATA 0x03020301 +#define DDRSS_CTL_383_DATA 0x04000102 #define DDRSS_CTL_384_DATA 0x1B000004 #define DDRSS_CTL_385_DATA 0x00000176 #define DDRSS_CTL_386_DATA 0x00000200 @@ -407,24 +406,24 @@ #define DDRSS_CTL_390_DATA 0x00000693 #define DDRSS_CTL_391_DATA 0x00000E9C #define DDRSS_CTL_392_DATA 0x03050202 -#define DDRSS_CTL_393_DATA 0x00240201 -#define DDRSS_CTL_394_DATA 0x00001440 +#define DDRSS_CTL_393_DATA 0x00250201 +#define DDRSS_CTL_394_DATA 0x00001850 #define DDRSS_CTL_395_DATA 0x00000200 #define DDRSS_CTL_396_DATA 0x00000200 #define DDRSS_CTL_397_DATA 0x00000200 #define DDRSS_CTL_398_DATA 0x00000200 -#define DDRSS_CTL_399_DATA 0x00005B20 -#define DDRSS_CTL_400_DATA 0x0000CA80 -#define DDRSS_CTL_401_DATA 0x080D0402 -#define DDRSS_CTL_402_DATA 0x00240405 -#define DDRSS_CTL_403_DATA 0x00001440 +#define DDRSS_CTL_399_DATA 0x00006D68 +#define DDRSS_CTL_400_DATA 0x0000F320 +#define DDRSS_CTL_401_DATA 0x070D0402 +#define DDRSS_CTL_402_DATA 0x00250405 +#define DDRSS_CTL_403_DATA 0x00001850 #define DDRSS_CTL_404_DATA 0x00000200 #define DDRSS_CTL_405_DATA 0x00000200 #define DDRSS_CTL_406_DATA 0x00000200 #define DDRSS_CTL_407_DATA 0x00000200 -#define DDRSS_CTL_408_DATA 0x00005B20 -#define DDRSS_CTL_409_DATA 0x0000CA80 -#define DDRSS_CTL_410_DATA 0x080D0402 +#define DDRSS_CTL_408_DATA 0x00006D68 +#define DDRSS_CTL_409_DATA 0x0000F320 +#define DDRSS_CTL_410_DATA 0x070D0402 #define DDRSS_CTL_411_DATA 0x00000405 #define DDRSS_CTL_412_DATA 0x00000000 #define DDRSS_CTL_413_DATA 0x0302000A @@ -483,7 +482,7 @@ #define DDRSS_PI_43_DATA 0x00000000 #define DDRSS_PI_44_DATA 0x00000000 #define DDRSS_PI_45_DATA 0x00010100 -#define DDRSS_PI_46_DATA 0x00000014 +#define DDRSS_PI_46_DATA 0x00000015 #define DDRSS_PI_47_DATA 0x000007D0 #define DDRSS_PI_48_DATA 0x00000300 #define DDRSS_PI_49_DATA 0x00000000 @@ -602,8 +601,8 @@ #define DDRSS_PI_162_DATA 0x00000000 #define DDRSS_PI_163_DATA 0x00000000 #define DDRSS_PI_164_DATA 0x00000800 -#define DDRSS_PI_165_DATA 0x00640064 -#define DDRSS_PI_166_DATA 0x000E0E01 +#define DDRSS_PI_165_DATA 0x00780078 +#define DDRSS_PI_166_DATA 0x00101001 #define DDRSS_PI_167_DATA 0x00000034 #define DDRSS_PI_168_DATA 0x00000042 #define DDRSS_PI_169_DATA 0x00020042 @@ -614,84 +613,84 @@ #define DDRSS_PI_174_DATA 0x001C0000 #define DDRSS_PI_175_DATA 0x00000013 #define DDRSS_PI_176_DATA 0x000000BB -#define DDRSS_PI_177_DATA 0x000000FE -#define DDRSS_PI_178_DATA 0x00000A20 -#define DDRSS_PI_179_DATA 0x000000FE -#define DDRSS_PI_180_DATA 0x04000A20 +#define DDRSS_PI_177_DATA 0x00000130 +#define DDRSS_PI_178_DATA 0x00000C28 +#define DDRSS_PI_179_DATA 0x00000130 +#define DDRSS_PI_180_DATA 0x04000C28 #define DDRSS_PI_181_DATA 0x01010404 #define DDRSS_PI_182_DATA 0x00001501 -#define DDRSS_PI_183_DATA 0x001B001B +#define DDRSS_PI_183_DATA 0x001D001D #define DDRSS_PI_184_DATA 0x01000100 #define DDRSS_PI_185_DATA 0x00000100 #define DDRSS_PI_186_DATA 0x00000000 #define DDRSS_PI_187_DATA 0x05050503 -#define DDRSS_PI_188_DATA 0x01010B0B +#define DDRSS_PI_188_DATA 0x01010C0C #define DDRSS_PI_189_DATA 0x01010101 #define DDRSS_PI_190_DATA 0x000C0C0A #define DDRSS_PI_191_DATA 0x00000000 #define DDRSS_PI_192_DATA 0x00000000 #define DDRSS_PI_193_DATA 0x04000000 -#define DDRSS_PI_194_DATA 0x04020909 +#define DDRSS_PI_194_DATA 0x04020808 #define DDRSS_PI_195_DATA 0x04040204 #define DDRSS_PI_196_DATA 0x00090031 -#define DDRSS_PI_197_DATA 0x000F0037 -#define DDRSS_PI_198_DATA 0x000F0037 +#define DDRSS_PI_197_DATA 0x00110039 +#define DDRSS_PI_198_DATA 0x00110039 #define DDRSS_PI_199_DATA 0x01010101 -#define DDRSS_PI_200_DATA 0x0001000D -#define DDRSS_PI_201_DATA 0x000100A7 -#define DDRSS_PI_202_DATA 0x010000A7 +#define DDRSS_PI_200_DATA 0x0002000D +#define DDRSS_PI_201_DATA 0x000200C8 +#define DDRSS_PI_202_DATA 0x010000C8 #define DDRSS_PI_203_DATA 0x000E000E -#define DDRSS_PI_204_DATA 0x00A80100 -#define DDRSS_PI_205_DATA 0x010000A8 -#define DDRSS_PI_206_DATA 0x00A800A8 +#define DDRSS_PI_204_DATA 0x00C90100 +#define DDRSS_PI_205_DATA 0x010000C9 +#define DDRSS_PI_206_DATA 0x00C900C9 #define DDRSS_PI_207_DATA 0x32103200 #define DDRSS_PI_208_DATA 0x01013210 #define DDRSS_PI_209_DATA 0x0A070601 -#define DDRSS_PI_210_DATA 0x0B08070D -#define DDRSS_PI_211_DATA 0x0B08070D +#define DDRSS_PI_210_DATA 0x0D09070D +#define DDRSS_PI_211_DATA 0x0D09070D #define DDRSS_PI_212_DATA 0x000C000D #define DDRSS_PI_213_DATA 0x00001000 #define DDRSS_PI_214_DATA 0x00000C00 #define DDRSS_PI_215_DATA 0x00001000 #define DDRSS_PI_216_DATA 0x00000C00 #define DDRSS_PI_217_DATA 0x02001000 -#define DDRSS_PI_218_DATA 0x0015000D -#define DDRSS_PI_219_DATA 0x001500A7 -#define DDRSS_PI_220_DATA 0x000000A7 +#define DDRSS_PI_218_DATA 0x0016000D +#define DDRSS_PI_219_DATA 0x001600C8 +#define DDRSS_PI_220_DATA 0x000000C8 #define DDRSS_PI_221_DATA 0x00001900 #define DDRSS_PI_222_DATA 0x32000056 #define DDRSS_PI_223_DATA 0x06000101 #define DDRSS_PI_224_DATA 0x001D0204 -#define DDRSS_PI_225_DATA 0x32120059 +#define DDRSS_PI_225_DATA 0x32120058 #define DDRSS_PI_226_DATA 0x05000101 -#define DDRSS_PI_227_DATA 0x001D0409 -#define DDRSS_PI_228_DATA 0x32120059 +#define DDRSS_PI_227_DATA 0x001D0408 +#define DDRSS_PI_228_DATA 0x32120058 #define DDRSS_PI_229_DATA 0x05000101 -#define DDRSS_PI_230_DATA 0x00000409 +#define DDRSS_PI_230_DATA 0x00000408 #define DDRSS_PI_231_DATA 0x05030900 #define DDRSS_PI_232_DATA 0x00040900 #define DDRSS_PI_233_DATA 0x0000062B #define DDRSS_PI_234_DATA 0x20010004 #define DDRSS_PI_235_DATA 0x0A0A0A03 -#define DDRSS_PI_236_DATA 0x0E090000 -#define DDRSS_PI_237_DATA 0x0E09000D -#define DDRSS_PI_238_DATA 0x00005244 -#define DDRSS_PI_239_DATA 0x2003001D -#define DDRSS_PI_240_DATA 0x0A0A0A0A -#define DDRSS_PI_241_DATA 0x0E090000 -#define DDRSS_PI_242_DATA 0x0E09000D -#define DDRSS_PI_243_DATA 0x00005244 -#define DDRSS_PI_244_DATA 0x2003001D -#define DDRSS_PI_245_DATA 0x0A0A0A0A +#define DDRSS_PI_236_DATA 0x11090000 +#define DDRSS_PI_237_DATA 0x1009000F +#define DDRSS_PI_238_DATA 0x000062B8 +#define DDRSS_PI_239_DATA 0x20030023 +#define DDRSS_PI_240_DATA 0x0C0A0C0C +#define DDRSS_PI_241_DATA 0x11090000 +#define DDRSS_PI_242_DATA 0x1009000F +#define DDRSS_PI_243_DATA 0x000062B8 +#define DDRSS_PI_244_DATA 0x20030023 +#define DDRSS_PI_245_DATA 0x0C0A0C0C #define DDRSS_PI_246_DATA 0x00000000 #define DDRSS_PI_247_DATA 0x00000176 #define DDRSS_PI_248_DATA 0x00000E9C -#define DDRSS_PI_249_DATA 0x00001440 -#define DDRSS_PI_250_DATA 0x0000CA80 -#define DDRSS_PI_251_DATA 0x00001440 -#define DDRSS_PI_252_DATA 0x0000CA80 -#define DDRSS_PI_253_DATA 0x01030014 -#define DDRSS_PI_254_DATA 0x03030103 +#define DDRSS_PI_249_DATA 0x00001850 +#define DDRSS_PI_250_DATA 0x0000F320 +#define DDRSS_PI_251_DATA 0x00001850 +#define DDRSS_PI_252_DATA 0x0000F320 +#define DDRSS_PI_253_DATA 0x01360014 +#define DDRSS_PI_254_DATA 0x03030136 #define DDRSS_PI_255_DATA 0x00000003 #define DDRSS_PI_256_DATA 0x00000000 #define DDRSS_PI_257_DATA 0x05030503 @@ -701,23 +700,23 @@ #define DDRSS_PI_261_DATA 0x00000005 #define DDRSS_PI_262_DATA 0x00000064 #define DDRSS_PI_263_DATA 0x00000014 -#define DDRSS_PI_264_DATA 0x000208D6 +#define DDRSS_PI_264_DATA 0x00027100 #define DDRSS_PI_265_DATA 0x000186A0 #define DDRSS_PI_266_DATA 0x00000005 -#define DDRSS_PI_267_DATA 0x00000536 -#define DDRSS_PI_268_DATA 0x00000103 -#define DDRSS_PI_269_DATA 0x000208D6 +#define DDRSS_PI_267_DATA 0x00000640 +#define DDRSS_PI_268_DATA 0x00000136 +#define DDRSS_PI_269_DATA 0x00027100 #define DDRSS_PI_270_DATA 0x000186A0 #define DDRSS_PI_271_DATA 0x00000005 -#define DDRSS_PI_272_DATA 0x00000536 -#define DDRSS_PI_273_DATA 0x01000103 +#define DDRSS_PI_272_DATA 0x00000640 +#define DDRSS_PI_273_DATA 0x01000136 #define DDRSS_PI_274_DATA 0x00320040 #define DDRSS_PI_275_DATA 0x00010008 -#define DDRSS_PI_276_DATA 0x029B0040 -#define DDRSS_PI_277_DATA 0x00010014 -#define DDRSS_PI_278_DATA 0x029B0040 -#define DDRSS_PI_279_DATA 0x00000314 -#define DDRSS_PI_280_DATA 0x00280021 +#define DDRSS_PI_276_DATA 0x03200040 +#define DDRSS_PI_277_DATA 0x00010018 +#define DDRSS_PI_278_DATA 0x03200040 +#define DDRSS_PI_279_DATA 0x00000318 +#define DDRSS_PI_280_DATA 0x00280028 #define DDRSS_PI_281_DATA 0x03040404 #define DDRSS_PI_282_DATA 0x00000303 #define DDRSS_PI_283_DATA 0x02020101 @@ -745,7 +744,7 @@ #define DDRSS_PI_305_DATA 0x00000000 #define DDRSS_PI_306_DATA 0x00000024 #define DDRSS_PI_307_DATA 0x00000012 -#define DDRSS_PI_308_DATA 0x00000031 +#define DDRSS_PI_308_DATA 0x000000B1 #define DDRSS_PI_309_DATA 0x00000000 #define DDRSS_PI_310_DATA 0x00000000 #define DDRSS_PI_311_DATA 0x46000000 @@ -753,7 +752,7 @@ #define DDRSS_PI_313_DATA 0x00000000 #define DDRSS_PI_314_DATA 0x00000024 #define DDRSS_PI_315_DATA 0x00000012 -#define DDRSS_PI_316_DATA 0x00000031 +#define DDRSS_PI_316_DATA 0x000000B1 #define DDRSS_PI_317_DATA 0x00000000 #define DDRSS_PI_318_DATA 0x00000000 #define DDRSS_PI_319_DATA 0x46000000 @@ -769,7 +768,7 @@ #define DDRSS_PI_329_DATA 0x00000000 #define DDRSS_PI_330_DATA 0x00000024 #define DDRSS_PI_331_DATA 0x00000012 -#define DDRSS_PI_332_DATA 0x00000031 +#define DDRSS_PI_332_DATA 0x000000B1 #define DDRSS_PI_333_DATA 0x00000000 #define DDRSS_PI_334_DATA 0x00000000 #define DDRSS_PI_335_DATA 0x46000000 @@ -777,7 +776,7 @@ #define DDRSS_PI_337_DATA 0x00000000 #define DDRSS_PI_338_DATA 0x00000024 #define DDRSS_PI_339_DATA 0x00000012 -#define DDRSS_PI_340_DATA 0x00000031 +#define DDRSS_PI_340_DATA 0x000000B1 #define DDRSS_PI_341_DATA 0x00000000 #define DDRSS_PI_342_DATA 0x00000000 #define DDRSS_PI_343_DATA 0x46000000 @@ -869,29 +868,29 @@ #define DDRSS_PHY_84_DATA 0x00100010 #define DDRSS_PHY_85_DATA 0x00100010 #define DDRSS_PHY_86_DATA 0x00100010 -#define DDRSS_PHY_87_DATA 0x02000010 +#define DDRSS_PHY_87_DATA 0x02020010 #define DDRSS_PHY_88_DATA 0x51516041 #define DDRSS_PHY_89_DATA 0x31C06000 #define DDRSS_PHY_90_DATA 0x07AB0340 #define DDRSS_PHY_91_DATA 0x0000C0C0 -#define DDRSS_PHY_92_DATA 0x03040000 -#define DDRSS_PHY_93_DATA 0x00000403 +#define DDRSS_PHY_92_DATA 0x04050000 +#define DDRSS_PHY_93_DATA 0x00000504 #define DDRSS_PHY_94_DATA 0x42100010 #define DDRSS_PHY_95_DATA 0x010C053E -#define DDRSS_PHY_96_DATA 0x000F0C1A +#define DDRSS_PHY_96_DATA 0x000F0C1D #define DDRSS_PHY_97_DATA 0x01000140 -#define DDRSS_PHY_98_DATA 0x00660120 +#define DDRSS_PHY_98_DATA 0x007A0120 #define DDRSS_PHY_99_DATA 0x00000C00 -#define DDRSS_PHY_100_DATA 0x000001AA +#define DDRSS_PHY_100_DATA 0x000001CC #define DDRSS_PHY_101_DATA 0x20100200 -#define DDRSS_PHY_102_DATA 0x00000004 +#define DDRSS_PHY_102_DATA 0x00000005 #define DDRSS_PHY_103_DATA 0x76543210 #define DDRSS_PHY_104_DATA 0x00000008 -#define DDRSS_PHY_105_DATA 0x032A032A -#define DDRSS_PHY_106_DATA 0x032A032A -#define DDRSS_PHY_107_DATA 0x032A032A -#define DDRSS_PHY_108_DATA 0x032A032A -#define DDRSS_PHY_109_DATA 0x0000032A +#define DDRSS_PHY_105_DATA 0x034C034C +#define DDRSS_PHY_106_DATA 0x034C034C +#define DDRSS_PHY_107_DATA 0x034C034C +#define DDRSS_PHY_108_DATA 0x034C034C +#define DDRSS_PHY_109_DATA 0x0000034C #define DDRSS_PHY_110_DATA 0x00008000 #define DDRSS_PHY_111_DATA 0x00800080 #define DDRSS_PHY_112_DATA 0x00800080 @@ -901,7 +900,7 @@ #define DDRSS_PHY_116_DATA 0x00800080 #define DDRSS_PHY_117_DATA 0x00800080 #define DDRSS_PHY_118_DATA 0x00800080 -#define DDRSS_PHY_119_DATA 0x01190080 +#define DDRSS_PHY_119_DATA 0x01800080 #define DDRSS_PHY_120_DATA 0x01A00001 #define DDRSS_PHY_121_DATA 0x00000000 #define DDRSS_PHY_122_DATA 0x00000000 @@ -1125,29 +1124,29 @@ #define DDRSS_PHY_340_DATA 0x00100010 #define DDRSS_PHY_341_DATA 0x00100010 #define DDRSS_PHY_342_DATA 0x00100010 -#define DDRSS_PHY_343_DATA 0x02000010 +#define DDRSS_PHY_343_DATA 0x02020010 #define DDRSS_PHY_344_DATA 0x51516041 #define DDRSS_PHY_345_DATA 0x31C06000 #define DDRSS_PHY_346_DATA 0x07AB0340 #define DDRSS_PHY_347_DATA 0x0000C0C0 -#define DDRSS_PHY_348_DATA 0x03040000 -#define DDRSS_PHY_349_DATA 0x00000403 +#define DDRSS_PHY_348_DATA 0x04050000 +#define DDRSS_PHY_349_DATA 0x00000504 #define DDRSS_PHY_350_DATA 0x42100010 #define DDRSS_PHY_351_DATA 0x010C053E -#define DDRSS_PHY_352_DATA 0x000F0C1A +#define DDRSS_PHY_352_DATA 0x000F0C1D #define DDRSS_PHY_353_DATA 0x01000140 -#define DDRSS_PHY_354_DATA 0x00660120 +#define DDRSS_PHY_354_DATA 0x007A0120 #define DDRSS_PHY_355_DATA 0x00000C00 -#define DDRSS_PHY_356_DATA 0x000001AA +#define DDRSS_PHY_356_DATA 0x000001CC #define DDRSS_PHY_357_DATA 0x20100200 -#define DDRSS_PHY_358_DATA 0x00000004 +#define DDRSS_PHY_358_DATA 0x00000005 #define DDRSS_PHY_359_DATA 0x76543210 #define DDRSS_PHY_360_DATA 0x00000008 -#define DDRSS_PHY_361_DATA 0x032A032A -#define DDRSS_PHY_362_DATA 0x032A032A -#define DDRSS_PHY_363_DATA 0x032A032A -#define DDRSS_PHY_364_DATA 0x032A032A -#define DDRSS_PHY_365_DATA 0x0000032A +#define DDRSS_PHY_361_DATA 0x034C034C +#define DDRSS_PHY_362_DATA 0x034C034C +#define DDRSS_PHY_363_DATA 0x034C034C +#define DDRSS_PHY_364_DATA 0x034C034C +#define DDRSS_PHY_365_DATA 0x0000034C #define DDRSS_PHY_366_DATA 0x00008000 #define DDRSS_PHY_367_DATA 0x00800080 #define DDRSS_PHY_368_DATA 0x00800080 @@ -1157,7 +1156,7 @@ #define DDRSS_PHY_372_DATA 0x00800080 #define DDRSS_PHY_373_DATA 0x00800080 #define DDRSS_PHY_374_DATA 0x00800080 -#define DDRSS_PHY_375_DATA 0x01190080 +#define DDRSS_PHY_375_DATA 0x01800080 #define DDRSS_PHY_376_DATA 0x01A00001 #define DDRSS_PHY_377_DATA 0x00000000 #define DDRSS_PHY_378_DATA 0x00000000 @@ -1326,7 +1325,7 @@ #define DDRSS_PHY_541_DATA 0x003F0000 #define DDRSS_PHY_542_DATA 0x000F013F #define DDRSS_PHY_543_DATA 0x0000000F -#define DDRSS_PHY_544_DATA 0x000002CC +#define DDRSS_PHY_544_DATA 0x020002CC #define DDRSS_PHY_545_DATA 0x00030000 #define DDRSS_PHY_546_DATA 0x00000300 #define DDRSS_PHY_547_DATA 0x00000300 @@ -1582,7 +1581,7 @@ #define DDRSS_PHY_797_DATA 0x00000000 #define DDRSS_PHY_798_DATA 0x000F0000 #define DDRSS_PHY_799_DATA 0x0000000F -#define DDRSS_PHY_800_DATA 0x000002CC +#define DDRSS_PHY_800_DATA 0x020002CC #define DDRSS_PHY_801_DATA 0x00030000 #define DDRSS_PHY_802_DATA 0x00000300 #define DDRSS_PHY_803_DATA 0x00000300 @@ -1838,7 +1837,7 @@ #define DDRSS_PHY_1053_DATA 0x10000000 #define DDRSS_PHY_1054_DATA 0x000F0000 #define DDRSS_PHY_1055_DATA 0x0000000F -#define DDRSS_PHY_1056_DATA 0x000002CC +#define DDRSS_PHY_1056_DATA 0x020002CC #define DDRSS_PHY_1057_DATA 0x00030000 #define DDRSS_PHY_1058_DATA 0x00000300 #define DDRSS_PHY_1059_DATA 0x00000300 @@ -2116,7 +2115,7 @@ #define DDRSS_PHY_1331_DATA 0x00004410 #define DDRSS_PHY_1332_DATA 0x00000000 #define DDRSS_PHY_1333_DATA 0x00000076 -#define DDRSS_PHY_1334_DATA 0x00010000 +#define DDRSS_PHY_1334_DATA 0x00000400 #define DDRSS_PHY_1335_DATA 0x00000008 #define DDRSS_PHY_1336_DATA 0x00000000 #define DDRSS_PHY_1337_DATA 0x00000000 @@ -2154,7 +2153,7 @@ #define DDRSS_PHY_1369_DATA 0x00000000 #define DDRSS_PHY_1370_DATA 0x00000000 #define DDRSS_PHY_1371_DATA 0x0001F7C0 -#define DDRSS_PHY_1372_DATA 0x00000002 +#define DDRSS_PHY_1372_DATA 0x00020002 #define DDRSS_PHY_1373_DATA 0x00000000 #define DDRSS_PHY_1374_DATA 0x00001142 #define DDRSS_PHY_1375_DATA 0x03020000 @@ -2187,4 +2186,4 @@ #define DDRSS_PHY_1402_DATA 0x019900E0 #define DDRSS_PHY_1403_DATA 0x00018011 #define DDRSS_PHY_1404_DATA 0x0089FF00 -#define DDRSS_PHY_1405_DATA 0x20040001 +#define DDRSS_PHY_1405_DATA 0x20040004 diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts index cf3ba0e209..97f44e220a 100644 --- a/arch/arm/dts/k3-am642-r5-sk.dts +++ b/arch/arm/dts/k3-am642-r5-sk.dts @@ -9,7 +9,7 @@ #include <dt-bindings/phy/phy.h> #include <dt-bindings/net/ti-dp83867.h> #include "k3-am642.dtsi" -#include "k3-am64-sk-lp4-1333MTs.dtsi" +#include "k3-am64-sk-lp4-1600MTs.dtsi" #include "k3-am64-ddr.dtsi" / { -- 2.34.1

2 3

[PATCH V2] dt-bindings: nvmem: u-boot, env: add Broadcom's variant binding
by Rafał Miłecki 18 Oct '22

18 Oct '22

From: Rafał Miłecki <rafal(a)milecki.pl> Broadcom uses U-Boot for a lot of their bcmbca familiy chipsets. U-Boot stores its configuration in an environment data block. Such blocks are usually stored on flash as a separated partition at hardcoded address. Broadcom however decided to: 1. Store env data block inside U-Boot partition 2. Avoid sticking to hardcoded offsets 3. Use custom header with "uEnv" magic and env data length Example (length 0x4000): $ hexdump -n 32 -C -s 0x40000 /dev/mtdblock0 00040000 76 6e 45 75 00 40 00 00 34 89 7a 82 49 4d 41 47 |vnEu.@..4.z.IMAG| 00040010 45 3d 4e 41 4e 44 3a 31 4d 2c 31 30 32 34 4d 00 |E=NAND:1M,1024M.| (0x40000 offset is unit specific and can change) Starting with the commit 118f3fbe517f4 ("dt-bindings: mtd: partitions: support label/name only partition") DT can describe partitions matching them by a name (without specifying actual address). With that feature and this binding change it's possible to: 1. Specify DT node for Broadcom's U-Boot env data subpartition 2. Add nodes for specific environment data variables 3. Reference them as NVMEM cells This binding is unlikely to help Broadcom's U-Boot. U-Boot SPL needs to find environment data early (before it accesses DTB) and it does that by looking for an "uEnv" magic. Dirty way. This binding can however be used by operating systems. It allows describing cleanly U-Boot, its env data and variables. It tells operating system about Broadcom-specific env data so it can parse it. Signed-off-by: Rafał Miłecki <rafal(a)milecki.pl> --- V2: Work on better commit body & add example --- .../devicetree/bindings/nvmem/u-boot,env.yaml | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/nvmem/u-boot,env.yaml b/Documentation/devicetree/bindings/nvmem/u-boot,env.yaml index e96bca99f2d9..987957e3ffc8 100644 --- a/Documentation/devicetree/bindings/nvmem/u-boot,env.yaml +++ b/Documentation/devicetree/bindings/nvmem/u-boot,env.yaml @@ -38,6 +38,8 @@ properties: const: u-boot,env-redundant-bool - description: Two redundant blocks with active having higher counter const: u-boot,env-redundant-count + - description: Broadcom's variant with custom header + const: brcm,env reg: maxItems: 1 @@ -73,3 +75,22 @@ examples: }; }; }; + - | + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x100000>; + compatible = "brcm,u-boot"; + label = "u-boot"; + + partition-u-boot-env { + compatible = "brcm,env"; + + mac: ethaddr { + }; + }; + }; + }; -- 2.34.1

3 6

[PATCH] ARM: dts: stm32: Add DHCOR based Testbench board
by Marek Vasut 18 Oct '22

18 Oct '22

Add DT for DHCOR Testbench board, which is a testbench for testing of DHCOR SoM during manufacturing. This is effectively a trimmed down version of AV96 board with CSI-2 bridge, HDMI bridge, WiFi, Audio and LEDs removed and used as GPIOs instead. Furthermore, the PMIC Buck3 is always configured from PMIC NVM to cater for both 1V8 and 3V3 SoM variant. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/dts/Makefile | 3 +- .../stm32mp15xx-dhcor-testbench-u-boot.dtsi | 100 ++++++++++ arch/arm/dts/stm32mp15xx-dhcor-testbench.dts | 178 ++++++++++++++++++ board/dhelectronics/dh_stm32mp1/board.c | 40 ++-- .../dh_stm32mp1/u-boot-dhcor.its | 21 ++- 5 files changed, 325 insertions(+), 17 deletions(-) create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp15xx-dhcor-testbench.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 965895bc2a3..4a2c0de74a0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1201,7 +1201,8 @@ dtb-$(CONFIG_STM32MP15x) += \ stm32mp15xx-dhcom-pdk2.dtb \ stm32mp15xx-dhcom-picoitx.dtb \ stm32mp15xx-dhcor-avenger96.dtb \ - stm32mp15xx-dhcor-drc-compact.dtb + stm32mp15xx-dhcor-drc-compact.dtb \ + stm32mp15xx-dhcor-testbench.dtb dtb-$(CONFIG_SOC_K3_AM654) += \ k3-am654-base-board.dtb \ diff --git a/arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi new file mode 100644 index 00000000000..5b051b8ac45 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor-testbench-u-boot.dtsi @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2022 Marek Vasut <marex(a)denx.de> + */ + +#include "stm32mp15xx-dhcor-u-boot.dtsi" + +/ { + aliases { + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + usb0 = &usbotg_hs; + }; + + config { + dh,board-coding-gpios = <&gpiog 13 0>, <&gpiod 9 0>; + }; +}; + +&ethernet0 { + phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + + mdio0 { + ethernet-phy@7 { + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <1000>; + }; + }; +}; + +&sdmmc1 { + u-boot,dm-spl; + st,use-ckin; + st,cmd-gpios = <&gpiod 2 0>; + st,ck-gpios = <&gpioc 12 0>; + st,ckin-gpios = <&gpioe 4 0>; +}; + +&sdmmc1_b4_pins_a { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&sdmmc1_dir_pins_b { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&sdmmc2 { + u-boot,dm-spl; +}; + +&sdmmc2_b4_pins_a { + u-boot,dm-spl; + pins1 { + u-boot,dm-spl; + }; + pins2 { + u-boot,dm-spl; + }; +}; + +&sdmmc2_d47_pins_c { + u-boot,dm-spl; + pins { + u-boot,dm-spl; + }; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; + +&uart4_pins_b { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + /delete-property/ bias-disable; + bias-pull-up; + }; +}; + +&usbotg_hs { + u-boot,force-b-session-valid; + hnp-srp-disable; +}; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts new file mode 100644 index 00000000000..c9163e1c028 --- /dev/null +++ b/arch/arm/dts/stm32mp15xx-dhcor-testbench.dts @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) 2022 Marek Vasut <marex(a)denx.de> + */ +/dts-v1/; + +#include "stm32mp151.dtsi" +#include "stm32mp15xx-dhcor-som.dtsi" + +/ { + model = "DH electronics STM32MP15xx DHCOR Testbench"; + compatible = "dh,stm32mp15xx-dhcor-testbench", "st,stm32mp1xx"; + + aliases { + ethernet0 = &ethernet0; + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + serial0 = &uart4; + serial1 = &uart7; + spi0 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + sd_switch: regulator-sd_switch { + compatible = "regulator-gpio"; + regulator-name = "sd_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2900000>; + regulator-type = "voltage"; + regulator-always-on; + + gpios = <&gpioi 5 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + states = <1800000 0x1>, + <2900000 0x0>; + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc12_ain_pins_b>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + + adc1: adc@0 { + st,adc-channels = <0 1 6>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; + + adc2: adc@100 { + st,adc-channels = <0 1 2>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; +}; + +&ethernet0 { + status = "okay"; + pinctrl-0 = <&ethernet0_rgmii_pins_c>; + pinctrl-1 = <&ethernet0_rgmii_sleep_pins_c>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + + phy0: ethernet-phy@7 { + reg = <7>; + + rxc-skew-ps = <1500>; + rxdv-skew-ps = <540>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + + txc-skew-ps = <1440>; + txen-skew-ps = <540>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <420>; + txd3-skew-ps = <420>; + }; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_b>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_b>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_b>; + cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,sig-dir; + st,neg-edge; + st,use-ckin; + bus-width = <4>; + vmmc-supply = <&vdd_sd>; + vqmmc-supply = <&sd_switch>; + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; + bus-width = <8>; + mmc-ddr-1_8v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + status = "okay"; +}; + +&usbotg_hs { + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + status = "okay"; + vbus-supply = <&vbus_otg>; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; + +&vdd { + /delete-property/ regulator-always-on; + regulator-min-microvolt = <1200000>; +}; diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index b0284609183..a5afc64024c 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -547,7 +547,7 @@ static int board_get_regulator_buck3_nvm_uv_av96(int *uv) if (!prop || !len) return -ENODEV; - if (!strstr(prop, "avenger96")) + if (!strstr(prop, "avenger96") && !strstr(prop, "dhcor-testbench")) return -EINVAL; /* Read out STPMIC1 NVM and determine default Buck3 voltage. */ @@ -564,18 +564,32 @@ static int board_get_regulator_buck3_nvm_uv_av96(int *uv) bucks_vout >>= STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_OFFSET(3); bucks_vout &= STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_MASK; - /* - * Avenger96 board comes in multiple regulator configurations: - * - rev.100 or rev.200 have Buck3 preconfigured to 3V3 operation on - * boot and contains extra Enpirion EP53A8LQI DCDC converter which - * supplies the IO. Reduce Buck3 voltage to 2V9 to not waste power. - * - rev.200L have Buck3 preconfigured to 1V8 operation and have no - * Enpirion EP53A8LQI DCDC anymore, the IO is supplied from Buck3. - */ - if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V3) - *uv = 2900000; - else - *uv = 1800000; + if (strstr(prop, "avenger96")) { + /* + * Avenger96 board comes in multiple regulator configurations: + * - rev.100 or rev.200 have Buck3 preconfigured to + * 3V3 operation on boot and contains extra Enpirion + * EP53A8LQI DCDC converter which supplies the IO. + * Reduce Buck3 voltage to 2V9 to not waste power. + * - rev.200L have Buck3 preconfigured to 1V8 operation + * and have no Enpirion EP53A8LQI DCDC anymore, the + * IO is supplied from Buck3. + */ + if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V3) + *uv = 2900000; + else + *uv = 1800000; + } else { + /* Testbench always respects Buck3 NVM settings */ + if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V3) + *uv = 3300000; + else if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_3V0) + *uv = 3000000; + else if (bucks_vout == STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_1V8) + *uv = 1800000; + else /* STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_1V2 */ + *uv = 1200000; + } return 0; } diff --git a/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its b/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its index de7dcb317f3..f9c1075616b 100644 --- a/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its +++ b/board/dhelectronics/dh_stm32mp1/u-boot-dhcor.its @@ -18,13 +18,21 @@ fdt-1 { description = ".dtb"; - data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtb"); + data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-testbench.dtb"); type = "flat_dt"; arch = "arm"; compression = "none"; }; fdt-2 { + description = ".dtb"; + data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtb"); + type = "flat_dt"; + arch = "arm"; + compression = "none"; + }; + + fdt-3 { description = ".dtb"; data = /incbin/("arch/arm/dts/stm32mp15xx-dhcor-drc-compact.dtb"); type = "flat_dt"; @@ -38,18 +46,25 @@ config-1 { /* DT+SoM+board model */ - description = "arrow,stm32mp15xx-avenger96_somrev0_boardrev1"; + description = "dh,stm32mp15xx-dhcor-testbench_somrev0_boardrev1"; firmware = "uboot"; fdt = "fdt-1"; }; config-2 { /* DT+SoM+board model */ - description = "dh,stm32mp15xx-dhcor-drc-compact_somrev0_boardrev0"; + description = "arrow,stm32mp15xx-avenger96_somrev0_boardrev1"; firmware = "uboot"; fdt = "fdt-2"; }; + config-3 { + /* DT+SoM+board model */ + description = "dh,stm32mp15xx-dhcor-drc-compact_somrev0_boardrev0"; + firmware = "uboot"; + fdt = "fdt-3"; + }; + /* Add 586-200..586-400 with fdt-2..fdt-4 here */ }; }; -- 2.35.1

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[PATCH] ARM: dts: stm32: Drop extra newline from AV96 U-Boot extras DT
by Marek Vasut 18 Oct '22

18 Oct '22

Remove duplicate newline, no functional change. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi index b6fceb9ad58..6dee51dc1c2 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96-u-boot.dtsi @@ -19,7 +19,6 @@ }; }; - &ethernet0 { phy-reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; -- 2.35.1

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