July 2022 - U-Boot

[PATCH 1/2] spi: fsl_qspi: Add support for i.MX7ULP
by Ye Li 09 Nov '22

09 Nov '22

Add compatible string and driver data for i.MX7ULP. Meanwhile, the address set to SFA1AD/SFA2AD/SFB1AD/SFB2AD should align with 1KB, because the lowest 10 bits are reserved by the registers definition. For i.MX7ULP which has only 128Bytes AHB buffer, must align it when setting the registers and selecting cs. Signed-off-by: Ye Li <ye.li(a)nxp.com> Reviewed-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> Reviewed-by: Kuldeep Singh <kuldeep.singh(a)nxp.com> --- drivers/spi/fsl_qspi.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index e715f98..d9f531a 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -231,6 +231,15 @@ static const struct fsl_qspi_devtype_data imx6ul_data = { .little_endian = true, }; +static const struct fsl_qspi_devtype_data imx7ulp_data = { + .rxfifo = SZ_64, + .txfifo = SZ_64, + .ahb_buf_size = SZ_128, + .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK | + QUADSPI_QUIRK_USE_TDH_SETTING, + .little_endian = true, +}; + static const struct fsl_qspi_devtype_data ls1021a_data = { .rxfifo = SZ_128, .txfifo = SZ_64, @@ -485,7 +494,7 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave) static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op) { memcpy_fromio(op->data.buf.in, - q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size, + q->ahb_addr + q->selected * ALIGN(q->devtype_data->ahb_buf_size, 0x400), op->data.nbytes); } @@ -589,7 +598,7 @@ static int fsl_qspi_exec_op(struct spi_slave *slave, addr_offset = q->memmap_phy; qspi_writel(q, - q->selected * q->devtype_data->ahb_buf_size + addr_offset, + q->selected * ALIGN(q->devtype_data->ahb_buf_size, 0x400) + addr_offset, base + QUADSPI_SFAR); qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) | @@ -695,13 +704,13 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q) * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD, * SFB2AD accordingly. */ - qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset, + qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) + addr_offset, base + QUADSPI_SFA1AD); - qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset, + qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) * 2 + addr_offset, base + QUADSPI_SFA2AD); - qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset, + qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) * 3 + addr_offset, base + QUADSPI_SFB1AD); - qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset, + qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) * 4 + addr_offset, base + QUADSPI_SFB2AD); q->selected = -1; @@ -799,6 +808,7 @@ static const struct udevice_id fsl_qspi_ids[] = { { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data, }, { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_data, }, { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, }, + { .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data, }, { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, }, { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, }, { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, }, -- 2.7.4

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[PATCH v1] spi: nuvoton: add NPCM PSPI controller driver
by Jim Liu 27 Oct '22

27 Oct '22

Add Nuvoton NPCM BMC Peripheral SPI controller driver. NPCM750 include two general-purpose SPI interface. Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> --- drivers/spi/Kconfig | 5 + drivers/spi/Makefile | 1 + drivers/spi/npcm_pspi.c | 226 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 232 insertions(+) create mode 100644 drivers/spi/npcm_pspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a1e515cb2b..4e4e05f849 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -289,6 +289,11 @@ config NPCM_FIU_SPI This enables support for the Flash Interface Unit SPI controller in master mode. +config NPCM_PSPI + bool "PSPI driver for Nuvoton NPCM SoC" + help + PSPI driver for NPCM SoC + config NXP_FSPI bool "NXP FlexSPI driver" depends on SPI_MEM diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 06e81b465b..1b843636bc 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_NPCM_FIU_SPI) += npcm_fiu_spi.o +obj-$(CONFIG_NPCM_PSPI) += npcm_pspi.o obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o diff --git a/drivers/spi/npcm_pspi.c b/drivers/spi/npcm_pspi.c new file mode 100644 index 0000000000..bd9ac65411 --- /dev/null +++ b/drivers/spi/npcm_pspi.c @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Nuvoton Technology. + */ + +#include <common.h> +#include <dm.h> +#include <spi.h> +#include <clk.h> +#include <asm/gpio.h> +#include <linux/iopoll.h> + +#define MAX_DIV 127 + +/* Register offsets */ +#define PSPI_DATA 0 +#define PSPI_CTL1 2 +#define PSPI_STAT 4 + +/* PSPI_CTL1 fields */ +#define PSPI_CTL1_SPIEN BIT(0) +#define PSPI_CTL1_SCM BIT(7) +#define PSPI_CTL1_SCIDL BIT(8) +#define PSPI_CTL1_SCDV_MASK GENMASK(15, 9) +#define PSPI_CTL1_SCDV_SHIFT 9 + +/* PSPI_STAT fields */ +#define PSPI_STAT_BSY BIT(0) +#define PSPI_STAT_RBF BIT(1) + +struct npcm_pspi_priv { + void __iomem *base; + struct clk clk; + struct gpio_desc cs_gpio; + u32 max_hz; +}; + +static inline void spi_cs_activate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct npcm_pspi_priv *priv = dev_get_priv(bus); + + dm_gpio_set_value(&priv->cs_gpio, 0); +} + +static inline void spi_cs_deactivate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct npcm_pspi_priv *priv = dev_get_priv(bus); + + dm_gpio_set_value(&priv->cs_gpio, 1); +} + +static inline void npcm_pspi_enable(struct npcm_pspi_priv *priv) +{ + u16 val; + + val = readw(priv->base + PSPI_CTL1); + val |= PSPI_CTL1_SPIEN; + writew(val, priv->base + PSPI_CTL1); +} + +static inline void npcm_pspi_disable(struct npcm_pspi_priv *priv) +{ + u16 val; + + val = readw(priv->base + PSPI_CTL1); + val &= ~PSPI_CTL1_SPIEN; + writew(val, priv->base + PSPI_CTL1); +} + +static int npcm_pspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct npcm_pspi_priv *priv = dev_get_priv(bus); + void __iomem *base = priv->base; + const u8 *tx = dout; + u8 *rx = din; + u32 bytes = bitlen / 8; + u8 tmp; + u32 val; + int i, ret = 0; + + npcm_pspi_enable(priv); + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(dev); + + for (i = 0; i < bytes; i++) { + /* Making sure we can write */ + ret = readb_poll_timeout(base + PSPI_STAT, val, + !(val & PSPI_STAT_BSY), + 1000000); + if (ret < 0) + break; + + if (tx) + writeb(*tx++, base + PSPI_DATA); + else + writeb(0, base + PSPI_DATA); + + /* Wait till write completed */ + ret = readb_poll_timeout(base + PSPI_STAT, val, + !(val & PSPI_STAT_BSY), + 1000000); + if (ret < 0) + break; + + /* Wait till read buffer full */ + ret = readb_poll_timeout(base + PSPI_STAT, val, + (val & PSPI_STAT_RBF), + 1000000); + if (ret < 0) + break; + + tmp = readb(base + PSPI_DATA); + if (rx) + *rx++ = tmp; + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(dev); + + npcm_pspi_disable(priv); + + return ret; +} + +static int npcm_pspi_set_speed(struct udevice *bus, uint speed) +{ + struct npcm_pspi_priv *priv = dev_get_priv(bus); + ulong apb_clock; + u32 divisor; + u16 val; + + apb_clock = clk_get_rate(&priv->clk); + if (!apb_clock) + return -EINVAL; + + if (speed > priv->max_hz) + speed = priv->max_hz; + + divisor = DIV_ROUND_CLOSEST(apb_clock, (2 * speed) - 1); + if (divisor > MAX_DIV) + divisor = MAX_DIV; + + val = readw(priv->base + PSPI_CTL1); + val &= ~PSPI_CTL1_SCDV_MASK; + val |= divisor << PSPI_CTL1_SCDV_SHIFT; + writew(val, priv->base + PSPI_CTL1); + + debug("%s: apb_clock=%lu speed=%d divisor=%u\n", + __func__, apb_clock, speed, divisor); + + return 0; +} + +static int npcm_pspi_set_mode(struct udevice *bus, uint mode) +{ + struct npcm_pspi_priv *priv = dev_get_priv(bus); + u16 pspi_mode, val; + + switch (mode & (SPI_CPOL | SPI_CPHA)) { + case SPI_MODE_0: + pspi_mode = 0; + break; + case SPI_MODE_1: + pspi_mode = PSPI_CTL1_SCM; + break; + case SPI_MODE_2: + pspi_mode = PSPI_CTL1_SCIDL; + break; + case SPI_MODE_3: + pspi_mode = PSPI_CTL1_SCIDL | PSPI_CTL1_SCM; + break; + default: + break; + } + + val = readw(priv->base + PSPI_CTL1); + val &= ~(PSPI_CTL1_SCIDL | PSPI_CTL1_SCM); + val |= pspi_mode; + writew(val, priv->base + PSPI_CTL1); + + return 0; +} + +static int npcm_pspi_probe(struct udevice *bus) +{ + struct npcm_pspi_priv *priv = dev_get_priv(bus); + int node = dev_of_offset(bus); + int ret; + + ret = clk_get_by_index(bus, 0, &priv->clk); + if (ret < 0) + return ret; + + priv->base = dev_read_addr_ptr(bus); + priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0); + gpio_request_by_name_nodev(offset_to_ofnode(node), "cs-gpios", 0, + &priv->cs_gpio, GPIOD_IS_OUT); + + return 0; +} + +static const struct dm_spi_ops npcm_pspi_ops = { + .xfer = npcm_pspi_xfer, + .set_speed = npcm_pspi_set_speed, + .set_mode = npcm_pspi_set_mode, +}; + +static const struct udevice_id npcm_pspi_ids[] = { + { .compatible = "nuvoton,npcm845-pspi"}, + { .compatible = "nuvoton,npcm750-pspi"}, + { } +}; + +U_BOOT_DRIVER(npcm_pspi) = { + .name = "npcm_pspi", + .id = UCLASS_SPI, + .of_match = npcm_pspi_ids, + .ops = &npcm_pspi_ops, + .priv_auto = sizeof(struct npcm_pspi_priv), + .probe = npcm_pspi_probe, +}; -- 2.17.1

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[PATCH] drivers: mmc: Reset watchdog when accessing mmc device
by qianfanguijin＠163.com 27 Oct '22

27 Oct '22

From: qianfan Zhao <qianfanguijin(a)163.com> watchdog will reset when 'mmc read' or 'ext4load' a large file from mmc device. Reset watchdog when accessing mmc device. Signed-off-by: qianfan Zhao <qianfanguijin(a)163.com> --- drivers/mmc/mmc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 4d9871d69f..27ffdb7fa7 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -24,6 +24,7 @@ #include <memalign.h> #include <linux/list.h> #include <div64.h> +#include <watchdog.h> #include "mmc_private.h" #define DEFAULT_CMD6_TIMEOUT_MS 500 @@ -297,6 +298,7 @@ int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms) if (timeout_ms-- <= 0) break; + WATCHDOG_RESET(); udelay(1000); } @@ -500,6 +502,8 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, blocks_todo -= cur; start += cur; dst += cur * mmc->read_bl_len; + + WATCHDOG_RESET(); } while (blocks_todo > 0); return blkcnt; -- 2.25.1

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[PATCH] crypto: hash: sw: fix Kconfig dependencies
by Benjamin Bara 26 Oct '22

26 Oct '22

From: Benjamin Bara <Benjamin.Bara(a)skidata.com> Fix SHA512 config name and add missing SHA384 config. Signed-off-by: Benjamin Bara <Benjamin.Bara(a)skidata.com> --- drivers/crypto/hash/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/hash/Kconfig b/drivers/crypto/hash/Kconfig index bf9540eca6..aa355c44be 100644 --- a/drivers/crypto/hash/Kconfig +++ b/drivers/crypto/hash/Kconfig @@ -10,7 +10,8 @@ config HASH_SOFTWARE depends on MD5 depends on SHA1 depends on SHA256 - depends on SHA512_ALGO + depends on SHA384 + depends on SHA512 help Enable driver for hashing operations in software. Currently it support multiple hash algorithm including CRC/MD5/SHA. -- 2.34.1

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[PATCH 0/3] Clarify standalone application support
by Paul Barker 26 Oct '22

26 Oct '22

While looking into the support for u-boot standalone applications I noticed that there was some mis-alignment between the license exception and the files which needed to be included to get a functioning application. I also noticed that the set of SPI access functions defined in the jump table was missing a key function and did not match the set of prototypes defined in the exports header. These patches should rectify the issues I found. Paul Barker (3): Licenses: Clarify exceptions for standalone apps examples: hello_world: Drop inclusion of common header exports: Fix export of SPI access functions Licenses/Exceptions | 12 ++++++++---- examples/standalone/hello_world.c | 1 - include/_exports.h | 4 ++++ include/exports.h | 15 ++++++++++++++- 4 files changed, 26 insertions(+), 6 deletions(-) -- 2.25.1

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[PATCH v3] imx: imx8qm: cgtqmx8: switch to binman
by Oliver Graute 25 Oct '22

25 Oct '22

Switch to use binman to pack images Signed-off-by: Oliver Graute <oliver.graute(a)kococonnector.com> Reviewed-by: Fabio Estevam <festevam(a)denx.de> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes for v3 -added Reviewed-by -rebased on master arch/arm/dts/imx8qm-cgtqmx8.dts | 1 + arch/arm/mach-imx/imx8/Kconfig | 1 + board/congatec/cgtqmx8/imximage.cfg | 4 ++-- configs/cgtqmx8_defconfig | 2 +- doc/board/congatec/cgtqmx8.rst | 3 +-- 5 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/imx8qm-cgtqmx8.dts b/arch/arm/dts/imx8qm-cgtqmx8.dts index 555c357f6f..919d00644f 100644 --- a/arch/arm/dts/imx8qm-cgtqmx8.dts +++ b/arch/arm/dts/imx8qm-cgtqmx8.dts @@ -12,6 +12,7 @@ /memreserve/ 0x80000000 0x00020000; #include "fsl-imx8qm.dtsi" +#include "imx8qm-u-boot.dtsi" / { model = "Congatec QMX8 Qseven series"; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 4414cbc213..3094524460 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -74,6 +74,7 @@ config TARGET_IMX8QM_MEK config TARGET_CONGA_QMX8 bool "Support congatec conga-QMX8 board" + select BINMAN select BOARD_LATE_INIT select SUPPORT_SPL select IMX8QM diff --git a/board/congatec/cgtqmx8/imximage.cfg b/board/congatec/cgtqmx8/imximage.cfg index 5ecde0c530..43035088e3 100644 --- a/board/congatec/cgtqmx8/imximage.cfg +++ b/board/congatec/cgtqmx8/imximage.cfg @@ -4,8 +4,8 @@ */ -/* Boot from SD, sector size 0x400 */ -BOOT_FROM SD 0x400 +BOOT_FROM sd + /* SoC type IMX8QM */ SOC_TYPE IMX8QM /* Append seco container image */ diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig index 2cf882f826..fb334bc4a4 100644 --- a/configs/cgtqmx8_defconfig +++ b/configs/cgtqmx8_defconfig @@ -21,7 +21,7 @@ CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y diff --git a/doc/board/congatec/cgtqmx8.rst b/doc/board/congatec/cgtqmx8.rst index bccdef2f16..16711a844d 100644 --- a/doc/board/congatec/cgtqmx8.rst +++ b/doc/board/congatec/cgtqmx8.rst @@ -57,8 +57,7 @@ Build U-Boot $ export ATF_LOAD_ADDR=0x80000000 $ export BL33_LOAD_ADDR=0x80020000 $ make cgtqmx8_defconfig - $ make u-boot.bin - $ make flash.bin + $ make Flash the binary into the SD card --------------------------------- -- 2.17.1

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[PATCH 0/7] arm: dts: Create common imx8mn-u-boot
by Adam Ford 24 Oct '22

24 Oct '22

Every imx8mn board has a bunch of similar entries on their respective board-u-boot.dtsi file to make the board bootable. Instead of maintaining multiple files with duplicate code, have them all point to a new, common file. This file includes the necessary nodes that were common to nearly all boards and added spba1 to help faciliate SPL_DM_SERIAL. This also adds support for CONFIG_FSPI_CONF_HEADER which can be used to generate flash.bin files for booting from FlexSPI. Adam Ford (7): arm: dts: imx8mn-u-boot: Create common imx8mn-u-boot.dtsi arm: dts: imx8mn-beacon-kit: Consolidate with imx8mn-u-boot arm: dts: imx8mn-bsh-smm-s2: Consolidate with imx8mn-u-boot arm: dts: imx8mn-ddr4-evk: Consolidate with imx8mn-u-boot arm: dts: imx8mn-evk: Consolidate with imx8mn-u-boot arm: dts: imx8mn-var-som-symphony: Consolidate with imx8mn-u-boot arm: dts: imx8mn-venice: Consolidate with imx8mn-u-boot arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi | 180 +------------ .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 172 +----------- arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 180 +------------ arch/arm/dts/imx8mn-evk-u-boot.dtsi | 108 -------- arch/arm/dts/imx8mn-u-boot.dtsi | 248 ++++++++++++++++++ .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 188 +------------ arch/arm/dts/imx8mn-venice-u-boot.dtsi | 188 +------------ 7 files changed, 254 insertions(+), 1010 deletions(-) create mode 100644 arch/arm/dts/imx8mn-u-boot.dtsi -- 2.34.1

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[PATCH v2] clk: update clk_clean_rate_cache to use private clk struct
by Patrick Delaunay 20 Oct '22

20 Oct '22

In clk_clean_rate_cache, clk->rate should update the private clock struct, in particular when CCF is activated, to save the cached rate value. When clk_get_parent_rate is called, the cached information is read from pclk->rate, with pclk = clk_get_parent(clk). As the cached is read from private clk data, the update should be done also on it. Fixes: 6b7fd3128f7 ("clk: fix set_rate to clean up cached rates for the hierarchy") Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- Changes in v2: - set *clkp = clk when CCF is not activated and when the clock is not found drivers/clk/clk-uclass.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index b89c77bf794..5cfa022a6dc 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -544,6 +544,19 @@ ulong clk_round_rate(struct clk *clk, ulong rate) return ops->round_rate(clk, rate); } +static void clk_get_priv(struct clk *clk, struct clk **clkp) +{ + *clkp = clk; + + /* get private clock struct associated to the provided clock */ + if (CONFIG_IS_ENABLED(CLK_CCF)) { + /* Take id 0 as a non-valid clk, such as dummy */ + if (clk->id) + clk_get_by_id(clk->id, clkp); + } +} + +/* clean cache, called with private clock struct */ static void clk_clean_rate_cache(struct clk *clk) { struct udevice *child_dev; @@ -563,6 +576,7 @@ static void clk_clean_rate_cache(struct clk *clk) ulong clk_set_rate(struct clk *clk, ulong rate) { const struct clk_ops *ops; + struct clk *clkp; debug("%s(clk=%p, rate=%lu)\n", __func__, clk, rate); if (!clk_valid(clk)) @@ -572,8 +586,10 @@ ulong clk_set_rate(struct clk *clk, ulong rate) if (!ops->set_rate) return -ENOSYS; + /* get private clock struct used for cache */ + clk_get_priv(clk, &clkp); /* Clean up cached rates for us and all child clocks */ - clk_clean_rate_cache(clk); + clk_clean_rate_cache(clkp); return ops->set_rate(clk, rate); } -- 2.25.1

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[PATCH v17 0/2] add TCP and HTTP for downloading images
by Ying-Chun Liu (PaulLiu) 19 Oct '22

19 Oct '22

From: "Ying-Chun Liu (PaulLiu)" <paul.liu(a)linaro.org> This patch is a refresh from previous patches made by Duncan Hare <DuncanCHare at yahoo.com>. I've contacted him and continue to work on this patch. This patch introduce a TCP stack with SACK. And a simple wget command to download images from http server. v1-v12: Made by Duncan, didn't tracked. v13: Fix some issues which is reviewed by Christian v14: Add options to enable/disable SACK. v15: Fix various syntax errors reviewed by Michal. Remove magic numbers. Use kernel-doc format. v16: Add more kernel-doc. Fix more double spaces. v17: Fix wget with address timeout issue reported by Ramon. Ying-Chun Liu (PaulLiu) (2): net: Add TCP protocol net: Add wget application cmd/Kconfig | 7 + cmd/net.c | 13 + include/net.h | 38 ++- include/net/tcp.h | 312 ++++++++++++++++++++ include/net/wget.h | 22 ++ net/Kconfig | 16 + net/Makefile | 2 + net/net.c | 36 +++ net/tcp.c | 720 +++++++++++++++++++++++++++++++++++++++++++++ net/wget.c | 428 +++++++++++++++++++++++++++ 10 files changed, 1584 insertions(+), 10 deletions(-) create mode 100644 include/net/tcp.h create mode 100644 include/net/wget.h create mode 100644 net/tcp.c create mode 100644 net/wget.c -- 2.35.1

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[REGRESSION]: v2022.07: SHA256 hash is broken on imx8m series with CAAM enabled
by ZHIZHIKIN Andrey 16 Oct '22

16 Oct '22

Hello Gaurav, In the new v2022.07, I've stumbled upon the issue with calculating the SHA256 of memory blocks with CAAM hashing. This causes the FIT image not to pass the hash validation, and also `sha256` command not operable. I'm also wondering if any i.MX8M-based board maintainers have seen the same issues at their end? I've made a small test executing the following command sequence (with corresponding serial output): U-Boot 2022.07 (Jul 15 2022 - 14:36:00 +0200) CPU: Freescale i.MX8MMQ rev1.0 at 1200 MHz Reset cause: POR Model: FSL i.MX8MM EVK board DRAM: 2 GiB Core: 153 devices, 19 uclasses, devicetree: separate WDT: Started watchdog@30280000 with servicing (60s timeout) MMC: FSL_SDHC: 1, FSL_SDHC: 2 Loading Environment from MMC... *** Warning - bad CRC, using default environment In: serial@30890000 Out: serial@30890000 Err: serial@30890000 SEC0: RNG instantiated Net: eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 u-boot=> mw.b ${kernel_addr_r} DE 100 u-boot=> md.b ${kernel_addr_r} 100 40480000: dededede dededede dededede dededede ................ 40480010: dededede dededede dededede dededede ................ 40480020: dededede dededede dededede dededede ................ 40480030: dededede dededede dededede dededede ................ 40480040: dededede dededede dededede dededede ................ 40480050: dededede dededede dededede dededede ................ 40480060: dededede dededede dededede dededede ................ 40480070: dededede dededede dededede dededede ................ 40480080: dededede dededede dededede dededede ................ 40480090: dededede dededede dededede dededede ................ 404800a0: dededede dededede dededede dededede ................ 404800b0: dededede dededede dededede dededede ................ 404800c0: dededede dededede dededede dededede ................ 404800d0: dededede dededede dededede dededede ................ 404800e0: dededede dededede dededede dededede ................ 404800f0: dededede dededede dededede dededede ................ u-boot=> hash sha256 ${kernel_addr_r} 100 CAAM was not setup properly or it is faulty sha256 for 40480000 ... 404800ff ==> 736372697074616464727d0a626f6f745f6566695f62696e6172793d6c6f6164 Running `sha256` commands several times in a row also produces different Results, sometimes it comes out as all 0's. For comparison purposes, I've did similar on the desktop: $ while true ; do printf "\xDE"; done | dd of=./test_data bs=1 count=256 256+0 records in 256+0 records out 256 bytes copied, 0.000484 s, 529 kB/s $ hexdump -C -v ./test_data 00000000 de de de de de de de de de de de de de de de de |................| 00000010 de de de de de de de de de de de de de de de de |................| 00000020 de de de de de de de de de de de de de de de de |................| 00000030 de de de de de de de de de de de de de de de de |................| 00000040 de de de de de de de de de de de de de de de de |................| 00000050 de de de de de de de de de de de de de de de de |................| 00000060 de de de de de de de de de de de de de de de de |................| 00000070 de de de de de de de de de de de de de de de de |................| 00000080 de de de de de de de de de de de de de de de de |................| 00000090 de de de de de de de de de de de de de de de de |................| 000000a0 de de de de de de de de de de de de de de de de |................| 000000b0 de de de de de de de de de de de de de de de de |................| 000000c0 de de de de de de de de de de de de de de de de |................| 000000d0 de de de de de de de de de de de de de de de de |................| 000000e0 de de de de de de de de de de de de de de de de |................| 000000f0 de de de de de de de de de de de de de de de de |................| 00000100 $ sha256sum ./test_data 8b11bcdc65d5f1af0fa1edfa7b5db089dba40d4e8d29b455295d58ab2b314e76 ./test_data As one can see, the SHA256 has a totally different value, with desktop produces a rather correct one. Since the CAAM is enabled per default for all i.MX8M derivatives, there is no way to target SHA hash calculations back to SW implementation, therefore it blocks a lot of people to boot FIT images that has `hash` nodes in them. Looking a bit deeper into why it fails, I saw that the JR used for hash calculations is hard-coded to `0` in run_descriptor_jr() call, which is now reserved in S-World for HAB operations. But changing it to `1` did not change the behavior, the SHA256 is still not calculated proper. Can you please advise how this can be solved? And more conceptually: why is SHA hashing now hardwired to HW CAAM module, while it was perfectly executed in SW via `lib/sha.c`? Thanks a lot! Regards, Andrey

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