July 2022 - U-Boot

[PATCH v2 1/3] mmc: stm32_sdmmc2: cosmetic: rename stm32_sdmmc_bind
by Patrick Delaunay 13 Jul '22

13 Jul '22

Rename stm32_sdmmc_bind to stm32_sdmmc2_bind as all other functions in SDMMCv2 driver series-changes: 2 - fix typo in commit message (/oter function/other functions/) Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- (no changes since v1) drivers/mmc/stm32_sdmmc2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index 81b07609a91..e3853b7fbfb 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -763,7 +763,7 @@ clk_free: return ret; } -static int stm32_sdmmc_bind(struct udevice *dev) +static int stm32_sdmmc2_bind(struct udevice *dev) { struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); @@ -781,7 +781,7 @@ U_BOOT_DRIVER(stm32_sdmmc2) = { .of_match = stm32_sdmmc2_ids, .ops = &stm32_sdmmc2_ops, .probe = stm32_sdmmc2_probe, - .bind = stm32_sdmmc_bind, + .bind = stm32_sdmmc2_bind, .priv_auto = sizeof(struct stm32_sdmmc2_priv), .plat_auto = sizeof(struct stm32_sdmmc2_plat), }; -- 2.25.1

2 6

[PATCH v2 01/10] i2c: stm32: add support for the st,stm32mp13 SOC
by Patrick Delaunay 13 Jul '22

13 Jul '22

The stm32mp13 soc differs from the stm32mp15 in terms of clear register offset for controlling the FMP (Fast Mode Plus). Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- (no changes since v1) drivers/i2c/stm32f7_i2c.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c index c6ae65badb7..bf2a6c9b4bd 100644 --- a/drivers/i2c/stm32f7_i2c.c +++ b/drivers/i2c/stm32f7_i2c.c @@ -267,6 +267,10 @@ static const struct stm32_i2c_data stm32mp15_data = { .fmp_clr_offset = 0x40, }; +static const struct stm32_i2c_data stm32mp13_data = { + .fmp_clr_offset = 0x4, +}; + static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv) { struct stm32_i2c_regs *regs = i2c_priv->regs; @@ -957,6 +961,7 @@ static const struct dm_i2c_ops stm32_i2c_ops = { static const struct udevice_id stm32_i2c_of_match[] = { { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_data }, { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32mp15_data }, + { .compatible = "st,stm32mp13-i2c", .data = (ulong)&stm32mp13_data }, {} }; -- 2.25.1

2 20

[PATCH 1/4] ARM: dts: stm32mp15: alignment with v5.19
by Patrick Delaunay 13 Jul '22

13 Jul '22

Device tree alignment with Linux kernel v5.19-rc1 - ARM: dts: stm32: Add alternate pinmux for ethernet0 pins - ARM: dts: stm32: Add alternate pinmux for mco2 pins - ARM: dts: stm32: fix pinctrl node name warnings (MPU soc) - ARM: dts: stm32: stm32mp15-pinctrl: add spi1-1 pinmux group - dt-bindings: clock: add IDs for SCMI clocks on stm32mp15 - dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15 - dt-bindings: clock: stm32mp15: rename CK_SCMI define - dt-bindings: reset: stm32mp15: rename RST_SCMI define - dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15 - dt-bindings: clk: cleanup comments - ARM: dts: align SPI NOR node name with dtschema - ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP15 - ARM: dts: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1) - ARM: dts: stm32: move SCMI related nodes in a dedicated file for stm32mp15 + patch from stm32-dt-for-v5.19-fixes-2 - ARM: dts: stm32: move SCMI related nodes in a dedicated file for stm32mp15 - ARM: dts: stm32: fix pwr regulators references to use scmi - ARM: dts: stm32: use the correct clock source for CEC on stm32mp151 - ARM: dts: stm32: DSI should use LSE SCMI clock on DK1/ED1 STM32 board - ARM: dts: stm32: delete fixed clock node on STM32MP15-SCMI - ARM: dts: stm32: add missing usbh clock and fix clk order on stm32mp15 Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/dts/stm32mp15-pinctrl.dtsi | 64 ++++++++++++ arch/arm/dts/stm32mp15-scmi.dtsi | 109 ++++++++++++++++++++ arch/arm/dts/stm32mp151.dtsi | 10 +- arch/arm/dts/stm32mp157a-dk1-scmi.dts | 79 ++++++++++++++ arch/arm/dts/stm32mp157c-dk2-scmi.dts | 85 +++++++++++++++ arch/arm/dts/stm32mp157c-ed1-scmi.dts | 84 +++++++++++++++ arch/arm/dts/stm32mp157c-ev1-scmi.dts | 90 ++++++++++++++++ arch/arm/dts/stm32mp157c-ev1.dts | 4 +- include/dt-bindings/clock/stm32fx-clock.h | 4 +- include/dt-bindings/clock/stm32mp1-clks.h | 23 +++++ include/dt-bindings/pinctrl/stm32-pinfunc.h | 1 + include/dt-bindings/reset/stm32mp1-resets.h | 14 +++ 12 files changed, 558 insertions(+), 9 deletions(-) create mode 100644 arch/arm/dts/stm32mp15-scmi.dtsi create mode 100644 arch/arm/dts/stm32mp157a-dk1-scmi.dts create mode 100644 arch/arm/dts/stm32mp157c-dk2-scmi.dts create mode 100644 arch/arm/dts/stm32mp157c-ed1-scmi.dts create mode 100644 arch/arm/dts/stm32mp157c-ev1-scmi.dts diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi index b92a149a186..d3ed10335df 100644 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi @@ -379,6 +379,40 @@ }; }; + ethernet0_rmii_pins_c: rmii-2 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ + <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet0_rmii_sleep_pins_c: rmii-sleep-2 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ + }; + }; + fmc_pins_a: fmc-0 { pins1 { pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ @@ -889,6 +923,21 @@ }; }; + mco2_pins_a: mco2-0 { + pins { + pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + mco2_sleep_pins_a: mco2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */ + }; + }; + m_can1_pins_a: m-can1-0 { pins1 { pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ @@ -2331,4 +2380,19 @@ bias-disable; }; }; + + spi1_pins_b: spi1-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */ + <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */ + bias-disable; + }; + }; }; diff --git a/arch/arm/dts/stm32mp15-scmi.dtsi b/arch/arm/dts/stm32mp15-scmi.dtsi new file mode 100644 index 00000000000..37d4547b3e8 --- /dev/null +++ b/arch/arm/dts/stm32mp15-scmi.dtsi @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue(a)foss.st.com> for STMicroelectronics. + */ + +/ { + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi: scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + shmem = <&scmi_shm>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + + scmi_voltd: protocol@17 { + reg = <0x17>; + + scmi_reguls: regulators { + #address-cells = <1>; + #size-cells = <0>; + + scmi_reg11: reg11@0 { + reg = <0>; + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + scmi_reg18: reg18@1 { + voltd-name = "reg18"; + reg = <1>; + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + scmi_usb33: usb33@2 { + reg = <2>; + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + }; + }; + + soc { + scmi_sram: sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi_shm: scmi-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0 0x80>; + }; + }; + }; +}; + +&reg11 { + status = "disabled"; +}; + +&reg18 { + status = "disabled"; +}; + +&usb33 { + status = "disabled"; +}; + +&usbotg_hs { + usb33d-supply = <&scmi_usb33>; +}; + +&usbphyc { + vdda1v1-supply = <&scmi_reg11>; + vdda1v8-supply = <&scmi_reg18>; +}; + +/delete-node/ &clk_hse; +/delete-node/ &clk_hsi; +/delete-node/ &clk_lse; +/delete-node/ &clk_lsi; +/delete-node/ &clk_csi; +/delete-node/ &reg11; +/delete-node/ &reg18; +/delete-node/ &usb33; +/delete-node/ &pwr_regulators; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index e74a5faf4a3..a5ac62c83d3 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -583,7 +583,7 @@ compatible = "st,stm32-cec"; reg = <0x40016000 0x400>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc CEC_K>, <&clk_lse>; + clocks = <&rcc CEC_K>, <&rcc CEC>; clock-names = "cec", "hdmi-cec"; status = "disabled"; }; @@ -1504,7 +1504,7 @@ usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; - clocks = <&rcc USBH>, <&usbphyc>; + clocks = <&usbphyc>, <&rcc USBH>; resets = <&rcc USBH_R>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -1513,7 +1513,7 @@ usbh_ehci: usb@5800d000 { compatible = "generic-ehci"; reg = <0x5800d000 0x1000>; - clocks = <&rcc USBH>; + clocks = <&usbphyc>, <&rcc USBH>; resets = <&rcc USBH_R>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; companion = <&usbh_ohci>; @@ -1656,7 +1656,7 @@ * Break node order to solve dependency probe issue between * pinctrl and exti. */ - pinctrl: pin-controller@50002000 { + pinctrl: pinctrl@50002000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp157-pinctrl"; @@ -1788,7 +1788,7 @@ }; }; - pinctrl_z: pin-controller-z@54004000 { + pinctrl_z: pinctrl@54004000 { #address-cells = <1>; #size-cells = <1>; compatible = "st,stm32mp157-z-pinctrl"; diff --git a/arch/arm/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/dts/stm32mp157a-dk1-scmi.dts new file mode 100644 index 00000000000..e539cc80bef --- /dev/null +++ b/arch/arm/dts/stm32mp157a-dk1-scmi.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue(a)foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157a-dk1.dts" +#include "stm32mp15-scmi.dtsi" + +/ { + model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board"; + compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157"; + + reserved-memory { + optee@de000000 { + reg = <0xde000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&dsi { + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; diff --git a/arch/arm/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/dts/stm32mp157c-dk2-scmi.dts new file mode 100644 index 00000000000..97e4f94b0a2 --- /dev/null +++ b/arch/arm/dts/stm32mp157c-dk2-scmi.dts @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue(a)foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-dk2.dts" +#include "stm32mp15-scmi.dtsi" + +/ { + model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board"; + compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157"; + + reserved-memory { + optee@de000000 { + reg = <0xde000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&dsi { + phy-dsi-supply = <&scmi_reg18>; + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; diff --git a/arch/arm/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/dts/stm32mp157c-ed1-scmi.dts new file mode 100644 index 00000000000..9cf0a44d2f4 --- /dev/null +++ b/arch/arm/dts/stm32mp157c-ed1-scmi.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue(a)foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-ed1.dts" +#include "stm32mp15-scmi.dtsi" + +/ { + model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter"; + compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157"; + + reserved-memory { + optee@fe000000 { + reg = <0xfe000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&dsi { + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; diff --git a/arch/arm/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/dts/stm32mp157c-ev1-scmi.dts new file mode 100644 index 00000000000..3b9dd6f4ccc --- /dev/null +++ b/arch/arm/dts/stm32mp157c-ev1-scmi.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue <alexandre.torgue(a)foss.st.com> for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp157c-ev1.dts" +#include "stm32mp15-scmi.dtsi" + +/ { + model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother"; + compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", + "st,stm32mp157"; + + reserved-memory { + optee@fe000000 { + reg = <0xfe000000 0x2000000>; + no-map; + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; +}; + +&dsi { + phy-dsi-supply = <&scmi_reg18>; + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; +}; + +&m_can1 { + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&mlahb { + resets = <&scmi_reset RST_SCMI_MCU>; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index e222d2d2cb4..d142dd30e16 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -262,7 +262,7 @@ #size-cells = <0>; status = "okay"; - flash0: mx66l51235l@0 { + flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-rx-bus-width = <4>; @@ -271,7 +271,7 @@ #size-cells = <1>; }; - flash1: mx66l51235l@1 { + flash1: flash@1 { compatible = "jedec,spi-nor"; reg = <1>; spi-rx-bus-width = <4>; diff --git a/include/dt-bindings/clock/stm32fx-clock.h b/include/dt-bindings/clock/stm32fx-clock.h index 1cc89c54857..e5dad050d51 100644 --- a/include/dt-bindings/clock/stm32fx-clock.h +++ b/include/dt-bindings/clock/stm32fx-clock.h @@ -7,10 +7,10 @@ */ /* - * List of clocks wich are not derived from system clock (SYSCLOCK) + * List of clocks which are not derived from system clock (SYSCLOCK) * * The index of these clocks is the secondary index of DT bindings - * (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt) + * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt) * * e.g: <assigned-clocks = <&rcc 1 CLK_LSE>; diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h index 4cdaf135829..25e8cfd4345 100644 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ b/include/dt-bindings/clock/stm32mp1-clks.h @@ -248,4 +248,27 @@ #define STM32MP1_LAST_CLK 232 +/* SCMI clock identifiers */ +#define CK_SCMI_HSE 0 +#define CK_SCMI_HSI 1 +#define CK_SCMI_CSI 2 +#define CK_SCMI_LSE 3 +#define CK_SCMI_LSI 4 +#define CK_SCMI_PLL2_Q 5 +#define CK_SCMI_PLL2_R 6 +#define CK_SCMI_MPU 7 +#define CK_SCMI_AXI 8 +#define CK_SCMI_BSEC 9 +#define CK_SCMI_CRYP1 10 +#define CK_SCMI_GPIOZ 11 +#define CK_SCMI_HASH1 12 +#define CK_SCMI_I2C4 13 +#define CK_SCMI_I2C6 14 +#define CK_SCMI_IWDG1 15 +#define CK_SCMI_RNG1 16 +#define CK_SCMI_RTC 17 +#define CK_SCMI_RTCAPB 18 +#define CK_SCMI_SPI6 19 +#define CK_SCMI_USART1 20 + #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h index e6e07807894..e6fb8ada3f4 100644 --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h @@ -39,3 +39,4 @@ #define STM32MP_PKG_AD 0x8 #endif /* _DT_BINDINGS_STM32_PINFUNC_H */ + diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h index 702da37a2e8..4ffa7c3612e 100644 --- a/include/dt-bindings/reset/stm32mp1-resets.h +++ b/include/dt-bindings/reset/stm32mp1-resets.h @@ -106,4 +106,18 @@ #define GPIOJ_R 19785 #define GPIOK_R 19786 +/* SCMI reset domain identifiers */ +#define RST_SCMI_SPI6 0 +#define RST_SCMI_I2C4 1 +#define RST_SCMI_I2C6 2 +#define RST_SCMI_USART1 3 +#define RST_SCMI_STGEN 4 +#define RST_SCMI_GPIOZ 5 +#define RST_SCMI_CRYP1 6 +#define RST_SCMI_HASH1 7 +#define RST_SCMI_RNG1 8 +#define RST_SCMI_MDMA 9 +#define RST_SCMI_MCU 10 +#define RST_SCMI_MCU_HOLD_BOOT 11 + #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ -- 2.25.1

2 8

[PATCH 1/2] ARM: dts: stm32mp13: add OP-TEE nodes
by Patrick Delaunay 13 Jul '22

13 Jul '22

Add the node for OP-TEE firmware with the associated reserved memory nodes Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/dts/stm32mp13-u-boot.dtsi | 4 ++++ arch/arm/dts/stm32mp131.dtsi | 7 +++++++ arch/arm/dts/stm32mp135f-dk.dts | 11 +++++++++++ 3 files changed, 22 insertions(+) diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi index 1b5b3586905..adc7e67ee58 100644 --- a/arch/arm/dts/stm32mp13-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13-u-boot.dtsi @@ -82,6 +82,10 @@ u-boot,dm-pre-reloc; }; +&optee { + u-boot,dm-pre-reloc; +}; + &pinctrl { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi index 950e172e455..652743fd06e 100644 --- a/arch/arm/dts/stm32mp131.dtsi +++ b/arch/arm/dts/stm32mp131.dtsi @@ -27,6 +27,13 @@ interrupt-parent = <&intc>; }; + firmware { + optee: optee { + method = "smc"; + compatible = "linaro,optee-tz"; + }; + }; + clocks { clk_axi: clk-axi { #clock-cells = <0>; diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts index ee100d108ea..31c510f976a 100644 --- a/arch/arm/dts/stm32mp135f-dk.dts +++ b/arch/arm/dts/stm32mp135f-dk.dts @@ -23,6 +23,17 @@ reg = <0xc0000000 0x20000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + optee@de000000 { + reg = <0xde000000 0x2000000>; + no-map; + }; + }; + vdd_sd: vdd-sd { compatible = "regulator-fixed"; regulator-name = "vdd_sd"; -- 2.25.1

2 4

[PATCH] arm: dts: stm32mp1: Drop fastboot and stm32prog trigger gpios on DHCOM
by Johann Neuhauser 13 Jul '22

13 Jul '22

PA13 and PA14 are used for USB power control and can't be used to enforce fastboot or stm32prog mode by pressing a button. Defining CONFIG_FASTBOOT/CONFIG_CMD_STM32PROG without this patch applied results in fastboot/stm32prog always starting, because PA13/PA14 are always low during boot. So drop the wrong trigger gpios definitions. Signed-off-by: Johann Neuhauser <jneuhauser(a)dh-electronics.com> --- arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index d73967ac1b5d..ee747a52bb7c 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -27,8 +27,6 @@ config { u-boot,boot-led = "heartbeat"; u-boot,error-led = "error"; - st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>; dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>; }; -- 2.30.2

4 4

minor regression in U-Boot 2022.04
by Daniel Golle 13 Jul '22

13 Jul '22

Hi! I'm about to bump the U-Boot build for MediaTek MT7622 boards in OpenWrt to U-Boot 2022.04. While practially everything seems to work fine, I've noticed an error message early in the serial output which was not present in U-Boot 2022.01. It is even followed by a bunch of random characters which are different on every boot (hints to a read-out-of-bounds on uninitialzed memory or the like): serial_mtk serial@11002000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19�CC� At another boot: serial_mtk serial@11002000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19��H�H�UI��$&L�1.04-OpenWrt-r19423-c9c2b01b84 (Apr 11 2022 - 19:25:34 +0000) This is probably related to recent changes in dm and pinctrl, as there haven't been any changes to mtk_serial itself. Log including ROM and ARM Trusted Firmware A serial output: F0: 102B 0000 F6: 0000 0000 V0: 0000 0000 [0001] 00: 0000 0000 BP: 0400 0041 [0000] G0: 1190 0000 T0: 0000 02AD [000F] Jump to BL NOTICE: BL2: v2.4(release):OpenWrt v2021-05-08-d2c75b21-2 (mt7622-snand-2ddr) NOTICE: BL2: Built : 12:03:10, Apr 11 2022 NOTICE: SPI-NAND: W25N01GV (128MB) NOTICE: BL2: Booting BL31 NOTICE: BL31: v2.4(release):OpenWrt v2021-05-08-d2c75b21-2 (mt7622-snand-2ddr) NOTICE: BL31: Built : 12:03:10, Apr 11 2022 serial_mtk serial@11002000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19�CC� U-Boot 2022.04-OpenWrt-r19423-c9c2b01b84 (Apr 11 2022 - 19:25:34 +0000) CPU: MediaTek MT7622 Model: mt7622-bpi-r64 DRAM: 1 GiB Core: 55 devices, 18 uclasses, devicetree: separate MMC: mmc@11230000: 0, mmc@11240000: 1 Loading Environment from UBI... SPI-NAND: W25N01GV (128MB) ... I will most likely not investigate this any further, but thought it might be good to let you know. Best regards Daniel

2 3

[PATCH] spl_imx_romapi: Remove extraneous character
by Fabio Estevam 12 Jul '22

12 Jul '22

From: Fabio Estevam <festevam(a)denx.de> Currently the following output is shown: ... Trying to boot from BOOTROM Find img info 0x&48020a00, size 872 ... Remove the extraneous "&" character, so that the correct output can be seen. Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- arch/arm/mach-imx/spl_imx_romapi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index c47f5a6bdb44..2996d2761690 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -306,7 +306,7 @@ static int spl_romapi_load_image_stream(struct spl_image_info *spl_image, } imagesize = img_info_size(phdr); - printf("Find img info 0x&%p, size %d\n", phdr, imagesize); + printf("Find img info 0x%p, size %d\n", phdr, imagesize); if (p - phdr < imagesize) { imagesize -= p - phdr; -- 2.25.1

4 3

[PATCH 1/1] fs/fat: correct handling of full directory
by Heinrich Schuchardt 12 Jul '22

12 Jul '22

If fat_create_dir_entry() fails, e.g. if the root directory is full, file_fat_write_at() must not try to write the file. Fixes: 10abea4f851a ("fs: fat: carve out fat_create_dir_entry()") Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- fs/fat/fat_write.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index a25b2283d4..ee28ca5f14 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -1428,6 +1428,11 @@ int file_fat_write_at(const char *filename, loff_t pos, void *buffer, } ret = fat_create_dir_entry(itr, basename, size, ATTR_ARCH); + if (ret < 0) { + log_err("Can't create directory entry\n"); + ret = -EIO; + goto exit; + } retdent = itr->dent; } -- 2.30.2

1 0

[RFCv2 1/2] doc: Add statistics page for v2022.07
by Tom Rini 12 Jul '22

12 Jul '22

These tables are generated by gitdm, patched to generate an rST .. table directive and then with the header, orphan tag and stats summary added manually. Cc: Heinrich Schuchardt <xypron.glpk(a)gmx.de> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- Changes in v2: - Include :orphan: this time - Use .. table and auto-width as suggested by Heinrich --- .../statistics/u-boot-stats-v2022.07.rst | 806 ++++++++++++++++++ 1 file changed, 806 insertions(+) create mode 100644 doc/develop/statistics/u-boot-stats-v2022.07.rst diff --git a/doc/develop/statistics/u-boot-stats-v2022.07.rst b/doc/develop/statistics/u-boot-stats-v2022.07.rst new file mode 100644 index 000000000000..0655e3ea933f --- /dev/null +++ b/doc/develop/statistics/u-boot-stats-v2022.07.rst @@ -0,0 +1,806 @@ +:orphan: + +U-Boot v2022.07 Release Statistics +================================== + +* Processed 1696 csets from 183 developers + +* 27 employers found + +* A total of 148026 lines added, 56440 removed (delta 91586) + +.. table:: Developers with the most changesets + :widths: auto + + ========================= ========== + Name Changesets + ========================= ========== + Tom Rini 164 (9.7%) + Simon Glass 141 (8.3%) + Pali Rohár 114 (6.7%) + Marek Vasut 94 (5.5%) + Peng Fan 61 (3.6%) + Sean Anderson 59 (3.5%) + Heinrich Schuchardt 57 (3.4%) + Samuel Holland 49 (2.9%) + Michal Simek 49 (2.9%) + Johan Jonker 45 (2.7%) + Aaron Williams 40 (2.4%) + AKASHI Takahiro 38 (2.2%) + Marek Behún 36 (2.1%) + Tim Harvey 33 (1.9%) + Philippe Reynes 29 (1.7%) + Andre Przywara 28 (1.7%) + Andrew Scull 27 (1.6%) + Patrice Chotard 26 (1.5%) + Patrick Delaunay 25 (1.5%) + Fabio Estevam 24 (1.4%) + Gaurav Jain 20 (1.2%) + Ye Li 20 (1.2%) + Ashok Reddy Soma 16 (0.9%) + Stefan Roese 13 (0.8%) + Sughosh Ganu 12 (0.7%) + Masahisa Kojima 12 (0.7%) + Michael Trimarchi 11 (0.6%) + Paweł Anikiel 11 (0.6%) + Adam Ford 11 (0.6%) + Marcel Ziswiler 11 (0.6%) + Dave Gerlach 11 (0.6%) + Philip Oberfichtner 11 (0.6%) + T Karthik Reddy 11 (0.6%) + Bin Meng 9 (0.5%) + Tommaso Merciai 9 (0.5%) + Heiko Thiery 8 (0.5%) + Alper Nebi Yasak 8 (0.5%) + Philippe Schenker 8 (0.5%) + Vyacheslav Bocharov 8 (0.5%) + Michael Walle 7 (0.4%) + Peter Robinson 6 (0.4%) + Francesco Dolcini 6 (0.4%) + Mark Kettenis 6 (0.4%) + Neal Frager 6 (0.4%) + Robert Marko 6 (0.4%) + Jim Liu 6 (0.4%) + Tudor Ambarus 6 (0.4%) + Paweł Jarosz 5 (0.3%) + Dinesh Maniyam 5 (0.3%) + Ariel D'Alessandro 5 (0.3%) + Eugen Hristev 5 (0.3%) + Sergiu Moga 5 (0.3%) + Lukasz Majewski 5 (0.3%) + Clément Léger 5 (0.3%) + Huang Jianan 5 (0.3%) + Etienne Carriere 5 (0.3%) + Tien Fong Chee 4 (0.2%) + Chris Morgan 4 (0.2%) + Dario Binacchi 4 (0.2%) + Frieder Schrempf 4 (0.2%) + Janne Grunau 4 (0.2%) + Josua Mayer 4 (0.2%) + Vincent Stehlé 4 (0.2%) + Chris Packham 4 (0.2%) + Sai Pavan Boddu 4 (0.2%) + Neil Armstrong 4 (0.2%) + Jan Kiszka 4 (0.2%) + Andrew Davis 4 (0.2%) + Aswath Govindraju 4 (0.2%) + Masami Hiramatsu 4 (0.2%) + Durai Manickam KR 4 (0.2%) + Billy Tsai 4 (0.2%) + Angus Ainslie 4 (0.2%) + Jesse Taube 4 (0.2%) + Andrew Jeffery 4 (0.2%) + Hari Nagalla 4 (0.2%) + Icenowy Zheng 4 (0.2%) + Romain Naour 4 (0.2%) + Joel Stanley 3 (0.2%) + Andrey Zhizhikin 3 (0.2%) + Loic Poulain 3 (0.2%) + Rasmus Villemoes 3 (0.2%) + Vagrant Cascadian 3 (0.2%) + Ilias Apalodimas 3 (0.2%) + Eddie James 3 (0.2%) + Gireesh Hiremath 3 (0.2%) + Sam Shih 3 (0.2%) + Luca Ellero 3 (0.2%) + Tony Dinh 3 (0.2%) + Paul Barker 3 (0.2%) + Oleksandr Suvorov 3 (0.2%) + Igor Opaniuk 3 (0.2%) + Denys Drozdov 3 (0.2%) + SESA644425 3 (0.2%) + Vignesh Raghavendra 3 (0.2%) + Dzmitry Sankouski 3 (0.2%) + Jernej Skrabec 3 (0.2%) + Miquel Raynal 2 (0.1%) + Christian Gmeiner 2 (0.1%) + Nate Drude 2 (0.1%) + Rick Chen 2 (0.1%) + Yannick Fertre 2 (0.1%) + Peter Hoyes 2 (0.1%) + Dominic Rath 2 (0.1%) + Du Huanpeng 2 (0.1%) + Haolin Li 2 (0.1%) + Clement Faure 2 (0.1%) + Vladimir Oltean 2 (0.1%) + Christoph Niedermaier 2 (0.1%) + Paul Barbieri 1 (0.1%) + Hannes Schmelzer 1 (0.1%) + Teik Heng Chong 1 (0.1%) + Andrea Scian 1 (0.1%) + Jerome Forissier 1 (0.1%) + Emmanuel Vadot 1 (0.1%) + Nicolas Iooss 1 (0.1%) + Andrejs Cainikovs 1 (0.1%) + qianfan Zhao 1 (0.1%) + Yau Wai Gan 1 (0.1%) + Corentin LABBE 1 (0.1%) + Christophe Leroy 1 (0.1%) + Chunfeng Yun 1 (0.1%) + Camelia Groza 1 (0.1%) + Wasim Khan 1 (0.1%) + Georgi Vlaev 1 (0.1%) + Andrea zi0Black Cappa 1 (0.1%) + Leo Yu-Chi Liang 1 (0.1%) + Humberto Naves 1 (0.1%) + Sean Nyekjaer 1 (0.1%) + Christoph Fritz 1 (0.1%) + Sergei Antonov 1 (0.1%) + George Hilliard 1 (0.1%) + Ying-Chun Liu (PaulLiu) 1 (0.1%) + Vishal Patel 1 (0.1%) + Piyush Mehta 1 (0.1%) + Amit Kumar Mahapatra 1 (0.1%) + Jorge Ramirez-Ortiz 1 (0.1%) + Ralph Siemsen 1 (0.1%) + Ovidiu Panait 1 (0.1%) + John Keeping 1 (0.1%) + Oliver Graute 1 (0.1%) + Nicolas Heemeryck 1 (0.1%) + Stanley Chu 1 (0.1%) + Josef Schlehofer 1 (0.1%) + Stephen Carlson 1 (0.1%) + Yuantian Tang 1 (0.1%) + Hou Zhiqiang 1 (0.1%) + Kyle Evans 1 (0.1%) + Lyle Franklin 1 (0.1%) + Andrew Abbott 1 (0.1%) + Oleksii Titov 1 (0.1%) + Kshitiz Varshney 1 (0.1%) + Ian Ray 1 (0.1%) + Rogier Stam 1 (0.1%) + Diego Rondini 1 (0.1%) + Daniel Golle 1 (0.1%) + Peter Cai 1 (0.1%) + Alexandre Besnard 1 (0.1%) + Elmar Albert 1 (0.1%) + Arjan Minzinga Zijlstra 1 (0.1%) + Oleksii Bidnichenko 1 (0.1%) + Ji Luo 1 (0.1%) + Clark Wang 1 (0.1%) + Clément Péron 1 (0.1%) + Andy Shevchenko 1 (0.1%) + Hajo Noerenberg 1 (0.1%) + Ville Baillie 1 (0.1%) + Paul HENRYS 1 (0.1%) + Jérôme Carretero 1 (0.1%) + Dhananjay Phadke 1 (0.1%) + Ivan Vozvakhov 1 (0.1%) + Tom Saeger 1 (0.1%) + Adarsh Babu Kalepalli 1 (0.1%) + He Yong 1 (0.1%) + Samuel Dionne-Riel 1 (0.1%) + Felix Vietmeyer 1 (0.1%) + Yi Liu 1 (0.1%) + Angelo Dureghello 1 (0.1%) + Baltazár Radics 1 (0.1%) + Alexander Graf 1 (0.1%) + Mihai Sain 1 (0.1%) + Sai Krishna Potthuri 1 (0.1%) + weichangzheng 1 (0.1%) + ========================= ========== + + +.. table:: Developers with the most changed lines + :widths: auto + + ========================= ========== + Name Changesets + ========================= ========== + Aaron Williams 31473 (16.9%) + Tom Rini 25599 (13.7%) + Simon Glass 17972 (9.7%) + Marek Vasut 14707 (7.9%) + Tim Harvey 11858 (6.4%) + Sean Anderson 10323 (5.5%) + Samuel Holland 8705 (4.7%) + Stefan Roese 4394 (2.4%) + Johan Jonker 3712 (2.0%) + Jim Liu 3650 (2.0%) + Ariel D'Alessandro 3358 (1.8%) + Huang Jianan 3272 (1.8%) + Philippe Reynes 2587 (1.4%) + Philip Oberfichtner 2400 (1.3%) + Peng Fan 2365 (1.3%) + Pali Rohár 2277 (1.2%) + Paweł Jarosz 2092 (1.1%) + AKASHI Takahiro 1700 (0.9%) + Eugen Hristev 1532 (0.8%) + Gaurav Jain 1522 (0.8%) + Humberto Naves 1498 (0.8%) + Marek Behún 1353 (0.7%) + Andre Przywara 1318 (0.7%) + Paul Barker 1308 (0.7%) + Patrick Delaunay 1200 (0.6%) + Paweł Anikiel 1162 (0.6%) + Michal Simek 1065 (0.6%) + Patrice Chotard 1038 (0.6%) + Ashok Reddy Soma 1000 (0.5%) + Sughosh Ganu 954 (0.5%) + Denys Drozdov 942 (0.5%) + Neal Frager 894 (0.5%) + Angus Ainslie 804 (0.4%) + Heinrich Schuchardt 692 (0.4%) + weichangzheng 686 (0.4%) + Etienne Carriere 652 (0.4%) + Janne Grunau 648 (0.3%) + Marcel Ziswiler 636 (0.3%) + Andrew Scull 606 (0.3%) + Neil Armstrong 598 (0.3%) + Masahisa Kojima 567 (0.3%) + Adam Ford 524 (0.3%) + Billy Tsai 497 (0.3%) + Alper Nebi Yasak 440 (0.2%) + Fabio Estevam 420 (0.2%) + Michael Trimarchi 393 (0.2%) + Durai Manickam KR 378 (0.2%) + Vincent Stehlé 369 (0.2%) + Andrew Jeffery 359 (0.2%) + T Karthik Reddy 322 (0.2%) + Francesco Dolcini 306 (0.2%) + Ye Li 303 (0.2%) + Nate Drude 275 (0.1%) + Dave Gerlach 263 (0.1%) + Sergiu Moga 260 (0.1%) + Tony Dinh 256 (0.1%) + Sam Shih 252 (0.1%) + Ivan Vozvakhov 252 (0.1%) + Dzmitry Sankouski 244 (0.1%) + Tommaso Merciai 242 (0.1%) + Yannick Fertre 217 (0.1%) + Clément Léger 208 (0.1%) + Eddie James 202 (0.1%) + Ilias Apalodimas 190 (0.1%) + Philippe Schenker 189 (0.1%) + Adarsh Babu Kalepalli 174 (0.1%) + Igor Opaniuk 160 (0.1%) + Michael Walle 159 (0.1%) + Lukasz Majewski 157 (0.1%) + Josua Mayer 137 (0.1%) + Vyacheslav Bocharov 131 (0.1%) + Stanley Chu 131 (0.1%) + Gireesh Hiremath 127 (0.1%) + Hari Nagalla 126 (0.1%) + Leo Yu-Chi Liang 116 (0.1%) + Luca Ellero 107 (0.1%) + Chris Morgan 100 (0.1%) + Peter Hoyes 100 (0.1%) + Ji Luo 100 (0.1%) + George Hilliard 82 (0.0%) + Mark Kettenis 79 (0.0%) + Frieder Schrempf 78 (0.0%) + Heiko Thiery 72 (0.0%) + Icenowy Zheng 69 (0.0%) + Joel Stanley 66 (0.0%) + Diego Rondini 64 (0.0%) + Robert Marko 63 (0.0%) + Dinesh Maniyam 59 (0.0%) + Andrejs Cainikovs 49 (0.0%) + Samuel Dionne-Riel 48 (0.0%) + Mihai Sain 45 (0.0%) + Bin Meng 41 (0.0%) + Loic Poulain 40 (0.0%) + SESA644425 40 (0.0%) + Masami Hiramatsu 39 (0.0%) + Clement Faure 39 (0.0%) + He Yong 39 (0.0%) + Rasmus Villemoes 38 (0.0%) + Jernej Skrabec 37 (0.0%) + Jerome Forissier 35 (0.0%) + Paul HENRYS 31 (0.0%) + Jérôme Carretero 30 (0.0%) + Paul Barbieri 28 (0.0%) + Aswath Govindraju 27 (0.0%) + Jan Kiszka 26 (0.0%) + Jesse Taube 26 (0.0%) + Nicolas Heemeryck 23 (0.0%) + Ville Baillie 23 (0.0%) + Andrew Davis 22 (0.0%) + Kyle Evans 22 (0.0%) + Peter Robinson 21 (0.0%) + Romain Naour 21 (0.0%) + Peter Cai 21 (0.0%) + Hou Zhiqiang 20 (0.0%) + Clark Wang 20 (0.0%) + Sai Pavan Boddu 18 (0.0%) + Amit Kumar Mahapatra 18 (0.0%) + Elmar Albert 18 (0.0%) + Tudor Ambarus 16 (0.0%) + Oleksandr Suvorov 16 (0.0%) + Chris Packham 15 (0.0%) + Vagrant Cascadian 15 (0.0%) + Dominic Rath 13 (0.0%) + Andrea Scian 13 (0.0%) + Christoph Fritz 13 (0.0%) + Nicolas Iooss 12 (0.0%) + Miquel Raynal 11 (0.0%) + Vishal Patel 11 (0.0%) + Georgi Vlaev 9 (0.0%) + Dario Binacchi 8 (0.0%) + Teik Heng Chong 8 (0.0%) + Piyush Mehta 8 (0.0%) + Ovidiu Panait 8 (0.0%) + John Keeping 8 (0.0%) + Dhananjay Phadke 8 (0.0%) + Tom Saeger 8 (0.0%) + Tien Fong Chee 7 (0.0%) + Stephen Carlson 7 (0.0%) + Lyle Franklin 7 (0.0%) + Felix Vietmeyer 7 (0.0%) + Alexander Graf 7 (0.0%) + Andrey Zhizhikin 6 (0.0%) + Vignesh Raghavendra 6 (0.0%) + Christian Gmeiner 6 (0.0%) + Haolin Li 6 (0.0%) + Daniel Golle 6 (0.0%) + Rick Chen 5 (0.0%) + Ying-Chun Liu (PaulLiu) 5 (0.0%) + Rogier Stam 5 (0.0%) + Alexandre Besnard 5 (0.0%) + Angelo Dureghello 5 (0.0%) + Christoph Niedermaier 4 (0.0%) + Hannes Schmelzer 4 (0.0%) + Chunfeng Yun 4 (0.0%) + Kshitiz Varshney 4 (0.0%) + Yi Liu 4 (0.0%) + Baltazár Radics 4 (0.0%) + Christophe Leroy 3 (0.0%) + Wasim Khan 3 (0.0%) + Andrea zi0Black Cappa 3 (0.0%) + Sean Nyekjaer 3 (0.0%) + Andy Shevchenko 3 (0.0%) + Du Huanpeng 2 (0.0%) + Vladimir Oltean 2 (0.0%) + Camelia Groza 2 (0.0%) + Sergei Antonov 2 (0.0%) + Oliver Graute 2 (0.0%) + Yuantian Tang 2 (0.0%) + Oleksii Titov 2 (0.0%) + Arjan Minzinga Zijlstra 2 (0.0%) + Oleksii Bidnichenko 2 (0.0%) + Clément Péron 2 (0.0%) + Hajo Noerenberg 2 (0.0%) + Sai Krishna Potthuri 2 (0.0%) + Emmanuel Vadot 1 (0.0%) + qianfan Zhao 1 (0.0%) + Yau Wai Gan 1 (0.0%) + Corentin LABBE 1 (0.0%) + Jorge Ramirez-Ortiz 1 (0.0%) + Ralph Siemsen 1 (0.0%) + Josef Schlehofer 1 (0.0%) + Andrew Abbott 1 (0.0%) + Ian Ray 1 (0.0%) + ========================= ========== + + +.. table:: Developers with the most lines removed + :widths: auto + + ========================= ========== + Name Changesets + ========================= ========== + Tom Rini 19724 (34.9%) + Denys Drozdov 941 (1.7%) + Marcel Ziswiler 430 (0.8%) + Stefan Roese 331 (0.6%) + Marek Behún 309 (0.5%) + Adam Ford 247 (0.4%) + Tony Dinh 187 (0.3%) + Igor Opaniuk 134 (0.2%) + Leo Yu-Chi Liang 116 (0.2%) + Etienne Carriere 97 (0.2%) + Francesco Dolcini 30 (0.1%) + Rasmus Villemoes 19 (0.0%) + Hou Zhiqiang 16 (0.0%) + Frieder Schrempf 14 (0.0%) + John Keeping 8 (0.0%) + Romain Naour 5 (0.0%) + Ying-Chun Liu (PaulLiu) 5 (0.0%) + Ovidiu Panait 3 (0.0%) + Vignesh Raghavendra 3 (0.0%) + Andrea zi0Black Cappa 2 (0.0%) + Andy Shevchenko 2 (0.0%) + Peter Robinson 1 (0.0%) + Josef Schlehofer 1 (0.0%) + Ian Ray 1 (0.0%) + ========================= ========== + + +.. table:: Developers with the most signoffs (total 266) + :widths: auto + + ========================= ========== + Name Changesets + ========================= ========== + Andre Przywara 50 (18.8%) + Michal Simek 43 (16.2%) + Stefan Roese 41 (15.4%) + Patrice Chotard 23 (8.6%) + Peng Fan 17 (6.4%) + Marcel Ziswiler 16 (6.0%) + Neil Armstrong 9 (3.4%) + Priyanka Jain 7 (2.6%) + Michael Trimarchi 6 (2.3%) + Johan Jonker 5 (1.9%) + Tom Rini 4 (1.5%) + Tom Warren 4 (1.5%) + T Karthik Reddy 4 (1.5%) + Stanley Chu 4 (1.5%) + Samuel Holland 4 (1.5%) + Yau Wai Gan 2 (0.8%) + Jagan Teki 2 (0.8%) + Biwen Li 2 (0.8%) + Ye Li 2 (0.8%) + Ilias Apalodimas 2 (0.8%) + Heinrich Schuchardt 2 (0.8%) + Ariel D'Alessandro 2 (0.8%) + Amit Kumar Mahapatra 1 (0.4%) + Wolfgang Wallner 1 (0.4%) + Alexandru M Stan 1 (0.4%) + Kever Yang 1 (0.4%) + Chee Hong Ang 1 (0.4%) + Yifan Gu 1 (0.4%) + Horia Geantă 1 (0.4%) + Richard Weinberger 1 (0.4%) + Anatolij Gustschin 1 (0.4%) + Gabriel Fernandez 1 (0.4%) + Christian Gmeiner 1 (0.4%) + Sai Krishna Potthuri 1 (0.4%) + Josua Mayer 1 (0.4%) + Masahisa Kojima 1 (0.4%) + Ashok Reddy Soma 1 (0.4%) + ========================= ========== + + +.. table:: Developers with the most reviews (total 871) + :widths: auto + + ========================= ========== + Name Changesets + ========================= ========== + Simon Glass 100 (11.5%) + Fabio Estevam 69 (7.9%) + Stefan Roese 67 (7.7%) + Ramon Fried 65 (7.5%) + Kever Yang 63 (7.2%) + Priyanka Jain 53 (6.1%) + Patrice Chotard 38 (4.4%) + Patrick Delaunay 38 (4.4%) + Heinrich Schuchardt 35 (4.0%) + Andre Przywara 31 (3.6%) + Peng Fan 26 (3.0%) + Bin Meng 25 (2.9%) + Alper Nebi Yasak 23 (2.6%) + Tom Rini 21 (2.4%) + Marek Behún 21 (2.4%) + Jaehoon Chung 19 (2.2%) + Ye Li 13 (1.5%) + Marek Vasut 12 (1.4%) + Heiko Schocher 9 (1.0%) + Tien Fong Chee 9 (1.0%) + Sean Anderson 9 (1.0%) + Vladimir Oltean 8 (0.9%) + Ilias Apalodimas 7 (0.8%) + Leo Yu-Chi Liang 6 (0.7%) + Mark Kettenis 6 (0.7%) + Neil Armstrong 5 (0.6%) + Samuel Holland 5 (0.6%) + Jagan Teki 5 (0.6%) + Masami Hiramatsu 5 (0.6%) + Gaurav Jain 5 (0.6%) + Christian Gmeiner 4 (0.5%) + Chia-Wei Wang 4 (0.5%) + Claudiu Beznea 4 (0.5%) + Pali Rohár 4 (0.5%) + Ashok Reddy Soma 3 (0.3%) + Francesco Dolcini 3 (0.3%) + Nishanth Menon 3 (0.3%) + Stefano Babic 3 (0.3%) + Holger Brunck 3 (0.3%) + Miquel Raynal 3 (0.3%) + Michael Walle 3 (0.3%) + Michal Simek 2 (0.2%) + Michael Trimarchi 2 (0.2%) + Tony Dinh 2 (0.2%) + Frieder Schrempf 2 (0.2%) + Minkyu Kang 2 (0.2%) + Rick Chen 2 (0.2%) + Tudor Ambarus 2 (0.2%) + Joel Stanley 2 (0.2%) + Tim Harvey 2 (0.2%) + Marcel Ziswiler 1 (0.1%) + John Keeping 1 (0.1%) + Peter Robinson 1 (0.1%) + Peter Collingbourne 1 (0.1%) + Pankaj Gupta 1 (0.1%) + Han Xu 1 (0.1%) + Radhey Shyam Pandey 1 (0.1%) + Philipp Tomsich 1 (0.1%) + Thomas Chou 1 (0.1%) + Kristian Amlie 1 (0.1%) + Qu Wenruo 1 (0.1%) + Jacky Bai 1 (0.1%) + Ley Foon Tan 1 (0.1%) + Dylan Hung 1 (0.1%) + Andrey Zhizhikin 1 (0.1%) + Kshitiz Varshney 1 (0.1%) + Andrew Scull 1 (0.1%) + Janne Grunau 1 (0.1%) + ========================= ========== + + +.. table:: Developers with the most test credits (total 66) + :widths: auto + + ========================= ========== + Name Changesets + ========================= ========== + Tim Harvey 15 (22.7%) + Patrice Chotard 5 (7.6%) + Mark Kettenis 4 (6.1%) + Adam Ford 4 (6.1%) + Fabio Estevam 3 (4.5%) + Marek Vasut 3 (4.5%) + Marcel Ziswiler 3 (4.5%) + Derald D. Woods 3 (4.5%) + Pali Rohár 2 (3.0%) + Ariel D'Alessandro 2 (3.0%) + Heiko Thiery 2 (3.0%) + Andre Przywara 1 (1.5%) + Chia-Wei Wang 1 (1.5%) + Stefano Babic 1 (1.5%) + Frieder Schrempf 1 (1.5%) + John Keeping 1 (1.5%) + Peter Robinson 1 (1.5%) + Peter Collingbourne 1 (1.5%) + Kshitiz Varshney 1 (1.5%) + Janne Grunau 1 (1.5%) + Josua Mayer 1 (1.5%) + Ying-Chun Liu (PaulLiu) 1 (1.5%) + Peter Griffin 1 (1.5%) + Tatsuhiko Yasumatsu 1 (1.5%) + Jincheng Wang 1 (1.5%) + Gabriel Hojda 1 (1.5%) + Arti Zirk 1 (1.5%) + Merlijn Wajer 1 (1.5%) + Soeren Moch 1 (1.5%) + Raffaele RECALCATI 1 (1.5%) + Angus Ainslie 1 (1.5%) + ========================= ========== + + +.. table:: Developers who gave the most tested-by credits (total 67) + :widths: auto + + ========================= ========== + Name Changesets + ========================= ========== + Marek Vasut 14 (20.9%) + Fabio Estevam 6 (9.0%) + Michael Trimarchi 6 (9.0%) + Heiko Thiery 4 (6.0%) + Adam Ford 3 (4.5%) + Heinrich Schuchardt 3 (4.5%) + Tom Rini 3 (4.5%) + Pali Rohár 2 (3.0%) + Andre Przywara 2 (3.0%) + Frieder Schrempf 2 (3.0%) + Janne Grunau 2 (3.0%) + Miquel Raynal 2 (3.0%) + Masahisa Kojima 2 (3.0%) + Tim Harvey 1 (1.5%) + Mark Kettenis 1 (1.5%) + Angus Ainslie 1 (1.5%) + Simon Glass 1 (1.5%) + Peng Fan 1 (1.5%) + Marek Behún 1 (1.5%) + Ye Li 1 (1.5%) + Gaurav Jain 1 (1.5%) + Joel Stanley 1 (1.5%) + Rasmus Villemoes 1 (1.5%) + Christoph Niedermaier 1 (1.5%) + Peter Cai 1 (1.5%) + Jerome Forissier 1 (1.5%) + Andrejs Cainikovs 1 (1.5%) + Nate Drude 1 (1.5%) + AKASHI Takahiro 1 (1.5%) + ========================= ========== + + +.. table:: Developers with the most report credits (total 19) + :widths: auto + + ========================= ========== + Name Changesets + ========================= ========== + Tom Rini 2 (10.5%) + Patrick Delaunay 2 (10.5%) + Fabio Estevam 1 (5.3%) + Tim Harvey 1 (5.3%) + Tatsuhiko Yasumatsu 1 (5.3%) + Jincheng Wang 1 (5.3%) + Gabriel Hojda 1 (5.3%) + Nishanth Menon 1 (5.3%) + Milan P. Stanić 1 (5.3%) + Yun-Chien Yu 1 (5.3%) + Nicolas Bidron 1 (5.3%) + Balaji Anandapadmanaban 1 (5.3%) + David Mosberger-Tang 1 (5.3%) + Jesse Villarreal 1 (5.3%) + Suman Anna 1 (5.3%) + Vagrant Cascadian 1 (5.3%) + Chris Morgan 1 (5.3%) + ========================= ========== + + +.. table:: Developers who gave the most report credits (total 19) + :widths: auto + + ========================= ========== + Name Changesets + ========================= ========== + Simon Glass 5 (26.3%) + Andre Przywara 3 (15.8%) + Heinrich Schuchardt 2 (10.5%) + Miquel Raynal 2 (10.5%) + Aswath Govindraju 2 (10.5%) + Tom Rini 1 (5.3%) + Fabio Estevam 1 (5.3%) + Samuel Holland 1 (5.3%) + Tudor Ambarus 1 (5.3%) + Chunfeng Yun 1 (5.3%) + ========================= ========== + + +.. table:: Top changeset contributors by employer + :widths: auto + + ========================= ========== + Name Changesets + ========================= ========== + (Unknown) 669 (39.4%) + Google, Inc. 168 (9.9%) + Konsulko Group 164 (9.7%) + DENX Software Engineering 147 (8.7%) + NXP 112 (6.6%) + Linaro 80 (4.7%) + ST Microelectronics 53 (3.1%) + AMD 51 (3.0%) + Marvell 40 (2.4%) + Xilinx 39 (2.3%) + ARM 34 (2.0%) + Toradex 33 (1.9%) + Texas Instruments 27 (1.6%) + Amarula Solutions 24 (1.4%) + Intel 12 (0.7%) + Semihalf Embedded Systems 11 (0.6%) + Bootlin 7 (0.4%) + BayLibre SAS 5 (0.3%) + Collabora Ltd. 5 (0.3%) + Siemens 4 (0.2%) + Debian.org 3 (0.2%) + IBM 3 (0.2%) + Wind River 1 (0.1%) + Dave S.r.l. 1 (0.1%) + General Electric 1 (0.1%) + Oracle 1 (0.1%) + Rockchip 1 (0.1%) + ========================= ========== + + +.. table:: Top lines changed by employer + :widths: auto + + ========================= ========== + Name Changesets + ========================= ========== + (Unknown) 63402 (34.0%) + Marvell 31473 (16.9%) + Konsulko Group 25599 (13.7%) + DENX Software Engineering 22078 (11.9%) + Google, Inc. 18578 (10.0%) + NXP 4382 (2.4%) + Linaro 4183 (2.2%) + Collabora Ltd. 3358 (1.8%) + ST Microelectronics 2455 (1.3%) + Xilinx 2277 (1.2%) + Toradex 2140 (1.1%) + ARM 1787 (1.0%) + Semihalf Embedded Systems 1162 (0.6%) + AMD 1061 (0.6%) + Amarula Solutions 643 (0.3%) + BayLibre SAS 599 (0.3%) + Texas Instruments 453 (0.2%) + Bootlin 219 (0.1%) + IBM 202 (0.1%) + Intel 78 (0.0%) + Siemens 26 (0.0%) + Debian.org 15 (0.0%) + Dave S.r.l. 13 (0.0%) + Wind River 8 (0.0%) + Oracle 8 (0.0%) + Rockchip 4 (0.0%) + General Electric 1 (0.0%) + ========================= ========== + + +.. table:: Employers with the most signoffs (total 266) + :widths: auto + + ========================= ========== + Name Changesets + ========================= ========== + ARM 50 (18.8%) + DENX Software Engineering 42 (15.8%) + Xilinx 39 (14.7%) + NXP 29 (10.9%) + ST Microelectronics 24 (9.0%) + (Unknown) 21 (7.9%) + Toradex 16 (6.0%) + AMD 11 (4.1%) + BayLibre SAS 9 (3.4%) + Amarula Solutions 8 (3.0%) + Konsulko Group 4 (1.5%) + NVidia 4 (1.5%) + Linaro 3 (1.1%) + Intel 3 (1.1%) + Collabora Ltd. 2 (0.8%) + Rockchip 1 (0.4%) + ========================= ========== + + +.. table:: Employers with the most hackers (total 185) + :widths: auto + + ========================= ========== + Name Changesets + ========================= ========== + (Unknown) 102 (55.1%) + NXP 12 (6.5%) + Linaro 10 (5.4%) + Xilinx 9 (4.9%) + Toradex 7 (3.8%) + Texas Instruments 6 (3.2%) + DENX Software Engineering 5 (2.7%) + Intel 5 (2.7%) + ARM 3 (1.6%) + ST Microelectronics 3 (1.6%) + Amarula Solutions 3 (1.6%) + AMD 2 (1.1%) + BayLibre SAS 2 (1.1%) + Google, Inc. 2 (1.1%) + Bootlin 2 (1.1%) + Konsulko Group 1 (0.5%) + Collabora Ltd. 1 (0.5%) + Rockchip 1 (0.5%) + Marvell 1 (0.5%) + Semihalf Embedded Systems 1 (0.5%) + IBM 1 (0.5%) + Siemens 1 (0.5%) + Debian.org 1 (0.5%) + Dave S.r.l. 1 (0.5%) + Wind River 1 (0.5%) + Oracle 1 (0.5%) + General Electric 1 (0.5%) + ========================= ========== + -- 2.25.1

3 14

[PATCH 1/2] rockchip: rk3399: fix incorrect ifdef check on SPL_DM_REGULATOR
by Quentin Schulz 12 Jul '22

12 Jul '22

From: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> The check to perform is on CONFIG_SPL_DM_REGULATOR and not SPL_DM_REGULATOR. Fixes: 07586ee4322a ("rockchip: rk3399: Support common spl_board_init") Cc: Quentin Schulz <foss+uboot(a)0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> --- arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index de11a3fa30..ad274b66ce 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -275,7 +275,7 @@ void spl_board_init(void) rk3399_force_power_on_reset(); #endif -#if defined(SPL_DM_REGULATOR) +#if defined(CONFIG_SPL_DM_REGULATOR) /* * Turning the eMMC and SPI back on (if disabled via the Qseven * BIOS_ENABLE) signal is done through a always-on regulator). -- 2.36.1

2 3