July 2022 - U-Boot

[PATCH] arm: dts: rockchip: rk3399: usb: ehci: Fix EHCI probe in rk3399 to access peripherals by USB 2.
by Xavier Drudis Ferran 31 Aug '22

31 Aug '22

arch/arm/dts/rk3399.dtsi has a node usb_host0_ehci: usb@fe380000 { compatible = "generic-ehci"; with clocks: clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, <&u2phy0>; The first 2 refer to nodes with class UCLASS_CLK, but &u2phy0 has class UCLASS_PHY. u2phy0: usb2phy@e450 { compatible = "rockchip,rk3399-usb2phy"; Since clk_get_bulk() only looks for devices with UCLASS_CLK, it fails with -ENODEV and then ehci_usb_probe() aborts. The consequence is peripherals connected to a USB 2 port (e.g. in a Rock Pi 4 the white port, nearer the edge) not being detected. They're detected if CONFIG_USB_OHCI_GENERIC is selected in Kconfig, because ohci_usb_probe() does not abort when one clk_get_by_index() fails, but then they work in USB 1 mode,. rk3399.dtsi comes from linux and the u2phy0 was added[1] to the clock list in: commit b5d1c57299734f5b54035ef2e61706b83041f20c Author: William wu <wulf(a)rock-chips.com> Date: Wed Dec 21 18:41:05 2016 +0800 arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399 We found that the suspend process was blocked when it run into ehci/ohci module due to clk-480m of usb2-phy was disabled. [...] Suspend concerns don't apply to U-Boot, and the problem with U-Boot failing to probe EHCI doesn't apply to linux, because in linux rockchip_usb2phy_clk480m_register makes u2phy0 a proper clock provider when called by rockchip_usb2phy_probe(). So I can think of a few alternative solutions: 1- Change ehci_usb_probe() to make it more similar to ohci_usb_probe(), and survive failure to get one clock. Looks a little harder, and I don't know whether it could break something if it ignored a clock that was important for something else than suspend. 2- Change rk3399.dtsi effecttively reverting the linux commit b5d1c57299734f5b54035ef2e61706b83041f20c. This dealigns the .dtsi from linux and seems fragile at the next synchronisation. 3- Change the clock list in rk3399-u-boot.dtsi or somewhere else. This survives .dts* sync but may survive "too much" and miss some change from linux that we might want. 4- Enable CONFIG_USB_OHCI_GENERIC and use the ports in USB 1 mode. This would need to be made for all boards using rk3399. In a simple test reading one file from USB storage it gave 769.5 KiB/s instead of 20.5 MiB/s with solution 2. 5- Trying to replicate linux and have usb2phy somehow provide a clk, or have a separate clock device for usb2phy in addition to the phy device. I just can't seem to imagine how to achieve this with the U-Boot driver model, maybe because of my limited familiarity with it. This patch is option 3. Looked like the simplest and most performant. But it might not be what's wanted, so comments wellcome. Link: [1] https://lkml.kernel.org/lkml/1731551.Q6cHK6n5ZM@phil/T/ Cc: Simon Glass <sjg(a)chromium.org> Cc: Philipp Tomsich <philipp.tomsich(a)vrull.eu> Cc: Kever Yang <kever.yang(a)rock-chips.com> Cc: Lukasz Majewski <lukma(a)denx.de> Cc: Sean Anderson <seanga2(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> Signed-off-by: Xavier Drudis Ferran <xdrudis(a)tinet.cat> --- arch/arm/dts/rk3399-u-boot.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 716b9a433a..63c7b10405 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -147,3 +147,11 @@ &vopl { u-boot,dm-pre-reloc; }; + +&usb_host0_ehci { + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; +}; + +&usb_host1_ehci { + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; +}; -- 2.20.1

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[PULL] u-boot-riscv/master
by Leo Liang 30 Aug '22

30 Aug '22

Hi Tom, The following changes since commit 7e0edcadb09d55d5319fdc862041fd1b874476f5: Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi (2022-05-24 23:29:00 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git for you to fetch changes up to c544b281cd3e549a4fcbf4ba9a05a5d72c9557dd: riscv: qemu: Set kernel_comp_addr_r for compressed kernel (2022-05-26 18:42:34 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/12131 ---------------------------------------------------------------- Bin Meng (3): riscv: sifive: unmatched: Adjust for big ramdisk image riscv: sifive: unleashed: Set kernel_comp_addr_r for compressed kernel riscv: qemu: Set kernel_comp_addr_r for compressed kernel Heinrich Schuchardt (1): cmd/sbi: add implementation ID 6 - Coffer Leo Yu-Chi Liang (1): riscv: Clean up asm/io.h Michal Simek (1): riscv: remove CONFIG_ARCH_MAP_SYSMEM from io.h Rick Chen (2): riscv: ae350: Fix OF_BOARD boot failure riscv: ae350: Fix OF_BOARD boot failure arch/riscv/include/asm/io.h | 138 ----------------------------------- board/AndesTech/ax25-ae350/Kconfig | 1 + cmd/riscv/sbi.c | 1 + configs/ae350_rv32_spl_defconfig | 1 + configs/ae350_rv32_spl_xip_defconfig | 1 + configs/ae350_rv64_spl_defconfig | 1 + configs/ae350_rv64_spl_xip_defconfig | 1 + doc/board/sifive/unleashed.rst | 2 - include/configs/qemu-riscv.h | 10 ++- include/configs/sifive-unleashed.h | 10 ++- include/configs/sifive-unmatched.h | 10 +-- 11 files changed, 23 insertions(+), 153 deletions(-) Best regards, Leo

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[PATCH 0/3] Conformance Profiles Table support in U-boot
by Jose Marinho 30 Aug '22

30 Aug '22

The Conformance Profiles Table (ECPT) table will be included in the UEFI specification 2.9+. The ECPT table was introduced in UEFI following the code-first path. The acceptance ticket can be viewed at: https://bugzilla.tianocore.org/show_bug.cgi?id=3591 This patch set implements the ECPT table in U-boot. Jose Marinho (3): efi: Create ECPT table efi: ECPT add EBBRv2.0 conformance profile cmd: efi: efidebug print ECPT table cmd/efidebug.c | 45 +++++++++++++++++++ include/efi_api.h | 14 ++++++ include/efi_loader.h | 9 ++++ lib/efi_loader/Kconfig | 12 +++++ lib/efi_loader/Makefile | 1 + lib/efi_loader/efi_conformance.c | 75 ++++++++++++++++++++++++++++++++ lib/efi_loader/efi_setup.c | 6 +++ 7 files changed, 162 insertions(+) create mode 100644 lib/efi_loader/efi_conformance.c -- 2.25.1

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[PATCH 1/2] xyz-modem: Wait infinitely for initial y-modem packet
by Pali Rohár 29 Aug '22

29 Aug '22

Now when command loady can be aborted / cancelled by CTRL+C, change wait timeout for initial packet to infinite. This would allow user to not be hurry when locating file which want to send. Commands loadb and loads already waits infinitely too. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- common/xyzModem.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/common/xyzModem.c b/common/xyzModem.c index ece25acb183b..d6be489a174b 100644 --- a/common/xyzModem.c +++ b/common/xyzModem.c @@ -449,8 +449,14 @@ xyzModem_stream_open (connection_info_t * info, int *err) return 0; } - while (retries-- > 0) + while (1) { + if (--retries <= 0) + { + retries = xyzModem_MAX_RETRIES; + crc_retries = xyzModem_MAX_RETRIES_WITH_CRC; + xyz.crc_mode = true; + } stat = xyzModem_get_hdr (); if (stat == 0) { -- 2.20.1

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[PATCH] nvme: Do a clean NVMe shutdown
by Hector Martin 27 Aug '22

27 Aug '22

The brute-force controller disable method can end up racing controller initilization and causing a crash when we shut down Apple ANS2 NVMe controllers. Do a proper controlled shutdown, which does block until things are quiesced properly. This is nicer in general for all controllers. Signed-off-by: Hector Martin <marcan(a)marcan.st> --- drivers/nvme/nvme.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index a305305885ec..5fd2fb9ed6a6 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -27,9 +27,8 @@ #define IO_TIMEOUT 30 #define MAX_PRP_POOL 512 -static int nvme_wait_ready(struct nvme_dev *dev, bool enabled) +static int nvme_wait_csts(struct nvme_dev *dev, u32 mask, u32 val) { - u32 bit = enabled ? NVME_CSTS_RDY : 0; int timeout; ulong start; @@ -38,7 +37,7 @@ static int nvme_wait_ready(struct nvme_dev *dev, bool enabled) start = get_timer(0); while (get_timer(start) < timeout) { - if ((readl(&dev->bar->csts) & NVME_CSTS_RDY) == bit) + if ((readl(&dev->bar->csts) & mask) == val) return 0; } @@ -295,7 +294,7 @@ static int nvme_enable_ctrl(struct nvme_dev *dev) dev->ctrl_config |= NVME_CC_ENABLE; writel(dev->ctrl_config, &dev->bar->cc); - return nvme_wait_ready(dev, true); + return nvme_wait_csts(dev, NVME_CSTS_RDY, NVME_CSTS_RDY); } static int nvme_disable_ctrl(struct nvme_dev *dev) @@ -304,7 +303,16 @@ static int nvme_disable_ctrl(struct nvme_dev *dev) dev->ctrl_config &= ~NVME_CC_ENABLE; writel(dev->ctrl_config, &dev->bar->cc); - return nvme_wait_ready(dev, false); + return nvme_wait_csts(dev, NVME_CSTS_RDY, 0); +} + +static int nvme_shutdown_ctrl(struct nvme_dev *dev) +{ + dev->ctrl_config &= ~NVME_CC_SHN_MASK; + dev->ctrl_config |= NVME_CC_SHN_NORMAL; + writel(dev->ctrl_config, &dev->bar->cc); + + return nvme_wait_csts(dev, NVME_CSTS_SHST_MASK, NVME_CSTS_SHST_CMPLT); } static void nvme_free_queue(struct nvme_queue *nvmeq) @@ -904,6 +912,13 @@ free_nvme: int nvme_shutdown(struct udevice *udev) { struct nvme_dev *ndev = dev_get_priv(udev); + int ret; + + ret = nvme_shutdown_ctrl(ndev); + if (ret < 0) { + printf("Error: %s: Shutdown timed out!\n", udev->name); + return ret; + } return nvme_disable_ctrl(ndev); } -- 2.35.1

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[PATCH] pci: Add checks to prevent config space overflow
by Pali Rohár 27 Aug '22

27 Aug '22

PCIe config space has address range 0-4095. So do not allow reading from addresses outside of this range. Lot of U-Boot drivers do not expect that passed value is not in this range. PCI DM read function is exetended to fill read value to all ones or zeros when it fails as U-Boot callers ignores return value. Calling U-Boot command 'pci display.b 0.0.0 0 0x2000' now stops printing config space at the end (before 0x1000 address). Signed-off-by: Pali Rohár <pali(a)kernel.org> --- cmd/pci.c | 16 ++++++++++++++-- drivers/pci/pci-uclass.c | 10 +++++++++- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/cmd/pci.c b/cmd/pci.c index a99e8f8ad6e0..6258699fec81 100644 --- a/cmd/pci.c +++ b/cmd/pci.c @@ -358,6 +358,9 @@ static int pci_cfg_display(struct udevice *dev, ulong addr, if (length == 0) length = 0x40 / byte_size; /* Standard PCI config space */ + if (addr >= 4096) + return 1; + /* Print the lines. * once, and all accesses are with the specified bus width. */ @@ -378,7 +381,10 @@ static int pci_cfg_display(struct udevice *dev, ulong addr, rc = 1; break; } - } while (nbytes > 0); + } while (nbytes > 0 && addr < 4096); + + if (rc == 0 && nbytes > 0) + return 1; return (rc); } @@ -390,6 +396,9 @@ static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size, int nbytes; ulong val; + if (addr >= 4096) + return 1; + /* Print the address, followed by value. Then accept input for * the next value. A non-converted value exits. */ @@ -427,7 +436,10 @@ static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size, addr += size; } } - } while (nbytes); + } while (nbytes && addr < 4096); + + if (nbytes) + return 1; return 0; } diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 89245a271e16..7402079471c8 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -288,6 +288,8 @@ int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset, ops = pci_get_ops(bus); if (!ops->write_config) return -ENOSYS; + if (offset < 0 || offset >= 4096) + return -EINVAL; return ops->write_config(bus, bdf, offset, value, size); } @@ -366,8 +368,14 @@ int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset, struct dm_pci_ops *ops; ops = pci_get_ops(bus); - if (!ops->read_config) + if (!ops->read_config) { + *valuep = pci_conv_32_to_size(~0, offset, size); return -ENOSYS; + } + if (offset < 0 || offset >= 4096) { + *valuep = pci_conv_32_to_size(0, offset, size); + return -EINVAL; + } return ops->read_config(bus, bdf, offset, valuep, size); } -- 2.20.1

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[PATCH 1/2] rockchip: rk3399: fix incorrect boot-device in u-boot, spl-boot-device
by Quentin Schulz 27 Aug '22

27 Aug '22

From: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> On RK3399, mmc0 is eMMC and mmc1 is SD card, c.f. console: MMC: mmc@fe320000: 1, mmc@fe330000: 0 In arch/arm/mach-rockchip/spl-boot-order.c:board_boot_order, the boot_device (BOOT_DEVICE_*) value is gotten from spl_node_to_boot_device function. Said function returns BOOT_DEVICE_MMC1 for mmc0 (eMMC) and BOOT_DEVICE_MMC2 for mmc1 (SD card). Since the SD card controller is at mmc@fe320000, it should be associated with BOOT_DEVICE_MMC2 and not BOOT_DEVICE_MMC1. Same applies to eMMC. Let's fix that by swapping the two BOOT_DEVICEs. Cc: Quentin Schulz <foss+uboot(a)0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> --- arch/arm/mach-rockchip/rk3399/rk3399.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index 691d69dc59..f280cb1dbf 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -180,8 +180,8 @@ const char *spl_decode_boot_device(u32 boot_device) u32 boot_device; const char *ofpath; } spl_boot_devices_tbl[] = { - { BOOT_DEVICE_MMC1, "/mmc@fe320000" }, - { BOOT_DEVICE_MMC2, "/mmc@fe330000" }, + { BOOT_DEVICE_MMC2, "/mmc@fe320000" }, + { BOOT_DEVICE_MMC1, "/mmc@fe330000" }, { BOOT_DEVICE_SPI, "/spi@ff1d0000" }, }; -- 2.36.1

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[PATCH v2 5/5] rockchip: rock-pi-4: dts: spi: Make the index of the spi flash the same in SPL and U-Boot proper
by Xavier Drudis Ferran 27 Aug '22

27 Aug '22

Spi0 is not needed in SPL and SPL could be a little smaller without it, but then the SF_DEFAULT_BOOT would have to be 0 to refer to spi1, and that's confusing, because once U-Boot proper runs, it numbers the bus 1. Add spi0 to the pre-reloc and spl trees so that the flash is always connected to bus 1. Changes since v1: - new patch in v2. Signed-off-by: Xavier Drudis Ferran <xdrudis(a)tinet.cat> Cc: Simon Glass <sjg(a)chromium.org> Cc: Philipp Tomsich <philipp.tomsich(a)vrull.eu> Cc: Kever Yang <kever.yang(a)rock-chips.com> --- arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi index 4c2fe8f6bc..68b6b752d6 100644 --- a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi +++ b/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi @@ -16,6 +16,12 @@ regulator-init-microvolt = <950000>; }; +/* not needed, but nicer to keep SF_DEFAULT_BUS in SPL the same index as in U-Boot proper */ +&spi0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + &spi1 { status = "okay"; spi-max-frequency = <40000000>; -- 2.20.1

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[PATCH] rockchip: rk3308: fix same-as-spl boot order
by John Keeping 27 Aug '22

27 Aug '22

Rockchip SoCs need the boot_devices array defined in order to map the bootloader's value to a U-Boot device. Implement this for rk3308. Signed-off-by: John Keeping <john(a)metanate.com> --- arch/arm/mach-rockchip/rk3308/rk3308.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c b/arch/arm/mach-rockchip/rk3308/rk3308.c index 70fe0d0ac3..dd9109b7c3 100644 --- a/arch/arm/mach-rockchip/rk3308/rk3308.c +++ b/arch/arm/mach-rockchip/rk3308/rk3308.c @@ -8,6 +8,7 @@ #include <asm/global_data.h> #include <asm/io.h> #include <asm/arch/grf_rk3308.h> +#include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/hardware.h> #include <asm/gpio.h> #include <debug_uart.h> @@ -142,6 +143,11 @@ enum { #define GPIO0_A4 4 +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/mmc@ff490000", + [BROM_BOOTSOURCE_SD] = "/mmc@ff480000", +}; + int rk_board_init(void) { static struct rk3308_grf * const grf = (void *)GRF_BASE; -- 2.37.1

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[PATCH] rockchip: rk3308: fix rockchip_dnl_key_pressed() on roc-cc
by John Keeping 27 Aug '22

27 Aug '22

Commit 6aa4fe3912 ("dm: core: Rename and fix uclass_get_by_name_len()") changed uclass_get_device_by_name() to an exact match when previously it behaved as a prefix match. The roc-cc code relied on this prefix match by only specifying part of the device name. Fix this by using the full name including the address. Signed-off-by: John Keeping <john(a)metanate.com> --- board/firefly/firefly-rk3308/roc_cc_rk3308.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/firefly/firefly-rk3308/roc_cc_rk3308.c b/board/firefly/firefly-rk3308/roc_cc_rk3308.c index 28dcc2a690..bdf3cc03dc 100644 --- a/board/firefly/firefly-rk3308/roc_cc_rk3308.c +++ b/board/firefly/firefly-rk3308/roc_cc_rk3308.c @@ -70,7 +70,7 @@ int rockchip_dnl_key_pressed(void) { unsigned int val; - if (adc_channel_single_shot("saradc", 1, &val)) { + if (adc_channel_single_shot("saradc@ff1e0000", 1, &val)) { printf("%s read adc key val failed\n", __func__); return false; } -- 2.37.1

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