June 2022 - U-Boot

linksys wrt1900acs v2 boot problem
by Dilyan Lazarov 07 Jan '23

07 Jan '23

Hi, I have a problem with my linksys wrt1900acs. My main question is this a hardware problem or software problem? Is it possible to address? I have started researching and have tried with "kwboot" under Windows VM - Ubuntu 20 - Linux but I have a problem with usb serial connection. I have tried several things but I understand that it isn't possible to start USB to Serial on a Windows VM. I will expect your response. Thank you in advance. All the best Dilyan I see the following Log from U-Boot with PuTTy under Windows 10: BootROM - 1.73 Booting from NAND flash General initialization - Version: 1.0.0 Detected Device ID 6820 High speed PHY - Version: 2.0 Init RD NAS topology Serdes Lane 3 is USB3 Serdes Lane 4 is SGMII board SerDes lanes topology details: | Lane # | Speed | Type | -------------------------------- | 0 | 06 | SATA0 | | 1 | 05 | PCIe0 | | 2 | 06 | SATA1 | | 3 | 05 | USB3 HOST1 | | 4 | 05 | PCIe1 | | 5 | 00 | SGMII2 | -------------------------------- :** Link is Gen1, check the EP capability PCIe, Idx 0: Link upgraded to Gen2 based on client cpabilities :** Link is Gen1, check the EP capability PCIe, Idx 1: remains Gen1 High speed PHY - Ended Successfully DDR3 Training Sequence - Ver TIP-1.26.0 mvSysEnvGetTopologyUpdateInfo: TWSI Read failed WL Supp: IF 0 busId 1 Failed ! WL Supp: IF 0 failed ddr3TipDynamicWriteLevelingSupp failure ******** DRAM initialization Failed (res 0x1) ******** DDR3 run algorithm - FAILED 0x1 DDR3 Training Sequence - FAILED ********** DRAM initialization failed! ******** -- Dilyan

3 2

kwboot : bug when board stops acking
by SC 06 Jan '23

06 Jan '23

Hi list, I think there's a bug in kwboot. I have a faulty board that stops acking xmodem frames after a certain number of packets and kwboot instead of exiting continues to send frames up to 100%. With the one second retry timer it's very long! More than 2 hours :-( The bug is in the kwboot_xm_sendblock() fonction : https://gitlab.denx.de/u-boot/u-boot/blob/master/tools/kwboot.c#L375 kwboot_tty_recv detects the timeout but the return value is based on the last character received (line 403) The variable c is not initialized so if it keeps the previous value which is ACK => rc=0 => infinite loop There are several ways to fix the bug: * Surround the "switch(c)" with a test: if ( !((rc == -1) && (errno == ETIMEDOUT)) ) { rc = -1; switch (c) { case ACK: rc = 0; break; case NAK: errno = EBADMSG; break; case CAN: errno = ECANCELED; break; default: errno = EPROTO; break; } } return rc; * In the case of a TIMEOUT set c to a specific value and add the case in the switch Do you agree with my diagnosis? What is the best solution to fix this bug? Should I provide a patch? Thank you, Stephane

3 2

Netgear RN102 U-Boot Nand Driver Modification
by Abdus Rainey 06 Jan '23

06 Jan '23

I have recently modded a Netgear RN102 NAND flash from 128 MB to 4096 MB (Samsung k9gbg08u0a) but i have a problem with NAND initialization. I can boot with kwboot which is unique for Armada CPU's. Here is my log from kwboot with my stock mtd0: root@whitepawnxeon:/home/jigsaw/Downloads# kwboot -t -B 115200 /dev/ttyUSB0 -b mtd0stockuboot.img -p Sending boot message. Please reboot the target...- Sending boot image... 0 % [......................................................................] 0 % [......................................................................] 1 % [......................................................................] 1 % [......................................................................] 2 % [......................................................................] 2 % [......................................................................] 3 % [......................................................................] 3 % [......................................................................] 4 % [......................................................................] 5 % [......... General initialization - Version: 1.0.0 High speed PHY - Version: 2.1.4 (COM-PHY-V20) Update PEX Device ID 0x6710 High speed PHY - Ended Successfully 0000 DDR3 Training Sequence - Ver 5.7.1 DDR3 Training Sequence - Run without PBS. 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| __ ) ___ ___ | |_ | | | |___| _ \ / _ \ / _ \| __| | |_| |___| |_) | (_) | (_) | |_ \___/ |____/ \___/ \___/ \__| ** LOADER ** U-Boot 2011.12-gec25d27-dirty (Oct 26 2015 - 16:53:05) Marvell version: v2011.12 2014_T2.0p1 06/23/2015 ReadyNAS-102 V2.0 Board: DB-88F6710-BP SoC: MV6710 A1 CPU: Marvell PJ4B v7 UP (Rev 1) LE CPU @ 1200 [MHz] L2 @ 600 [MHz] TClock @ 200 [MHz] DDR @ 600 [MHz] DDR 16Bit Width, FastPath Memory Access DRAM: 512 MiB Map: Code: 0x1feef000:0x1ff9ef34 BSS: 0x1ffef0a0 Stack: 0x1f9eeef8 Heap: 0x1f9ef000:0x1feef000 NAND: (ID 0xd7ec) nand_get_flash_type: second ID read did not match ac,d7 against ec,52 No NAND device found!!! 0 MiB MMC: MRVL_MMC: 0 *** Warning - readenv() failed, using default environment Initialize and scan all PCI interfaces PEX unit.port(active IF[-first bus]): ------------------------------------------ PEX 0: Root Complex Interface, Detected Link X1, GEN 2.0 PEX 1: Root Complex Interface, Detected Link X1, GEN 2.0 FPU not initialized USB 0: Host Mode USB 1: Host Mode Shutting down unused interfaces: GBE0 SDIO AUDIO TDM Modules/Interfaces Detected: RGMII1 Phy PEX0 (Lane 0) PEX1 (Lane 1) SATA0 (Lane 2) SATA1 (Lane 3) Net: , egiga1 [PRIME] Detect MVT/MP board... Saving Environment to NAND... Erasing Nand... Attempt to erase non page aligned data Power On! Updating env to v3... Saving Environment to NAND... Erasing Nand... Attempt to erase non page aligned data raise: Signal # 8 caught raise: Signal # 8 caught __ __ _ _ | \/ | __ _ _ ____ _____| | | | |\/| |/ _` | '__\ \ / / _ \ | | | | | | (_| | | \ V / __/ | | |_| |_|\__,_|_| \_/ \___|_|_| _ _ ____ _ | | | | | __ ) ___ ___ | |_ | | | |___| _ \ / _ \ / _ \| __| | |_| |___| |_) | (_) | (_) | |_ \___/ |____/ \___/ \___/ \__| ** LOADER ** U-Boot 2011.12-gec25d27-dirty (Oct 26 2015 - 16:53:05) Marvell version: v2011.12 2014_T2.0p1 06/23/2015 ReadyNAS-102 V2.0 Board: DB-88F6710-BP SoC: MV6710 A1 CPU: Marvell PJ4B v7 UP (Rev 1) LE CPU @ 1200 [MHz] L2 @ 600 [MHz] TClock @ 200 [MHz] DDR @ 600 [MHz] DDR 16Bit Width, FastPath Memory Access DRAM: 512 MiB Map: Code: 0x1feef000:0x1ff9ef34 BSS: 0x1ffef0a0 Stack: 0x1f9eeef8 Heap: 0x1f9ef000:0x1feef000 NAND: (ID 0xd7ec) nand_get_flash_type: second ID read did not match ac,d7 against ec,53 No NAND device found!!! 0 MiB MMC: MRVL_MMC: 0 *** Warning - readenv() failed, using default environment Initialize and scan all PCI interfaces PEX unit.port(active IF[-first bus]): ------------------------------------------ PEX 0: Root Complex Interface, Detected Link X1, GEN 2.0 PEX 1: Root Complex Interface, Detected Link X1, GEN 2.0 FPU not initialized USB 0: Host Mode USB 1: Host Mode Shutting down unused interfaces: GBE0 SDIO AUDIO TDM Modules/Interfaces Detected: RGMII1 Phy PEX0 (Lane 0) PEX1 (Lane 1) SATA0 (Lane 2) SATA1 (Lane 3) Net: , egiga1 [PRIME] Detect MVT/MP board... Saving Environment to NAND... Erasing Nand... Attempt to erase non page aligned data Power On! Updating env to v3... Saving Environment to NAND... Erasing Nand... Attempt to erase non page aligned data raise: Signal # 8 caught raise: Signal # 8 caught __ __ _ _ | \/ | __ _ _ ____ _____| | | | |\/| |/ _` | '__\ \ / / _ \ | | | | | | (_| | | \ V / __/ | | |_| |_|\__,_|_| \_/ \___|_|_| _ _ ____ _ | | | | | __ ) ___ ___ | |_ | | | |___| _ \ / _ \ / _ \| __| | |_| |___| |_) | (_) | (_) | |_ \___/ |____/ \___/ \___/ \__| ** LOADER ** U-Boot 2011.12-gec25d27-dirty (Oct 26 2015 - 16:53:05) Marvell version: v2011.12 2014_T2.0p1 06/23/2015 ReadyNAS-102 V2.0 Board: DB-88F6710-BP SoC: MV6710 A1 CPU: Marvell PJ4B v7 UP (Rev 1) LE CPU @ 1200 [MHz] L2 @ 600 [MHz] TClock @ 200 [MHz] DDR @ 600 [MHz] DDR 16Bit Width, FastPath Memory Access DRAM: 512 MiB Map: Code: 0x1feef000:0x1ff9ef34 BSS: 0x1ffef0a0 Stack: 0x1f9eeef8 Heap: 0x1f9ef000:0x1feef000 NAND: (ID 0xd7ec) nand_get_flash_type: second ID read did not match ac,d7 against ec,53 No NAND device found!!! 0 MiB MMC: MRVL_MMC: 0 *** Warning - readenv() failed, using default environment Initialize and scan all PCI interfaces PEX unit.port(active IF[-first bus]): ------------------------------------------ PEX 0: Root Complex Interface, Detected Link X1, GEN 2.0 PEX 1: Root Complex Interface, Detected Link X1, GEN 2.0 FPU not initialized USB 0: Host Mode USB 1: Host Mode Shutting down unused interfaces: GBE0 SDIO AUDIO TDM Modules/Interfaces Detected: RGMII1 Phy PEX0 (Lane 0) PEX1 (Lane 1) SATA0 (Lane 2) SATA1 (Lane 3) Net: , egiga1 [PRIME] As you can see u-boot sees device id and manufacturer id but cannot recognize it.My stock u-boot is very old and i get u-boot source code from Netgear GPL.(ReadyNASOS_V6.6.0_WW_src.zip) In here https://forum.doozan.com/read.php?2,106589,108204#msg-108204 you can see my whole story about this device. Can someone suggest any solution?

2 1

[RESEND PATCH v2 0/3] net: fm: Add support for loading firmware from filesystem
by Sean Anderson 28 Nov '22

28 Nov '22

This adds support for loading Fman firmware from a filesystem using the firmware loader subsystem. It was originally part of [1], but has been split off because it is conceptually separate. [1] https://lore.kernel.org/u-boot/20220324182306.2037094-1-sean.anderson@seco.… Changes in v2: - Split series into two Sean Anderson (3): misc: fs_loader: Add function to get the chosen loader net: fm: Add firmware name parameter net: fm: Support loading firmware from a filesystem arch/arm/mach-k3/common.c | 2 +- arch/arm/mach-omap2/boot-common.c | 2 +- drivers/fpga/socfpga_arria10.c | 24 ++----------------- drivers/misc/fs_loader.c | 27 +++++++++++++++++++++ drivers/net/fm/fm.c | 40 +++++++++++++++++++++++++++---- drivers/net/fm/fm.h | 2 +- drivers/net/fm/init.c | 4 ++-- drivers/qe/Kconfig | 4 ++++ include/fs_loader.h | 12 ++++++++++ 9 files changed, 86 insertions(+), 31 deletions(-) -- 2.35.1.1320.gc452695387.dirty

3 11

Nokia RX51 U-Boot USB support updates?
by Tom Rini 27 Nov '22

27 Nov '22

Hey all, So, the DM_USB migration deadline issue has been addressed by the series here: https://patchwork.ozlabs.org/project/uboot/list/?series=252793&state=* which splits out host and gadget support from the CONFIG_USB symbol itself. The migration deadline was for host support, and as noted, N900 is gadget only. That particular issue is resolved. But investigating that issue lead me to figure out some other problems, that I do need someone to say how will be addressed. Now that the other board removal series has been applied, and then with: https://patchwork.ozlabs.org/project/uboot/patch/20210708014348.4010-1-trin… also applied (for which the maintainer is happy to take), this brings N900 as the last and only user of the "old" musb driver (the "new" musb driver is now almost 9 years old) and also the last and only user of the usbtty driver. I suspect that moving to the "new" MUSB driver, for gadget only, and with that enabling DM_USB_GADGET should be a mechanical affair, so long as you can fit within the space constraints of the platform. I'm not immediately sure how hard it will be to update usbtty.c to modern gadget APIs. If there are size problems, then, well, we need solutions proposed (it's possible that some of the usb-uclass.c code is host-only and needs moving, but that likely won't stop gadget from needing it for gadget related information, to bring up a specific example). It's also likely that the MUSB support needs a little further clean-up for supporting building as gadget-only when there's some common code under a host-only check. What I would like is for someone to step forward and say they'll pick up this work. Is there an immediate deadline? No. I don't think that would be helpful. I'm not going to dictate how long it takes for someone to do the work, that's for the person doing the work to say how long they think it'll take. Thanks all! -- Tom

2 6

[PATCH 1/2] spi: fsl_qspi: Add support for i.MX7ULP
by Ye Li 09 Nov '22

09 Nov '22

Add compatible string and driver data for i.MX7ULP. Meanwhile, the address set to SFA1AD/SFA2AD/SFB1AD/SFB2AD should align with 1KB, because the lowest 10 bits are reserved by the registers definition. For i.MX7ULP which has only 128Bytes AHB buffer, must align it when setting the registers and selecting cs. Signed-off-by: Ye Li <ye.li(a)nxp.com> Reviewed-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> Reviewed-by: Kuldeep Singh <kuldeep.singh(a)nxp.com> --- drivers/spi/fsl_qspi.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index e715f98..d9f531a 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -231,6 +231,15 @@ static const struct fsl_qspi_devtype_data imx6ul_data = { .little_endian = true, }; +static const struct fsl_qspi_devtype_data imx7ulp_data = { + .rxfifo = SZ_64, + .txfifo = SZ_64, + .ahb_buf_size = SZ_128, + .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK | + QUADSPI_QUIRK_USE_TDH_SETTING, + .little_endian = true, +}; + static const struct fsl_qspi_devtype_data ls1021a_data = { .rxfifo = SZ_128, .txfifo = SZ_64, @@ -485,7 +494,7 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave) static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op) { memcpy_fromio(op->data.buf.in, - q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size, + q->ahb_addr + q->selected * ALIGN(q->devtype_data->ahb_buf_size, 0x400), op->data.nbytes); } @@ -589,7 +598,7 @@ static int fsl_qspi_exec_op(struct spi_slave *slave, addr_offset = q->memmap_phy; qspi_writel(q, - q->selected * q->devtype_data->ahb_buf_size + addr_offset, + q->selected * ALIGN(q->devtype_data->ahb_buf_size, 0x400) + addr_offset, base + QUADSPI_SFAR); qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) | @@ -695,13 +704,13 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q) * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD, * SFB2AD accordingly. */ - qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset, + qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) + addr_offset, base + QUADSPI_SFA1AD); - qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset, + qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) * 2 + addr_offset, base + QUADSPI_SFA2AD); - qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset, + qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) * 3 + addr_offset, base + QUADSPI_SFB1AD); - qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset, + qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) * 4 + addr_offset, base + QUADSPI_SFB2AD); q->selected = -1; @@ -799,6 +808,7 @@ static const struct udevice_id fsl_qspi_ids[] = { { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data, }, { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_data, }, { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, }, + { .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data, }, { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, }, { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, }, { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, }, -- 2.7.4

3 4

[PATCH v1] spi: nuvoton: add NPCM PSPI controller driver
by Jim Liu 27 Oct '22

27 Oct '22

Add Nuvoton NPCM BMC Peripheral SPI controller driver. NPCM750 include two general-purpose SPI interface. Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> --- drivers/spi/Kconfig | 5 + drivers/spi/Makefile | 1 + drivers/spi/npcm_pspi.c | 226 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 232 insertions(+) create mode 100644 drivers/spi/npcm_pspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index a1e515cb2b..4e4e05f849 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -289,6 +289,11 @@ config NPCM_FIU_SPI This enables support for the Flash Interface Unit SPI controller in master mode. +config NPCM_PSPI + bool "PSPI driver for Nuvoton NPCM SoC" + help + PSPI driver for NPCM SoC + config NXP_FSPI bool "NXP FlexSPI driver" depends on SPI_MEM diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 06e81b465b..1b843636bc 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o obj-$(CONFIG_NPCM_FIU_SPI) += npcm_fiu_spi.o +obj-$(CONFIG_NPCM_PSPI) += npcm_pspi.o obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o diff --git a/drivers/spi/npcm_pspi.c b/drivers/spi/npcm_pspi.c new file mode 100644 index 0000000000..bd9ac65411 --- /dev/null +++ b/drivers/spi/npcm_pspi.c @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2021 Nuvoton Technology. + */ + +#include <common.h> +#include <dm.h> +#include <spi.h> +#include <clk.h> +#include <asm/gpio.h> +#include <linux/iopoll.h> + +#define MAX_DIV 127 + +/* Register offsets */ +#define PSPI_DATA 0 +#define PSPI_CTL1 2 +#define PSPI_STAT 4 + +/* PSPI_CTL1 fields */ +#define PSPI_CTL1_SPIEN BIT(0) +#define PSPI_CTL1_SCM BIT(7) +#define PSPI_CTL1_SCIDL BIT(8) +#define PSPI_CTL1_SCDV_MASK GENMASK(15, 9) +#define PSPI_CTL1_SCDV_SHIFT 9 + +/* PSPI_STAT fields */ +#define PSPI_STAT_BSY BIT(0) +#define PSPI_STAT_RBF BIT(1) + +struct npcm_pspi_priv { + void __iomem *base; + struct clk clk; + struct gpio_desc cs_gpio; + u32 max_hz; +}; + +static inline void spi_cs_activate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct npcm_pspi_priv *priv = dev_get_priv(bus); + + dm_gpio_set_value(&priv->cs_gpio, 0); +} + +static inline void spi_cs_deactivate(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct npcm_pspi_priv *priv = dev_get_priv(bus); + + dm_gpio_set_value(&priv->cs_gpio, 1); +} + +static inline void npcm_pspi_enable(struct npcm_pspi_priv *priv) +{ + u16 val; + + val = readw(priv->base + PSPI_CTL1); + val |= PSPI_CTL1_SPIEN; + writew(val, priv->base + PSPI_CTL1); +} + +static inline void npcm_pspi_disable(struct npcm_pspi_priv *priv) +{ + u16 val; + + val = readw(priv->base + PSPI_CTL1); + val &= ~PSPI_CTL1_SPIEN; + writew(val, priv->base + PSPI_CTL1); +} + +static int npcm_pspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct npcm_pspi_priv *priv = dev_get_priv(bus); + void __iomem *base = priv->base; + const u8 *tx = dout; + u8 *rx = din; + u32 bytes = bitlen / 8; + u8 tmp; + u32 val; + int i, ret = 0; + + npcm_pspi_enable(priv); + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(dev); + + for (i = 0; i < bytes; i++) { + /* Making sure we can write */ + ret = readb_poll_timeout(base + PSPI_STAT, val, + !(val & PSPI_STAT_BSY), + 1000000); + if (ret < 0) + break; + + if (tx) + writeb(*tx++, base + PSPI_DATA); + else + writeb(0, base + PSPI_DATA); + + /* Wait till write completed */ + ret = readb_poll_timeout(base + PSPI_STAT, val, + !(val & PSPI_STAT_BSY), + 1000000); + if (ret < 0) + break; + + /* Wait till read buffer full */ + ret = readb_poll_timeout(base + PSPI_STAT, val, + (val & PSPI_STAT_RBF), + 1000000); + if (ret < 0) + break; + + tmp = readb(base + PSPI_DATA); + if (rx) + *rx++ = tmp; + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(dev); + + npcm_pspi_disable(priv); + + return ret; +} + +static int npcm_pspi_set_speed(struct udevice *bus, uint speed) +{ + struct npcm_pspi_priv *priv = dev_get_priv(bus); + ulong apb_clock; + u32 divisor; + u16 val; + + apb_clock = clk_get_rate(&priv->clk); + if (!apb_clock) + return -EINVAL; + + if (speed > priv->max_hz) + speed = priv->max_hz; + + divisor = DIV_ROUND_CLOSEST(apb_clock, (2 * speed) - 1); + if (divisor > MAX_DIV) + divisor = MAX_DIV; + + val = readw(priv->base + PSPI_CTL1); + val &= ~PSPI_CTL1_SCDV_MASK; + val |= divisor << PSPI_CTL1_SCDV_SHIFT; + writew(val, priv->base + PSPI_CTL1); + + debug("%s: apb_clock=%lu speed=%d divisor=%u\n", + __func__, apb_clock, speed, divisor); + + return 0; +} + +static int npcm_pspi_set_mode(struct udevice *bus, uint mode) +{ + struct npcm_pspi_priv *priv = dev_get_priv(bus); + u16 pspi_mode, val; + + switch (mode & (SPI_CPOL | SPI_CPHA)) { + case SPI_MODE_0: + pspi_mode = 0; + break; + case SPI_MODE_1: + pspi_mode = PSPI_CTL1_SCM; + break; + case SPI_MODE_2: + pspi_mode = PSPI_CTL1_SCIDL; + break; + case SPI_MODE_3: + pspi_mode = PSPI_CTL1_SCIDL | PSPI_CTL1_SCM; + break; + default: + break; + } + + val = readw(priv->base + PSPI_CTL1); + val &= ~(PSPI_CTL1_SCIDL | PSPI_CTL1_SCM); + val |= pspi_mode; + writew(val, priv->base + PSPI_CTL1); + + return 0; +} + +static int npcm_pspi_probe(struct udevice *bus) +{ + struct npcm_pspi_priv *priv = dev_get_priv(bus); + int node = dev_of_offset(bus); + int ret; + + ret = clk_get_by_index(bus, 0, &priv->clk); + if (ret < 0) + return ret; + + priv->base = dev_read_addr_ptr(bus); + priv->max_hz = dev_read_u32_default(bus, "spi-max-frequency", 0); + gpio_request_by_name_nodev(offset_to_ofnode(node), "cs-gpios", 0, + &priv->cs_gpio, GPIOD_IS_OUT); + + return 0; +} + +static const struct dm_spi_ops npcm_pspi_ops = { + .xfer = npcm_pspi_xfer, + .set_speed = npcm_pspi_set_speed, + .set_mode = npcm_pspi_set_mode, +}; + +static const struct udevice_id npcm_pspi_ids[] = { + { .compatible = "nuvoton,npcm845-pspi"}, + { .compatible = "nuvoton,npcm750-pspi"}, + { } +}; + +U_BOOT_DRIVER(npcm_pspi) = { + .name = "npcm_pspi", + .id = UCLASS_SPI, + .of_match = npcm_pspi_ids, + .ops = &npcm_pspi_ops, + .priv_auto = sizeof(struct npcm_pspi_priv), + .probe = npcm_pspi_probe, +}; -- 2.17.1

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[PATCH] crypto: hash: sw: fix Kconfig dependencies
by Benjamin Bara 26 Oct '22

26 Oct '22

From: Benjamin Bara <Benjamin.Bara(a)skidata.com> Fix SHA512 config name and add missing SHA384 config. Signed-off-by: Benjamin Bara <Benjamin.Bara(a)skidata.com> --- drivers/crypto/hash/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/hash/Kconfig b/drivers/crypto/hash/Kconfig index bf9540eca6..aa355c44be 100644 --- a/drivers/crypto/hash/Kconfig +++ b/drivers/crypto/hash/Kconfig @@ -10,7 +10,8 @@ config HASH_SOFTWARE depends on MD5 depends on SHA1 depends on SHA256 - depends on SHA512_ALGO + depends on SHA384 + depends on SHA512 help Enable driver for hashing operations in software. Currently it support multiple hash algorithm including CRC/MD5/SHA. -- 2.34.1

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[PATCH 0/3] Clarify standalone application support
by Paul Barker 26 Oct '22

26 Oct '22

While looking into the support for u-boot standalone applications I noticed that there was some mis-alignment between the license exception and the files which needed to be included to get a functioning application. I also noticed that the set of SPI access functions defined in the jump table was missing a key function and did not match the set of prototypes defined in the exports header. These patches should rectify the issues I found. Paul Barker (3): Licenses: Clarify exceptions for standalone apps examples: hello_world: Drop inclusion of common header exports: Fix export of SPI access functions Licenses/Exceptions | 12 ++++++++---- examples/standalone/hello_world.c | 1 - include/_exports.h | 4 ++++ include/exports.h | 15 ++++++++++++++- 4 files changed, 26 insertions(+), 6 deletions(-) -- 2.25.1

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[PATCH v3] imx: imx8qm: cgtqmx8: switch to binman
by Oliver Graute 25 Oct '22

25 Oct '22

Switch to use binman to pack images Signed-off-by: Oliver Graute <oliver.graute(a)kococonnector.com> Reviewed-by: Fabio Estevam <festevam(a)denx.de> Reviewed-by: Simon Glass <sjg(a)chromium.org> --- Changes for v3 -added Reviewed-by -rebased on master arch/arm/dts/imx8qm-cgtqmx8.dts | 1 + arch/arm/mach-imx/imx8/Kconfig | 1 + board/congatec/cgtqmx8/imximage.cfg | 4 ++-- configs/cgtqmx8_defconfig | 2 +- doc/board/congatec/cgtqmx8.rst | 3 +-- 5 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/imx8qm-cgtqmx8.dts b/arch/arm/dts/imx8qm-cgtqmx8.dts index 555c357f6f..919d00644f 100644 --- a/arch/arm/dts/imx8qm-cgtqmx8.dts +++ b/arch/arm/dts/imx8qm-cgtqmx8.dts @@ -12,6 +12,7 @@ /memreserve/ 0x80000000 0x00020000; #include "fsl-imx8qm.dtsi" +#include "imx8qm-u-boot.dtsi" / { model = "Congatec QMX8 Qseven series"; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 4414cbc213..3094524460 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -74,6 +74,7 @@ config TARGET_IMX8QM_MEK config TARGET_CONGA_QMX8 bool "Support congatec conga-QMX8 board" + select BINMAN select BOARD_LATE_INIT select SUPPORT_SPL select IMX8QM diff --git a/board/congatec/cgtqmx8/imximage.cfg b/board/congatec/cgtqmx8/imximage.cfg index 5ecde0c530..43035088e3 100644 --- a/board/congatec/cgtqmx8/imximage.cfg +++ b/board/congatec/cgtqmx8/imximage.cfg @@ -4,8 +4,8 @@ */ -/* Boot from SD, sector size 0x400 */ -BOOT_FROM SD 0x400 +BOOT_FROM sd + /* SoC type IMX8QM */ SOC_TYPE IMX8QM /* Append seco container image */ diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig index 2cf882f826..fb334bc4a4 100644 --- a/configs/cgtqmx8_defconfig +++ b/configs/cgtqmx8_defconfig @@ -21,7 +21,7 @@ CONFIG_SYS_LOAD_ADDR=0x80280000 CONFIG_REMAKE_ELF=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y diff --git a/doc/board/congatec/cgtqmx8.rst b/doc/board/congatec/cgtqmx8.rst index bccdef2f16..16711a844d 100644 --- a/doc/board/congatec/cgtqmx8.rst +++ b/doc/board/congatec/cgtqmx8.rst @@ -57,8 +57,7 @@ Build U-Boot $ export ATF_LOAD_ADDR=0x80000000 $ export BL33_LOAD_ADDR=0x80020000 $ make cgtqmx8_defconfig - $ make u-boot.bin - $ make flash.bin + $ make Flash the binary into the SD card --------------------------------- -- 2.17.1

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