June 2022 - U-Boot

[PATCH 0/7] sunxi: F1C100s: enable MMC and SPI in U-Boot proper
by Andre Przywara 18 Jul '22

18 Jul '22

So far the U-Boot proper support for the Allwinner F1C100 family of SoCs was really limited: we could realistically only deal with FEL booting, as there was no storage or network device acessible from U-Boot proper. This series enables the MMC and SPI controller, to be able to actually load something from the device. This is made possible by the updates to the devicetree in Linux, which now describes those devices. The first patch is taken from George's/Yifan's older series, and adds DM_CLK support for the F1C100s. The DM_PINCTRL support was already added with the DM conversion a few weeks back. Patches 2-4 fix the SPI driver clock setup, and add support for the differing SPI clock on the F1C100. Patch 5 updates the devicetree files, freshly synced from linux-next. Patch 6 reverts a hack we introduced back then to fix the reset functionality, with the DT update this is now no longer needed. The final patch adds SPI flash support to the Licheepi Nano defconfig, as these boards mostly ship with SPI flash soldered. Please have a look and test! Cheers, Andre Andre Przywara (6): spi: sunxi: refactor SPI speed/mode programming spi: sunxi: improve SPI clock calculation spi: sunxi: Add support for F1C100s SPI controller sunxi: F1C100s: update DT files from Linux Revert "sunxi: f1c100s: Drop SYSRESET to enable reset functionality" sunxi: licheepi_nano: enable SPI flash George Hilliard (1): clk: sunxi: implement clock driver for suniv f1c100s arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 31 ++++++ arch/arm/dts/suniv-f1c100s.dtsi | 104 ++++++++++++++++-- configs/licheepi_nano_defconfig | 4 +- drivers/clk/sunxi/Kconfig | 7 ++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_f1c100s.c | 74 +++++++++++++ drivers/spi/spi-sunxi.c | 109 +++++++++++-------- 7 files changed, 275 insertions(+), 55 deletions(-) create mode 100644 drivers/clk/sunxi/clk_f1c100s.c -- 2.35.3

2 15

[PATCH v2 0/2] Rockchip: Add option to prevent boot on plug-in
by Chris Morgan 16 Jul '22

16 Jul '22

From: Chris Morgan <macromorgan(a)hotmail.com> Sometimes it is desirable to prevent a board from automatically booting as soon as the power cable is plugged in. For boards with an rk8xx PMIC, (excluding the rk808) we can actually query the power up source. Changes from V1: - Moved a comment as requested to be above a function. - Removed unneeded variable of "plug_in". Chris Morgan (2): power: pmic: rk8xx: Support sysreset shutdown method rockchip: Add option to prevent booting on power plug-in arch/arm/mach-rockchip/Kconfig | 10 ++++ drivers/power/pmic/rk8xx.c | 84 +++++++++++++++++++++++++++++++++- include/power/rk8xx_pmic.h | 3 ++ 3 files changed, 96 insertions(+), 1 deletion(-) -- 2.25.1

4 7

[PATCH v8 0/9] enable menu-driven UEFI variable maintenance
by Masahisa Kojima 15 Jul '22

15 Jul '22

This series add the menu-driven UEFI boot variable maintenance and removable media support in bootmenu. Different from previous version, thie series adds a new U-Boot command "efimenu" to invoke the UEFI boot-related variable maintenance menu. Note that menu-driven UEFI Secure Boot key management patch series will follow. Source code can be cloned with: $ git clone https://git.linaro.org/people/masahisa.kojima/u-boot.git -b kojima/efi_menu_upstream_v8_0618 [Major Changes] - command name is changed from "efimenu" to "eficonfig" - there is detailed chang Masahisa Kojima (9): efi_loader: expose END device path node eficonfig: menu-driven addition of UEFI boot option eficonfig: add "Edit Boot Option" menu entry menu: add KEY_PLUS and KEY_MINUS handling eficonfig: add "Change Boot Order" menu entry eficonfig: add "Delete Boot Option" menu entry bootmenu: add removable media entries doc:bootmenu: add description for UEFI boot support doc:eficonfig: add documentation for eficonfig command cmd/Kconfig | 7 + cmd/Makefile | 1 + cmd/bootmenu.c | 99 +- cmd/eficonfig.c | 1872 ++++++++++++++++++++++++++++++ common/menu.c | 6 + doc/usage/cmd/bootmenu.rst | 74 ++ doc/usage/cmd/eficonfig.rst | 50 + doc/usage/index.rst | 1 + include/efi_config.h | 91 ++ include/efi_loader.h | 63 + include/menu.h | 2 + lib/efi_loader/efi_bootmgr.c | 4 + lib/efi_loader/efi_boottime.c | 52 +- lib/efi_loader/efi_console.c | 78 ++ lib/efi_loader/efi_device_path.c | 2 +- lib/efi_loader/efi_disk.c | 11 + lib/efi_loader/efi_file.c | 75 +- 17 files changed, 2437 insertions(+), 51 deletions(-) create mode 100644 cmd/eficonfig.c create mode 100644 doc/usage/cmd/eficonfig.rst create mode 100644 include/efi_config.h -- 2.17.1

4 21

[PATCH 0/4] mtd: spi: arm: rk3399: rock-pi-4: u-boot/next Support SPI NOR Flash in Rock Pi 4 (XTX xt25f32b)
by Xavier Drudis Ferran 15 Jul '22

15 Jul '22

The Radxa Rock Pi 4 board is sold from revision 1.4 with a soldered 4Mb SPI NOR Flash. This series allows to use it from U-Boot and boot from it. This series applies to u-boot/next. I have patches for master I can send if requested. I can for custodian trees, but i'd need to adapt and retest. I'm not sure other people will need all of the patches. It may depend on what other components are in use. I needed them and I'm sending them thinking they'd improve U-Boot, but I'm new here so it's likely I'm overseeing something. You may of course take all, some or none of them. I've tested with flashrom on linux-libre 5.15.42 (/dev/mtd0) with this patch applied to the kernel. (not all of it would be needed, just for "full disclosure" on tests) diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 100a76916..7fdb22a85 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -14,6 +14,13 @@ aliases { mmc0 = &sdmmc; mmc1 = &sdhci; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + spi5 = &spi5; + }; chosen { @@ -128,6 +135,12 @@ regulator-max-microvolt = <1400000>; vin-supply = <&vcc5v0_sys>; }; + + sound { + compatible = "audio-graph-card"; + label = "rockchip,rk33999"; + dais = <&i2s0_p0>; + }; }; &cpu_l0 { @@ -419,9 +432,28 @@ }; &i2c1 { - i2c-scl-rising-time-ns = <300>; i2c-scl-falling-time-ns = <15>; - status = "okay"; + i2c-scl-rising-time-ns = <300>; + status = "okay"; + + es8316: codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det_pin>; + interrupt-parent = <&gpio1>; + interrupts = <RK_PA1 IRQ_TYPE_LEVEL_HIGH>; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_p0_0>; + }; + }; + }; + }; &i2c3 { @@ -441,6 +473,15 @@ rockchip,capture-channels = <2>; rockchip,playback-channels = <2>; status = "okay"; + + i2s0_p0: port { + i2s0_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; + }; &i2s1 { @@ -481,6 +522,7 @@ vpcie1v8-supply = <&vcc_1v8>; vpcie3v3-supply = <&vcc3v3_pcie>; status = "okay"; + max-link-speed = <2>; }; &pinctrl { @@ -500,7 +542,7 @@ pcie { pcie_pwr_en: pcie-pwr-en { - rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_20ma>; }; }; @@ -556,6 +598,20 @@ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + es8316 { + hp_det_pin: hp-det-pin { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + i2s0 { + i2s_8ch_mclk_pin: i2s-8ch-mclk-pin { + rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + }; &pwm2 { @@ -596,6 +652,7 @@ }; &sdhci { + max-frequency = <150000000>; bus-width = <8>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts index 6c63e6170..c04fee0f5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts @@ -44,3 +44,29 @@ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; }; }; + +&spi1 { + max-freq = <40000000>; + status = "okay"; + + spiflash: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <40000000>; + spi-cpol; + spi-cpha; + + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + + loader@0 { + label = "loader"; + reg = <0x0 0x400000>; + }; + }; + }; +}; \ No newline at end of file diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index 6b904e439..e344077e3 100644 --- a/drivers/mtd/spi-nor/Makefile +++ b/drivers/mtd/spi-nor/Makefile @@ -17,6 +17,7 @@ spi-nor-objs += sst.o spi-nor-objs += winbond.o spi-nor-objs += xilinx.o spi-nor-objs += xmc.o +spi-nor-objs += xtx.o obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o obj-$(CONFIG_MTD_SPI_NOR) += controllers/ diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index cc08bd707..7ab768309 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -1846,6 +1846,7 @@ static const struct spi_nor_manufacturer *manufacturers[] = { &spi_nor_winbond, &spi_nor_xilinx, &spi_nor_xmc, + &spi_nor_xtx, }; static const struct flash_info * diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 3348e1dd1..fd2771fbe 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -489,6 +489,7 @@ extern const struct spi_nor_manufacturer spi_nor_sst; extern const struct spi_nor_manufacturer spi_nor_winbond; extern const struct spi_nor_manufacturer spi_nor_xilinx; extern const struct spi_nor_manufacturer spi_nor_xmc; +extern const struct spi_nor_manufacturer spi_nor_xtx; extern const struct attribute_group *spi_nor_sysfs_groups[]; diff --git a/drivers/mtd/spi-nor/xtx.c b/drivers/mtd/spi-nor/xtx.c new file mode 100644 index 000000000..3db8bfd93 --- /dev/null +++ b/drivers/mtd/spi-nor/xtx.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022, Xavier Drudis Ferran + * (based on eon.c from this directory + * and drivers/mtd/spi-nor/spi-nor.c from https://github.com/radxa/kernel.git ) + */ + +#include <linux/mtd/spi-nor.h> + +#include "core.h" + +static const struct flash_info xtx_parts[] = { + /* XTX -- xt25xxx */ + { "xt25f32b", INFO(0x0b4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ) }, + { "xt25f128b", INFO(0x0b4018, 0, 64 * 1024, 256, SECT_4K) }, +}; + +const struct spi_nor_manufacturer spi_nor_xtx = { + .name = "xtx", + .parts = xtx_parts, + .nparts = ARRAY_SIZE(xtx_parts), +};

2 6

[PATCH v3 0/2] usb: dwc3: add a SPL_USB_DWC3_GENERIC option for the dwc3 driver
by Angus Ainslie 14 Jul '22

14 Jul '22

Changes since v2: Add a second patch to deal with CI failures due to the new options. Changes since v1: Updated Kconfig depends Angus Ainslie (2): usb: dwc3: add a SPL_USB_DWC3_GENERIC option for the dwc3 driver configs: get rid of build warnings due to SPL_USB_DWC3_GENERIC configs/am43xx_evm_defconfig | 2 ++ configs/am43xx_evm_usbhost_boot_defconfig | 2 ++ configs/am43xx_hs_evm_defconfig | 2 ++ configs/am57xx_hs_evm_usb_defconfig | 2 ++ configs/am65x_evm_a53_defconfig | 2 ++ configs/am65x_evm_r5_usbdfu_defconfig | 2 ++ configs/dra7xx_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_usb_defconfig | 2 ++ drivers/usb/dwc3/Kconfig | 7 +++++++ drivers/usb/dwc3/Makefile | 2 +- 11 files changed, 26 insertions(+), 1 deletion(-) -- 2.34.1

2 9

[PATCH v2] xilinx: zynqmp: Do not use 0 as spl bss start address
by Stefan Herbrechtsmeier 14 Jul '22

14 Jul '22

From: Stefan Herbrechtsmeier <stefan.herbrechtsmeier(a)weidmueller.com> Do not use 0 as address for memory because of the special meaning for pointers (null pointer). Change the spl bss start address to the second page. Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier(a)weidmueller.com> --- The problem was discovered with a static array initialized with zero. The compiler placed the array at address 0 and thereby a pointer to the array was interpreted as null pointer. Changes in v2: - Rework commit message and replace address null by 0 include/configs/xilinx_zynqmp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index f25d796a1e..21a5cf1617 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -209,7 +209,7 @@ #define CONFIG_SPL_MAX_SIZE 0x40000 /* Just random location in OCM */ -#define CONFIG_SPL_BSS_START_ADDR 0x0 +#define CONFIG_SPL_BSS_START_ADDR 0x1000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 #if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) -- 2.30.2

5 12

[PATCH v2 1/3] mmc: stm32_sdmmc2: cosmetic: rename stm32_sdmmc_bind
by Patrick Delaunay 13 Jul '22

13 Jul '22

Rename stm32_sdmmc_bind to stm32_sdmmc2_bind as all other functions in SDMMCv2 driver series-changes: 2 - fix typo in commit message (/oter function/other functions/) Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- (no changes since v1) drivers/mmc/stm32_sdmmc2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index 81b07609a91..e3853b7fbfb 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -763,7 +763,7 @@ clk_free: return ret; } -static int stm32_sdmmc_bind(struct udevice *dev) +static int stm32_sdmmc2_bind(struct udevice *dev) { struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); @@ -781,7 +781,7 @@ U_BOOT_DRIVER(stm32_sdmmc2) = { .of_match = stm32_sdmmc2_ids, .ops = &stm32_sdmmc2_ops, .probe = stm32_sdmmc2_probe, - .bind = stm32_sdmmc_bind, + .bind = stm32_sdmmc2_bind, .priv_auto = sizeof(struct stm32_sdmmc2_priv), .plat_auto = sizeof(struct stm32_sdmmc2_plat), }; -- 2.25.1

2 6

[PATCH v2 01/10] i2c: stm32: add support for the st,stm32mp13 SOC
by Patrick Delaunay 13 Jul '22

13 Jul '22

The stm32mp13 soc differs from the stm32mp15 in terms of clear register offset for controlling the FMP (Fast Mode Plus). Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- (no changes since v1) drivers/i2c/stm32f7_i2c.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c index c6ae65badb7..bf2a6c9b4bd 100644 --- a/drivers/i2c/stm32f7_i2c.c +++ b/drivers/i2c/stm32f7_i2c.c @@ -267,6 +267,10 @@ static const struct stm32_i2c_data stm32mp15_data = { .fmp_clr_offset = 0x40, }; +static const struct stm32_i2c_data stm32mp13_data = { + .fmp_clr_offset = 0x4, +}; + static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv) { struct stm32_i2c_regs *regs = i2c_priv->regs; @@ -957,6 +961,7 @@ static const struct dm_i2c_ops stm32_i2c_ops = { static const struct udevice_id stm32_i2c_of_match[] = { { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_data }, { .compatible = "st,stm32mp15-i2c", .data = (ulong)&stm32mp15_data }, + { .compatible = "st,stm32mp13-i2c", .data = (ulong)&stm32mp13_data }, {} }; -- 2.25.1

2 20

[PATCH] arm: dts: stm32mp1: Drop fastboot and stm32prog trigger gpios on DHCOM
by Johann Neuhauser 13 Jul '22

13 Jul '22

PA13 and PA14 are used for USB power control and can't be used to enforce fastboot or stm32prog mode by pressing a button. Defining CONFIG_FASTBOOT/CONFIG_CMD_STM32PROG without this patch applied results in fastboot/stm32prog always starting, because PA13/PA14 are always low during boot. So drop the wrong trigger gpios definitions. Signed-off-by: Johann Neuhauser <jneuhauser(a)dh-electronics.com> --- arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index d73967ac1b5d..ee747a52bb7c 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -27,8 +27,6 @@ config { u-boot,boot-led = "heartbeat"; u-boot,error-led = "error"; - st,fastboot-gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; - st,stm32prog-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; dh,som-coding-gpios = <&gpiof 12 0>, <&gpiof 13 0>, <&gpiof 15 0>; dh,ddr3-coding-gpios = <&gpioz 6 0>, <&gpioz 7 0>; }; -- 2.30.2

4 4

minor regression in U-Boot 2022.04
by Daniel Golle 13 Jul '22

13 Jul '22

Hi! I'm about to bump the U-Boot build for MediaTek MT7622 boards in OpenWrt to U-Boot 2022.04. While practially everything seems to work fine, I've noticed an error message early in the serial output which was not present in U-Boot 2022.01. It is even followed by a bunch of random characters which are different on every boot (hints to a read-out-of-bounds on uninitialzed memory or the like): serial_mtk serial@11002000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19�CC� At another boot: serial_mtk serial@11002000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19��H�H�UI��$&L�1.04-OpenWrt-r19423-c9c2b01b84 (Apr 11 2022 - 19:25:34 +0000) This is probably related to recent changes in dm and pinctrl, as there haven't been any changes to mtk_serial itself. Log including ROM and ARM Trusted Firmware A serial output: F0: 102B 0000 F6: 0000 0000 V0: 0000 0000 [0001] 00: 0000 0000 BP: 0400 0041 [0000] G0: 1190 0000 T0: 0000 02AD [000F] Jump to BL NOTICE: BL2: v2.4(release):OpenWrt v2021-05-08-d2c75b21-2 (mt7622-snand-2ddr) NOTICE: BL2: Built : 12:03:10, Apr 11 2022 NOTICE: SPI-NAND: W25N01GV (128MB) NOTICE: BL2: Booting BL31 NOTICE: BL31: v2.4(release):OpenWrt v2021-05-08-d2c75b21-2 (mt7622-snand-2ddr) NOTICE: BL31: Built : 12:03:10, Apr 11 2022 serial_mtk serial@11002000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19�CC� U-Boot 2022.04-OpenWrt-r19423-c9c2b01b84 (Apr 11 2022 - 19:25:34 +0000) CPU: MediaTek MT7622 Model: mt7622-bpi-r64 DRAM: 1 GiB Core: 55 devices, 18 uclasses, devicetree: separate MMC: mmc@11230000: 0, mmc@11240000: 1 Loading Environment from UBI... SPI-NAND: W25N01GV (128MB) ... I will most likely not investigate this any further, but thought it might be good to let you know. Best regards Daniel

2 3