June 2022 - U-Boot

[PATCH 1/1] CVE-2022-30767: unbounded memcpy with a failed length check
by gerbert 06 Jun '22

06 Jun '22

This patch tries to fix a CVE-2019-14196 fix In if-condition, where NFSV2_FLAG is checked, memcpy call is performed to transfer a reply data of NFS_FHSIZE size. Since the data field in struct rpc_t structure has the size of (1024 / 4) + 26 = 282, while NFS_FHSIZE is only 32, it won't lead to out-of-bounds write (considering the size of data array won't change in the future). What concerns if-condition for NFSV3_FLAG, since filefh3_length is signed integer, it may carry negative values which may lead to memcpy failure, so in this case we need to introduce not only boundary check (filefh3_length > NFS3_FHSIZE), which exists, but also make sure that filefh3_length is not negative. Signed-off-by: gerbert <gerbert(a)users.noreply.github.com> --- net/nfs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/net/nfs.c b/net/nfs.c index 9152ab742e..5186130ea9 100644 --- a/net/nfs.c +++ b/net/nfs.c @@ -566,13 +566,13 @@ static int nfs_lookup_reply(uchar *pkt, unsigned len) } if (supported_nfs_versions & NFSV2_FLAG) { - if (((uchar *)&(rpc_pkt.u.reply.data[0]) - (uchar *)(&rpc_pkt) + NFS_FHSIZE) > len) - return -NFS_RPC_DROP; memcpy(filefh, rpc_pkt.u.reply.data + 1, NFS_FHSIZE); } else { /* NFSV3_FLAG */ filefh3_length = ntohl(rpc_pkt.u.reply.data[1]); + if (filefh3_length < 0) + return -NFS_RPC_DROP; if (filefh3_length > NFS3_FHSIZE) - filefh3_length = NFS3_FHSIZE; + filefh3_length = NFS3_FHSIZE; memcpy(filefh, rpc_pkt.u.reply.data + 2, filefh3_length); } -- 2.32.0

2 2

[PATCH] doc: update mail author for st-dt.rst
by Patrick Delaunay 06 Jun '22

06 Jun '22

Update author email address with the one dedicated to upstream activities. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- doc/board/st/st-dt.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/board/st/st-dt.rst b/doc/board/st/st-dt.rst index 3dade1681f..67e16ef165 100644 --- a/doc/board/st/st-dt.rst +++ b/doc/board/st/st-dt.rst @@ -1,5 +1,5 @@ .. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -.. sectionauthor:: Patrick Delaunay <patrick.delaunay(a)st.com> +.. sectionauthor:: Patrick Delaunay <patrick.delaunay(a)foss.st.com> U-Boot device tree bindings ---------------------------- -- 2.25.1

2 1

[PATCH] configs: fsl: add missing SYS_FMAN_FW_ADDR defines
by Camelia Groza 06 Jun '22

06 Jun '22

From: Camelia Groza <camelia.groza(a)nxp.com> Two defconfigs were missed when transitioning the SYS_FMAN_FW_ADDR symbol to Kconfig. CONFIG_SYS_FMAN_FW_ADDR is currently initialized to 0 by default on these builds, which prevents the firmware from loading. Add the correct symbols to these defconfigs. Fixes: a97a071d10d2b ("configs: fsl: migrate FMAN/QE specific defines to Kconfig") Signed-off-by: Camelia Groza <camelia.groza(a)nxp.com> --- configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig | 1 + configs/ls1046afrwy_tfa_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig index 3cbe1b7c10f0..fddb02e556ab 100644 --- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig @@ -57,6 +57,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_DM_SCSI=y diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index 2c198cd913ad..23ceb185f497 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -64,6 +64,7 @@ CONFIG_PHY_VITESSE=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y +CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCI=y CONFIG_DM_PCI_COMPAT=y -- 2.17.1

2 1

[PATCH v1] fdt: Add U-Boot version to chosen node
by Francesco Dolcini 06 Jun '22

06 Jun '22

Add a new device tree property "u-boot,version" in the chosen node to pass the U-Boot version to the operating system. This can be useful to implement a firmware upgrade procedure from the operating system. Signed-off-by: Francesco Dolcini <francesco.dolcini(a)toradex.com> --- common/fdt_support.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/common/fdt_support.c b/common/fdt_support.c index 7e9e6542041d..8c18af2ce156 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -19,6 +19,7 @@ #include <fdt_support.h> #include <exports.h> #include <fdtdec.h> +#include <version.h> /** * fdt_getprop_u32_default_node - Return a node's property or a default @@ -305,6 +306,15 @@ int fdt_chosen(void *fdt) } } + /* add u-boot version */ + err = fdt_setprop(fdt, nodeoffset, "u-boot,version", PLAIN_VERSION, + strlen(PLAIN_VERSION) + 1); + if (err < 0) { + printf("WARNING: could not set u-boot,version %s.\n", + fdt_strerror(err)); + return err; + } + return fdt_fixup_stdout(fdt, nodeoffset); } -- 2.25.1

3 5

[PATCH v2 1/3] drivers: tee: optee: remove unused probe local variable
by Etienne Carriere 06 Jun '22

06 Jun '22

Removes local variable child in optee_probe() that is not used. Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Signed-off-by: Etienne Carriere <etienne.carriere(a)linaro.org> --- New change not in v1 series. --- drivers/tee/optee/core.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/tee/optee/core.c b/drivers/tee/optee/core.c index a89d62aaf0..c1f5fc4c7a 100644 --- a/drivers/tee/optee/core.c +++ b/drivers/tee/optee/core.c @@ -642,7 +642,6 @@ static int optee_probe(struct udevice *dev) { struct optee_pdata *pdata = dev_get_plat(dev); u32 sec_caps; - struct udevice *child; int ret; if (!is_optee_api(pdata->invoke_fn)) { @@ -673,7 +672,7 @@ static int optee_probe(struct udevice *dev) * only bind the drivers associated to the supported OP-TEE TA */ if (IS_ENABLED(CONFIG_RNG_OPTEE)) { - ret = device_bind_driver(dev, "optee-rng", "optee-rng", &child); + ret = device_bind_driver(dev, "optee-rng", "optee-rng", NULL); if (ret) return ret; } -- 2.25.1

2 5

[PATCH] arm64: zynqmp: Add support for kr260 revA/B boards
by Michal Simek 06 Jun '22

06 Jun '22

From: Michal Simek <michal.simek(a)xilinx.com> Board is using kv260 design for couple of parts defined by spec like i2c eeproms, ina260, uart, etc. Board has 4 gems. One gem connected via PS SGMII(GT), another PS RGMII(MIO) and 2 via EMIO. First two shares the same MIO lines for PHYs. PL based one have separate EMIO lines via PL. Also two USB 3.0 with usb hubs are present. USB phys and USB hubs should have separate reset line. The first usb0 hub also has USB-SD controller (usb2244) connected to port 0. To test compatibility with k26 you can run: fdtoverlay -o /tmp/output.dtb -i arch/arm/dts/zynqmp-sm-k26-revA.dtb \ arch/arm/dts/zynqmp-sck-kr-g-revA.dtbo Also add support for kr260-revB board. Based on FRU it is revision B but schematics can be label as revA03. Changes in revB are: - SFP light - GEM2/3 TX_CLK fixes - PMOD/RPI connector fixes - Replace si5332 with oscilators Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/dts/Makefile | 2 + arch/arm/dts/zynqmp-sck-kr-g-revA.dts | 382 ++++++++++++++++++++++++++ arch/arm/dts/zynqmp-sck-kr-g-revB.dts | 382 ++++++++++++++++++++++++++ 3 files changed, 766 insertions(+) create mode 100644 arch/arm/dts/zynqmp-sck-kr-g-revA.dts create mode 100644 arch/arm/dts/zynqmp-sck-kr-g-revB.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 83630af4f67b..cda7fc37c217 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -342,6 +342,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-mini-qspi.dtb \ zynqmp-sm-k26-revA.dtb \ zynqmp-smk-k26-revA.dtb \ + zynqmp-sck-kr-g-revA.dtbo \ + zynqmp-sck-kr-g-revB.dtbo \ zynqmp-sck-kv-g-revA.dtbo \ zynqmp-sck-kv-g-revB.dtbo \ zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb \ diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dts b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts new file mode 100644 index 000000000000..7be02ab29fa1 --- /dev/null +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dts @@ -0,0 +1,382 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for KR260 revA Carrier Card + * + * (C) Copyright 2021, Xilinx, Inc. + * + * Michal Simek <michal.simek(a)xilinx.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "xlnx,zynqmp-sk-kr260-revA", + "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; + + ina260-u14 { + compatible = "iio-hwmon"; + io-channels = <&u14 0>, <&u14 1>, <&u14 2>; + }; + + si5332_0: si5332_0 { /* u17 - GEM0/1 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + si5332_1: si5332_1 { /* u17 - DP */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + si5332_2: si5332_2 { /* u17 - USB */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + si5332_3: si5332_3 { /* u17 - SFP+ */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + }; + + si5332_4: si5332_4 { /* u17 - GEM2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + si5332_5: si5332_5 { /* u17 - GEM3 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + + u14: ina260@40 { /* u14 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; + + slg7xl45106: gpio@11 { /* u19 - reset logic */ + compatible = "dlg,slg7xl45106"; + reg = <0x11>; + label = "resetchip"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", + "SD_RESET_B", "USB0_HUB_RESET_B", + "USB1_HUB_RESET_B", "PS_GEM0_RESET_B", + "PS_GEM1_RESET_B", ""; + }; + + i2c-mux@74 { /* u18 */ + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + usbhub_i2c0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + usbhub_i2c1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + /* Bus 2/3 are not connected */ + }; + + /* si5332@6a - u17 - clock-generator */ +}; + +/* GEM SGMII/DP and USB 3.0 */ +&psgtr { + status = "okay"; + /* gem0/1, dp, usb */ + clocks = <&si5332_0>, <&si5332_1>, <&si5332_2>; + clock-names = "ref0", "ref1", "ref2"; +}; + +&zynqmp_dpsub { + status = "okay"; + phy-names = "dp-phy0"; + phys = <&psgtr 1 PHY_TYPE_DP 0 1>; + assigned-clock-rates = <27000000>, <25000000>, <300000000>; +}; + +&zynqmp_dpdma { + status = "okay"; + assigned-clock-rates = <600000000>; +}; + +&usb0 { /* mio52 - mio63 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; + assigned-clock-rates = <250000000>, <20000000>; + + usbhub0: usb-hub { /* u43 */ + i2c-bus = <&usbhub_i2c0>; + compatible = "microchip,usb5744"; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + usb2244: usb-sd { /* u38 */ + compatible = "microchip,usb2244"; + reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>; + }; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; +}; + +&usb1 { /* mio64 - mio75 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; + reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; + assigned-clock-rates = <250000000>, <20000000>; + + usbhub1: usb-hub { /* u84 */ + i2c-bus = <&usbhub_i2c1>; + compatible = "microchip,usb5744"; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; +}; + +&dwc3_1 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; +}; + +&gem0 { /* mdio mio50/51 */ + status = "okay"; + phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; + phy-handle = <&phy0>; + phy-mode = "sgmii"; + is-internal-pcspma; +}; + +&gem1 { /* mdio mio50/51, gem mio38 - mio49 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem1_default>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@4 { /* u81 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <4>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <100>; + reset-deassert-us = <280>; + reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; + }; + phy1: ethernet-phy@8 { /* u36 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <8>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <100>; + reset-deassert-us = <280>; + reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* gem2/gem3 via PL with phys u79@2 and u80@3 */ + +&pinctrl0 { /* required by spec */ + status = "okay"; + + pinctrl_uart1_default: uart1-default { + conf { + groups = "uart1_9_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO36"; + bias-disable; + }; + + mux { + groups = "uart1_9_grp"; + function = "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups = "i2c1_6_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "i2c1_6_grp"; + function = "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + conf { + groups = "gpio0_24_grp", "gpio0_25_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_24_grp", "gpio0_25_grp"; + function = "gpio0"; + }; + }; + + pinctrl_gem1_default: gem1-default { + conf { + groups = "ethernet1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO44", "MIO46", "MIO48"; + bias-high-impedance; + low-power-disable; + }; + + conf-bootstrap { + pins = "MIO45", "MIO47", "MIO49"; + bias-disable; + low-power-disable; + }; + + conf-tx { + pins = "MIO38", "MIO39", "MIO40", + "MIO41", "MIO42", "MIO43"; + bias-disable; + low-power-enable; + }; + + conf-mdio { + groups = "mdio1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + bias-disable; + }; + + mux-mdio { + function = "mdio1"; + groups = "mdio1_0_grp"; + }; + + mux { + function = "ethernet1"; + groups = "ethernet1_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups = "usb0_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + }; + + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + }; + + pinctrl_usb1_default: usb1-default { + conf { + groups = "usb1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO64", "MIO65", "MIO67"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", + "MIO72", "MIO73", "MIO74", "MIO75"; + bias-disable; + }; + + mux { + groups = "usb1_0_grp"; + function = "usb1"; + }; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dts b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts new file mode 100644 index 000000000000..56effb5e21a9 --- /dev/null +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dts @@ -0,0 +1,382 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for KR260 revB Carrier Card (A03 revision) + * + * (C) Copyright 2021 - 2022, Xilinx, Inc. + * + * Michal Simek <michal.simek(a)xilinx.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/pinctrl/pinctrl-zynqmp.h> + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "xlnx,zynqmp-sk-kr260-revB", + "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp"; + + ina260-u14 { + compatible = "iio-hwmon"; + io-channels = <&u14 0>, <&u14 1>, <&u14 2>; + }; + + clk_125: clock0 { /* u87 - GEM0/1 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk_27: clock1 { /* u86 - DP */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + clk_26: clock2 { /* u89 - USB */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clk_156: clock3 { /* u90 - SFP+ */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <156250000>; + }; + + clk_25_0: clock4 { /* u92/u91 - GEM2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + clk_25_1: clock5 { /* u92/u91 - GEM3 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; +}; + +&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_default>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + + u14: ina260@40 { /* u14 */ + compatible = "ti,ina260"; + #io-channel-cells = <1>; + label = "ina260-u14"; + reg = <0x40>; + }; + + slg7xl45106: gpio@11 { /* u19 - reset logic */ + compatible = "dlg,slg7xl45106"; + reg = <0x11>; + label = "resetchip"; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", + "SD_RESET_B", "USB0_HUB_RESET_B", + "USB1_HUB_RESET_B", "PS_GEM0_RESET_B", + "PS_GEM1_RESET_B", ""; + }; + + i2c-mux@74 { /* u18 */ + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + usbhub_i2c0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + usbhub_i2c1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + /* Bus 2/3 are not connected */ + }; + + /* si5332@6a - u17 - clock-generator */ +}; + +/* GEM SGMII/DP and USB 3.0 */ +&psgtr { + status = "okay"; + /* gem0/1, dp, usb */ + clocks = <&clk_125>, <&clk_27>, <&clk_26>; + clock-names = "ref0", "ref1", "ref2"; +}; + +&zynqmp_dpsub { + status = "okay"; + phy-names = "dp-phy0"; + phys = <&psgtr 1 PHY_TYPE_DP 0 1>; + assigned-clock-rates = <27000000>, <25000000>, <300000000>; +}; + +&zynqmp_dpdma { + status = "okay"; + assigned-clock-rates = <600000000>; +}; + +&usb0 { /* mio52 - mio63 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 2 PHY_TYPE_USB3 0 2>; + reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>; + assigned-clock-rates = <250000000>, <20000000>; + + usbhub0: usb-hub { /* u43 */ + i2c-bus = <&usbhub_i2c0>; + compatible = "microchip,usb5744"; + reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; + }; + + usb2244: usb-sd { /* u38 */ + compatible = "microchip,usb2244"; + reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>; + }; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; +}; + +&usb1 { /* mio64 - mio75 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_default>; + phy-names = "usb3-phy"; + phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; + reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>; + assigned-clock-rates = <250000000>, <20000000>; + + usbhub1: usb-hub { /* u84 */ + i2c-bus = <&usbhub_i2c1>; + compatible = "microchip,usb5744"; + reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>; + }; +}; + +&dwc3_1 { + status = "okay"; + dr_mode = "host"; + snps,usb3_lpm_capable; + maximum-speed = "super-speed"; +}; + +&gem0 { /* mdio mio50/51 */ + status = "okay"; + phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; + phy-handle = <&phy0>; + phy-mode = "sgmii"; + is-internal-pcspma; +}; + +&gem1 { /* mdio mio50/51, gem mio38 - mio49 */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gem1_default>; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@4 { /* u81 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <4>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <100>; + reset-deassert-us = <280>; + reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; + }; + phy1: ethernet-phy@8 { /* u36 */ + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <8>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + reset-assert-us = <100>; + reset-deassert-us = <280>; + reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>; + }; + }; +}; + +/* gem2/gem3 via PL with phys u79@2 and u80@3 */ + +&pinctrl0 { /* required by spec */ + status = "okay"; + + pinctrl_uart1_default: uart1-default { + conf { + groups = "uart1_9_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + drive-strength = <12>; + }; + + conf-rx { + pins = "MIO37"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO36"; + bias-disable; + }; + + mux { + groups = "uart1_9_grp"; + function = "uart1"; + }; + }; + + pinctrl_i2c1_default: i2c1-default { + conf { + groups = "i2c1_6_grp"; + bias-pull-up; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "i2c1_6_grp"; + function = "i2c1"; + }; + }; + + pinctrl_i2c1_gpio: i2c1-gpio { + conf { + groups = "gpio0_24_grp", "gpio0_25_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + mux { + groups = "gpio0_24_grp", "gpio0_25_grp"; + function = "gpio0"; + }; + }; + + pinctrl_gem1_default: gem1-default { + conf { + groups = "ethernet1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO44", "MIO46", "MIO48"; + bias-high-impedance; + low-power-disable; + }; + + conf-bootstrap { + pins = "MIO45", "MIO47", "MIO49"; + bias-disable; + low-power-disable; + }; + + conf-tx { + pins = "MIO38", "MIO39", "MIO40", + "MIO41", "MIO42", "MIO43"; + bias-disable; + low-power-enable; + }; + + conf-mdio { + groups = "mdio1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + bias-disable; + }; + + mux-mdio { + function = "mdio1"; + groups = "mdio1_0_grp"; + }; + + mux { + function = "ethernet1"; + groups = "ethernet1_0_grp"; + }; + }; + + pinctrl_usb0_default: usb0-default { + conf { + groups = "usb0_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO52", "MIO53", "MIO55"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", + "MIO60", "MIO61", "MIO62", "MIO63"; + bias-disable; + }; + + mux { + groups = "usb0_0_grp"; + function = "usb0"; + }; + }; + + pinctrl_usb1_default: usb1-default { + conf { + groups = "usb1_0_grp"; + slew-rate = <SLEW_RATE_SLOW>; + power-source = <IO_STANDARD_LVCMOS18>; + }; + + conf-rx { + pins = "MIO64", "MIO65", "MIO67"; + bias-high-impedance; + }; + + conf-tx { + pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71", + "MIO72", "MIO73", "MIO74", "MIO75"; + bias-disable; + }; + + mux { + groups = "usb1_0_grp"; + function = "usb1"; + }; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; +}; -- 2.36.0

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[PATCH] serial: Setup serial base and freq for zynq/zynqmp
by Michal Simek 06 Jun '22

06 Jun '22

Setup default values for debug console, base address and frequency. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- drivers/serial/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 26fa498bbbb7..f9db7860750b 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -502,6 +502,8 @@ config DEBUG_UART_BASE depends on DEBUG_UART default 0 if DEBUG_SBI_CONSOLE default 0 if DEBUG_UART_SANDBOX + default 0xff000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQMP + default 0xe0000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQ help This is the base address of your UART for memory-mapped UARTs. @@ -514,6 +516,8 @@ config DEBUG_UART_CLOCK default 0 if DEBUG_SBI_CONSOLE default 0 if DEBUG_UART_SANDBOX default 0 if DEBUG_MVEBU_A3700_UART + default 100000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQMP + default 50000000 if DEBUG_UART_ZYNQ && ARCH_ZYNQ help The UART input clock determines the speed of the internal UART circuitry. The baud rate is derived from this by dividing the input -- 2.36.0

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[PATCH] arm64: zynqmp: Add debug messages to bl2_plat_get_bl31_params()
by Michal Simek 06 Jun '22

06 Jun '22

It is useful to get information about BL type and entry address that's why add some debug messages. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/mach-zynqmp/handoff.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c index 31346d9b2e21..b9e0c6c536be 100644 --- a/arch/arm/mach-zynqmp/handoff.c +++ b/arch/arm/mach-zynqmp/handoff.c @@ -79,7 +79,10 @@ struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, atfhandoffparams->magic[2] = 'N'; atfhandoffparams->magic[3] = 'X'; + debug("Creating handoff:\n"); + if (bl32_entry) { + debug(" to BL32 at 0x%x EL-1, Secure\n", (u32)bl32_entry); atfhandoffparams->partition[index].entry_point = bl32_entry; atfhandoffparams->partition[index].flags = FSBL_FLAGS_EL1 << FSBL_FLAGS_EL_SHIFT | FSBL_FLAGS_SECURE << FSBL_FLAGS_TZ_SHIFT; @@ -87,6 +90,7 @@ struct bl31_params *bl2_plat_get_bl31_params(uintptr_t bl32_entry, } if (bl33_entry) { + debug(" to BL33 at 0x%x EL-2\n", (u32)bl33_entry); atfhandoffparams->partition[index].entry_point = bl33_entry; atfhandoffparams->partition[index].flags = FSBL_FLAGS_EL2 << FSBL_FLAGS_EL_SHIFT; -- 2.36.0

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[PATCH] xilinx: fru: Replace spaces with \0 in detected revision
by Michal Simek 06 Jun '22

06 Jun '22

Also fix board revision field where spaces are used instead of \0. The same change was done for board name by commit 530560b6f8eb ("xilinx: fru: Replace spaces with \0 in detected name"). Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- board/xilinx/common/board.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index 5be3090c3186..629a6ee036ff 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -245,6 +245,10 @@ static int xilinx_read_eeprom_fru(struct udevice *dev, char *name, } strncpy(desc->revision, (char *)fru_data.brd.rev, sizeof(desc->revision)); + for (i = 0; i < sizeof(desc->revision); i++) { + if (desc->revision[i] == ' ') + desc->revision[i] = '\0'; + } strncpy(desc->serial, (char *)fru_data.brd.serial_number, sizeof(desc->serial)); -- 2.36.0

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Pull request for efi-2022-07-rc4-4
by Heinrich Schuchardt 05 Jun '22

05 Jun '22

Dear Tom, The following changes since commit 90189ecd59cdf14afbe6014be5c068e599b65a72: Merge branch '2022-06-03-assorted-fixes' (2022-06-03 15:42:13 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-efi.git tags/efi-2022-07-rc4-4 for you to fetch changes up to 8645aefc8b699f900d97cbadd55b7f492099c61e: efi: test/py: authenticate fit capsules (2022-06-04 08:43:55 +0200) Gitlab CI showed no issues: https://source.denx.de/u-boot/custodians/u-boot-efi/-/pipelines/12196 ---------------------------------------------------------------- Pull request for efi-2022-07-rc4-4 UEFI: * Fix the implementation of the firmware management protocol * Fix the unit tests for signed update capsules ---------------------------------------------------------------- Chris Packham (1): doc: environment: Fix typo Sughosh Ganu (2): EFI: Populate descriptor_count value only when image_info_size is not zero EFI: Update the documentation to reflect the correct value of OsIndications Vincent Stehlé (2): test/py: efi_capsule: repair image authentication test efi: test/py: authenticate fit capsules doc/develop/uefi/uefi.rst | 2 +- doc/usage/environment.rst | 2 +- lib/efi_loader/efi_firmware.c | 120 ++++++++++------ test/py/tests/test_efi_capsule/conftest.py | 25 +++- test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py | 257 ++++++++++++++++++++++++++++++++++ ...st_capsule_firmware_signed.py => test_capsule_firmware_signed_raw.py} | 14 +- 6 files changed, 362 insertions(+), 58 deletions(-) create mode 100644 test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py rename test/py/tests/test_efi_capsule/{test_capsule_firmware_signed.py => test_capsule_firmware_signed_raw.py} (96%)

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