June 2022 - U-Boot

[PATCH] arm: dts: socfpga: agilex: Add freeze controller node
by dinesh.maniyam＠intel.com 16 Jun '22

16 Jun '22

From: Dinesh Maniyam <dinesh.maniyam(a)intel.com> The freeze controller is required for FPGA partial reconfig. This node is disable on default. Enable this node via u-boot fdt command when needed. Signed-off-by: Yau Wai Gan <yau.wai.gan(a)intel.com> Signed-off-by: Dinesh Maniyam <dinesh.maniyam(a)intel.com> --- arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi index 6cac36a1fc..2400fad18a 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -2,7 +2,7 @@ /* * U-Boot additions * - * Copyright (C) 2019 Intel Corporation <www.intel.com> + * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> */ #include "socfpga_agilex-u-boot.dtsi" @@ -11,6 +11,15 @@ aliases { spi0 = &qspi; i2c0 = &i2c1; + freeze_br0 = &freeze_controller; + }; + + soc { + freeze_controller: freeze_controller@f9000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0xf9000450 0x00000010>; + status = "disabled"; + }; }; memory { -- 2.26.2

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[PATCH v2 00/11] Add Chameleon v3 support
by Paweł Anikiel 16 Jun '22

16 Jun '22

The Google Chameleon v3 is a board made for testing both video and audio interfaces of external devices. It has a connector compatible with the Mercury+ AA1 module, which itself contains an Arria 10 SoCFPGA. The AA1 module comes in a few different configurations, the Chameleon V3 supports ME-AA1-270-3E4-D11 and ME-AA1-480-2I3-D12E. This patchset adds support for the Chameleon v3 (both versions), as well as some bugfixes and optimizations, mostly in Arria 10 code. V2: Adjust devicetrees so that they work both in u-boot and linux Put u-boot-specific parts of devicetrees into *-u-boot.dtsi files Minor changes in Kconfig, defconfig, and config.h Paweł Anikiel (11): arm: dts: Add Mercury+ AA1 devicetrees arm: dts: Add Chameleonv3 handoff headers arm: dts: Add Chameleonv3 devicetrees board: Add Chameleonv3 board dir config: Add Chameleonv3 config misc: atsha204a: Increase wake delay by tWHI sysreset: socfpga: Use parent device for reading base address socfpga: arria10: Replace delays with busy waiting in cm_full_cfg socfpga: arria10: Improve bitstream loading speed socfpga: arria10: Wait for fifo empty after writing bitstream socfpga: arria10: Allow dcache_enable before relocation arch/arm/dts/Makefile | 2 + arch/arm/dts/socfpga_arria10_chameleonv3.dts | 90 ++++++ ...fpga_arria10_chameleonv3_270_3-u-boot.dtsi | 8 + .../dts/socfpga_arria10_chameleonv3_270_3.dts | 5 + ...ocfpga_arria10_chameleonv3_270_3_handoff.h | 305 ++++++++++++++++++ ...fpga_arria10_chameleonv3_480_2-u-boot.dtsi | 8 + .../dts/socfpga_arria10_chameleonv3_480_2.dts | 5 + ...ocfpga_arria10_chameleonv3_480_2_handoff.h | 305 ++++++++++++++++++ .../socfpga_arria10_mercury_aa1-u-boot.dtsi | 54 ++++ arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi | 72 +++++ arch/arm/mach-socfpga/Kconfig | 7 + arch/arm/mach-socfpga/clock_manager.c | 7 +- arch/arm/mach-socfpga/clock_manager_arria10.c | 12 +- .../mach-socfpga/include/mach/clock_manager.h | 4 + arch/arm/mach-socfpga/misc_arria10.c | 26 ++ board/google/chameleonv3/Makefile | 5 + board/google/chameleonv3/board.c | 27 ++ board/google/chameleonv3/fpga.its | 28 ++ board/google/chameleonv3/fpga_early_io.its | 35 ++ board/google/chameleonv3/mercury_aa1.c | 43 +++ board/google/chameleonv3/mercury_aa1.h | 12 + configs/socfpga_chameleonv3_defconfig | 29 ++ drivers/fpga/socfpga_arria10.c | 28 +- drivers/misc/atsha204a-i2c.c | 5 +- drivers/sysreset/sysreset_socfpga.c | 2 +- include/configs/socfpga_chameleonv3.h | 44 +++ 26 files changed, 1154 insertions(+), 14 deletions(-) create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3.dts create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi create mode 100644 board/google/chameleonv3/Makefile create mode 100644 board/google/chameleonv3/board.c create mode 100644 board/google/chameleonv3/fpga.its create mode 100644 board/google/chameleonv3/fpga_early_io.its create mode 100644 board/google/chameleonv3/mercury_aa1.c create mode 100644 board/google/chameleonv3/mercury_aa1.h create mode 100644 configs/socfpga_chameleonv3_defconfig create mode 100644 include/configs/socfpga_chameleonv3.h -- 2.36.1.124.g0e6072fb45-goog

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[RFC] Create arch/Kconfig.nxp
by Tom Rini 16 Jun '22

16 Jun '22

Hey all, As I migrate assorted CONFIG options over to Kconfig, a common problem I run in to is that between m68k, PowerPC and ARM (both Layerscape and sometimes i.MX) there are options that fit under more than one architecture but also don't have a good place to go. For example, I just ran in to CONFIG_SYS_FSL_NUM_CC_PLLS which started as PowerPC specific, but is used still in Layerscape and more of a SoC detail (but wouldn't make sense in drivers/soc/Kconfig). I was thinking that perhaps arch/Kconfig.nxp would be a good starting place to put these options, but I'm quite open to other suggestions. Thanks! -- Tom

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[PATCH V3 1/2] mtd: allow getting MTD device associated with a specific DT node
by Rafał Miłecki 15 Jun '22

15 Jun '22

From: Rafał Miłecki <rafal(a)milecki.pl> MTD subsystem API allows interacting with MTD devices (e.g. reading, writing, handling bad blocks). So far a random driver could get MTD device only by its name (get_mtd_device_nm()). This change allows getting them also by a DT node. This API is required for drivers handling DT defined MTD partitions in a specific way (e.g. U-Boot (sub)partition with environment variables). Signed-off-by: Rafał Miłecki <rafal(a)milecki.pl> --- V3: First introduction of of_get_mtd_device_by_node() mtd maintainers: please let know how would you like this patch processed. Would that be OK for you to Review/Ack it and let it go through NVMEM tree? --- drivers/mtd/mtdcore.c | 28 ++++++++++++++++++++++++++++ include/linux/mtd/mtd.h | 1 + 2 files changed, 29 insertions(+) diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index 9eb0680db312..7dc214271c85 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -1154,6 +1154,34 @@ int __get_mtd_device(struct mtd_info *mtd) } EXPORT_SYMBOL_GPL(__get_mtd_device); +/** + * of_get_mtd_device_by_node - obtain an MTD device associated with a given node + * + * @np: device tree node + */ +struct mtd_info *of_get_mtd_device_by_node(struct device_node *np) +{ + struct mtd_info *mtd = NULL; + struct mtd_info *tmp; + int err; + + mutex_lock(&mtd_table_mutex); + + err = -ENODEV; + mtd_for_each_device(tmp) { + if (mtd_get_of_node(tmp) == np) { + mtd = tmp; + err = __get_mtd_device(mtd); + break; + } + } + + mutex_unlock(&mtd_table_mutex); + + return err ? ERR_PTR(err) : mtd; +} +EXPORT_SYMBOL_GPL(of_get_mtd_device_by_node); + /** * get_mtd_device_nm - obtain a validated handle for an MTD device by * device name diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 955aee14b0f7..6fc841ceef31 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -677,6 +677,7 @@ extern int mtd_device_unregister(struct mtd_info *master); extern struct mtd_info *get_mtd_device(struct mtd_info *mtd, int num); extern int __get_mtd_device(struct mtd_info *mtd); extern void __put_mtd_device(struct mtd_info *mtd); +extern struct mtd_info *of_get_mtd_device_by_node(struct device_node *np); extern struct mtd_info *get_mtd_device_nm(const char *name); extern void put_mtd_device(struct mtd_info *mtd); -- 2.34.1

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[PATCH] configs: stm32mp: cleanup the stm32mp15 file
by Patrick Delaunay 15 Jun '22

15 Jun '22

Clean the comments in stm32mp15_common.h file after move CONFIG_ to Kconfig: - CONFIG_SYS_CBSIZE - CONFIG_SYS_SPL_MALLOC_START and CONFIG_SYS_SPL_MALLOC_SIZE Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- include/configs/stm32mp15_common.h | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index 08a72483bf..c7b200d4b1 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -15,10 +15,6 @@ */ #define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE -/* - * Console I/O buffer size - */ - /* * For booting Linux, use the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. @@ -30,11 +26,10 @@ /* SPL support */ #ifdef CONFIG_SPL -/* SPL use DDR */ - /* Restrict SPL to fit within SYSRAM */ #define STM32_SYSRAM_END (STM32_SYSRAM_BASE + STM32_SYSRAM_SIZE) #endif /* #ifdef CONFIG_SPL */ + /*MMC SD*/ #define CONFIG_SYS_MMC_MAX_DEVICE 3 -- 2.25.1

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[PATCH 1/3] ARM: renesas: condor: switch eMMC bus to 1V8
by Marek Vasut 15 Jun '22

15 Jun '22

From: Hai Pham <hai.pham.ud(a)renesas.com> The eMMC card has two supplies, VCC and VCCQ. The VCC supplies the NAND array and the VCCQ supplies the bus. On Condor, the VCC is connected to 3.3V rail, while the VCCQ is connected to 1.8V rail. Adjust the pinmux to match the bus, which is always operating in 1.8V mode. Based on Linux commit 69efe4bbeda50745 ("arm64: dts: renesas: condor: Switch eMMC bus to 1V8") from Wolfram Sang Signed-off-by: Hai Pham <hai.pham.ud(a)renesas.com> --- arch/arm/dts/r8a77980-condor.dts | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/arch/arm/dts/r8a77980-condor.dts b/arch/arm/dts/r8a77980-condor.dts index 3dde028e22..f0a0a51d73 100644 --- a/arch/arm/dts/r8a77980-condor.dts +++ b/arch/arm/dts/r8a77980-condor.dts @@ -212,7 +212,7 @@ &mmc0 { pinctrl-0 = <&mmc_pins>; - pinctrl-1 = <&mmc_pins_uhs>; + pinctrl-1 = <&mmc_pins>; pinctrl-names = "default", "state_uhs"; vmmc-supply = <&d3_3v>; @@ -253,12 +253,6 @@ }; mmc_pins: mmc { - groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; - function = "mmc"; - power-source = <3300>; - }; - - mmc_pins_uhs: mmc_uhs { groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; function = "mmc"; power-source = <1800>; -- 2.35.1

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[PATCH v2 0/5] mx6cuboxi: add eth support for SoMs revision 1.9+
by Josua Mayer 15 Jun '22

15 Jun '22

As of Revision 1.9 the SolidRun i.MX6 SoMs ship with a new PHY - an ADIN1300 at address 1. This patchset carries many small parts to facilitate proper operation of the ethernet port in U-Boot as well as Linux: 1. Fix a compile error in the recently added phy driver 2. Add support for configuring the clock output pins to the phy driver 3. update device-tree with support for the new phy 4. support runtime patching of device-tree for Linux: enable only the phy node detected during boot, to avoid warning messages when Linux probes the phys. 5. finally enable the phy driver in the cuboxi defconfig I have included Nate's patch here only so that it won't get lost - it is fully independent and I have not made any changes. Changes since v1: - applied proper compile fix by Nate Drude - removed -recovered clock options as requested by Linux maintainers Josua Mayer (4): phy: adin: add support for clock output ARM: dts: imx6qdl-sr-som: add support for alternate phy addresses mx6cuboxi: fixup dtb ethernet phy nodes before booting an OS mx6cuboxi: enable driver for adin1300 phy Nate Drude (1): phy: adin: fix broken support for adi,phy-mode-override arch/arm/dts/imx6qdl-sr-som.dtsi | 17 +++++- board/solidrun/mx6cuboxi/mx6cuboxi.c | 78 ++++++++++++++++++++++++++++ configs/mx6cuboxi_defconfig | 2 + drivers/net/phy/adin.c | 64 +++++++++++++++++++---- 4 files changed, 148 insertions(+), 13 deletions(-) -- 2.35.3

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[PATCH 1/2] toradex: tdx-cfg-block: add new 8gb apalis-imx8
by Philippe Schenker 15 Jun '22

15 Jun '22

From: Philippe Schenker <philippe.schenker(a)toradex.com> 0067: Apalis iMX8 QuadMax 8GB Wi-Fi / BT IT This module is identical to its 4GB counterpart 0037: Apalis iMX8 QuadMax 4GB Wi-Fi / BT IT except for the RAM size. Signed-off-by: Philippe Schenker <philippe.schenker(a)toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini(a)toradex.com> --- board/toradex/common/tdx-cfg-block.c | 18 ++++++++++++++++-- board/toradex/common/tdx-cfg-block.h | 1 + 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 9c87289ae9..6c8cf4592d 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -144,6 +144,7 @@ const char * const toradex_modules[] = { [64] = "Verdin iMX8M Plus Quad 2GB Wi-Fi / BT IT", [65] = "Verdin iMX8M Plus QuadLite 1GB IT", [66] = "Verdin iMX8M Plus Quad 8GB Wi-Fi / BT", + [67] = "Apalis iMX8 QuadMax 8GB Wi-Fi / BT IT", }; const char * const toradex_carrier_boards[] = { @@ -359,6 +360,7 @@ static int get_cfgblock_interactive(void) char *soc; char it = 'n'; char wb = 'n'; + char mem8g = 'n'; int len = 0; /* Unknown module by default */ @@ -377,6 +379,14 @@ static int get_cfgblock_interactive(void) sprintf(message, "Does the module have Wi-Fi / Bluetooth? [y/N] "); len = cli_readline(message); wb = console_buffer[0]; + +#if defined(CONFIG_TARGET_APALIS_IMX8) + if ((wb == 'y' || wb == 'Y') && (it == 'y' || it == 'Y')) { + sprintf(message, "Does your module have 8GB of RAM? [y/N] "); + len = cli_readline(message); + mem8g = console_buffer[0]; + } +#endif #endif soc = env_get("soc"); @@ -430,8 +440,12 @@ static int get_cfgblock_interactive(void) tdx_hw_tag.prodid = COLIBRI_IMX7S; else if (is_cpu_type(MXC_CPU_IMX8QM)) { if (it == 'y' || it == 'Y') { - if (wb == 'y' || wb == 'Y') - tdx_hw_tag.prodid = APALIS_IMX8QM_WIFI_BT_IT; + if (wb == 'y' || wb == 'Y') { + if (mem8g == 'y' || mem8g == 'Y') + tdx_hw_tag.prodid = APALIS_IMX8QM_8GB_WIFI_BT_IT; + else + tdx_hw_tag.prodid = APALIS_IMX8QM_WIFI_BT_IT; + } else tdx_hw_tag.prodid = APALIS_IMX8QM_IT; } else { diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index ddcf699748..43e662e41d 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -87,6 +87,7 @@ enum { VERDIN_IMX8MPQ_2GB_WIFI_BT_IT, VERDIN_IMX8MPQL_IT, /* 65 */ VERDIN_IMX8MPQ_8GB_WIFI_BT, + APALIS_IMX8QM_8GB_WIFI_BT_IT, }; enum { -- 2.35.1

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[PATCH] imx8mn_evk: Add the missing spl.bin entry
by Fabio Estevam 15 Jun '22

15 Jun '22

From: Fabio Estevam <festevam(a)denx.de> The generated flash.bin does not boot the imx8mn evk LPDDR4 variant as it misses the spl.bin description in binman. Add its entry to fix the boot on the imx8mn evk LPDDR4 variant. Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- arch/arm/dts/imx8mn-evk-u-boot.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/imx8mn-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-evk-u-boot.dtsi index 3db46d4cbc..593cf06eb9 100644 --- a/arch/arm/dts/imx8mn-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-evk-u-boot.dtsi @@ -58,7 +58,9 @@ }; - flash { + spl { + filename = "spl.bin"; + mkimage { args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000"; -- 2.25.1

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[PATCH 0/2] clk: imx8mp: clock names and clock source fixes
by Andrey Zhizhikin 15 Jun '22

15 Jun '22

This series addresses few fixes for clock sub-system for i.MX8MP SOC. One is dealing with incorrect names used, while the second one addresses root clock selection which has been apparently omitted during merge and caused the warning to be reported during boot. Andrey Zhizhikin (2): clk: imx8mp: fix root clock names for ecspi clk: imx8mp: use usb_core_ref for usb_root_clk drivers/clk/imx/clk-imx8mp.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) base-commit: 3053b781465711fd05b88ab141b1f2b55a875516 -- 2.25.1

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