June 2022 - U-Boot

[PATCH v2 00/14] doc: mkimage: Rework and refactor the man page; add long options
by Sean Anderson 16 Jun '22

16 Jun '22

This gives a facelift for the mkimage man page, bringing it in line with the style perscribed by man-pages(7) and groff_man_style(7). I have tried to remove typographical and grammatical errors and inconsistencies wherever possible. The man page now both looks and feels closer to other Linux man pages. As a bonus, I also added a man page for dumpimage in the same style. To address the impending exhaustion of short options, this also adds long options for each short option. Changes in v2: - Add long options - Better document multi images - Document -h and -V - Ensure comments are requests - Escape minus signs in examples - Fix -B not being bolded in the description for -R - Fix extra quote in -E synopsis - Fix spacing for -F - Further document -o and -R - Indent things more robustly - Italicize parameter for -d - Make lists of valid algos bold - Rearrange more options - Remove spaces around pipes - Rename first subsection to "General options" - Use escape-sequences for options width all three of B/I/R. This renders better with mandoc. - Use paired quotation marks Sean Anderson (14): doc: mkimage: Use standard style for synopsis doc: mkimage: Use empty request instead of blank lines doc: mkimage: Reformat examples doc: mkimage: Regularize option documentation doc: mkimage: Use subsection macro doc: mkimage: Rearrange/remove some options doc: mkimage: Use correct capitalization for NAME doc: mkimage: Edit options for style and consistency doc: mkimage: Add BUGS section doc: mkimage: Add SEE ALSO section doc: mkimage: Remove AUTHORS section mkimage: Add long options doc: mkimage: Further document -o and -R doc: Add man page for dumpimage doc/dumpimage.1 | 103 ++++++ doc/mkimage.1 | 933 ++++++++++++++++++++++++++++++++++-------------- tools/mkimage.c | 45 ++- 3 files changed, 811 insertions(+), 270 deletions(-) create mode 100644 doc/dumpimage.1 -- 2.35.1

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[PATCH v3] crypto/fsl: fsl_hash: Fix crash in flush dcache
by Gaurav Jain 16 Jun '22

16 Jun '22

wrong end address passed to flush_dcache_range. modified the flush_dache logic for scatter list elements. Fixes: 1919f58a8f (crypto/fsl: fsl_hash: Fix dcache issue in caam_hash_finish) Signed-off-by: Gaurav Jain <gaurav.jain(a)nxp.com> --- changes in v3: - fix error: left shift count >= width of type [-Werror=shift-count-overflow] drivers/crypto/fsl/fsl_hash.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index 9e6829b7ad..f8c5b1772f 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -131,25 +131,35 @@ static int caam_hash_update(void *hash_ctx, const void *buf, static int caam_hash_finish(void *hash_ctx, void *dest_buf, int size, enum caam_hash_algos caam_algo) { - uint32_t len = 0; + uint32_t len = 0, sg_entry_len; struct sha_ctx *ctx = hash_ctx; int i = 0, ret = 0; + ulong addr; if (size < driver_hash[caam_algo].digestsize) { return -EINVAL; } - for (i = 0; i < ctx->sg_num; i++) - len += (sec_in32(&ctx->sg_tbl[i].len_flag) & - SG_ENTRY_LENGTH_MASK); - + flush_dcache_range((ulong)ctx->sg_tbl, + (ulong)(ctx->sg_tbl) + (ctx->sg_num * sizeof(struct sg_entry))); + for (i = 0; i < ctx->sg_num; i++) { + sg_entry_len = (sec_in32(&ctx->sg_tbl[i].len_flag) & + SG_ENTRY_LENGTH_MASK); + len += sg_entry_len; +#ifdef CONFIG_CAAM_64BIT + addr = sec_in32(&ctx->sg_tbl[i].addr_hi); + addr = (addr << 32) | sec_in32(&ctx->sg_tbl[i].addr_lo); +#else + addr = sec_in32(&ctx->sg_tbl[i].addr_lo); +#endif + flush_dcache_range(addr, addr + sg_entry_len); + } inline_cnstr_jobdesc_hash(ctx->sha_desc, (uint8_t *)ctx->sg_tbl, len, ctx->hash, driver_hash[caam_algo].alg_type, driver_hash[caam_algo].digestsize, 1); - flush_dcache_range((ulong)ctx->sg_tbl, (ulong)(ctx->sg_tbl) + len); flush_dcache_range((ulong)ctx->sha_desc, (ulong)(ctx->sha_desc) + (sizeof(uint32_t) * MAX_CAAM_DESCSIZE)); flush_dcache_range((ulong)ctx->hash, -- 2.25.1

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Re: [PATCH v2 4/5] mx6cuboxi: fixup dtb ethernet phy nodes before booting an OS
by Josua Mayer 16 Jun '22

16 Jun '22

Hi Stefano, Thank you for applying this patchset. This patch had a functional flaw that I was intending to address in v3. Instead I have now followed up with a separate patch: [PATCH] mx6cuboxi: fix board detection while patching device-tree phy nodes Please make sure this one is added too. sincerely Josua Mayer Am 15.06.22 um 14:11 schrieb sbabic(a)denx.de: >> SoM revision 1.9 has replaced the ar8035 phy address 0 with an adin1300 >> at address 1. Because early SoMs had a hardware flaw, the ar8035 can >> also appear at address 4 - making it a total of 3 phy nodes in the DTB. >> To avoid confusing Linux with probe errors, fixup the dtb to only enable >> the phy node that is detected at runtime. >> Signed-off-by: Josua Mayer <josua(a)solid-run.com> > Applied to u-boot-imx, master, thanks ! > > Best regards, > Stefano Babic >

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[PATCH 1/2] usb: gadget: Add a config option to set the SPL product ID
by Alban Bedel 16 Jun '22

16 Jun '22

It might be desirable to have a different product ID for the SPL gadget. Several boards use dubious hack to achieve this like adding an hardcoded offset to the configurable main product ID. Add a new config option to set the product ID to use in the SPL and use it in the ethernet and download gadgets. Signed-off-by: Alban Bedel <alban.bedel(a)aerq.com> --- common/spl/Kconfig | 6 ++++++ drivers/usb/gadget/ether.c | 2 +- drivers/usb/gadget/g_dnl.c | 2 +- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index ac61b25a0660..196f3cfc5558 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1182,6 +1182,12 @@ config SPL_USB_GADGET if SPL_USB_GADGET +config SPL_USB_GADGET_PRODUCT_NUM + hex "Product ID of the SPL USB device" + default 0x0 + help + Product ID of the USB device emulated in SPL, reported to the host device. + config SPL_USB_ETHER bool "Support USB Ethernet drivers" depends on SPL_NET diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index 430732865723..18195d3ee19b 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -2078,7 +2078,7 @@ static int eth_bind(struct usb_gadget *gadget) device_desc.idVendor = __constant_cpu_to_le16(CONFIG_USB_GADGET_VENDOR_NUM); device_desc.idProduct = - __constant_cpu_to_le16(CONFIG_USB_GADGET_PRODUCT_NUM); + __constant_cpu_to_le16(CONFIG_VAL(USB_GADGET_PRODUCT_NUM)); #else device_desc.idVendor = __constant_cpu_to_le16(RNDIS_VENDOR_NUM); diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c index afb7b74f3057..85297cc0e501 100644 --- a/drivers/usb/gadget/g_dnl.c +++ b/drivers/usb/gadget/g_dnl.c @@ -63,7 +63,7 @@ static struct usb_device_descriptor device_desc = { .bDeviceSubClass = 0, /*0x02:CDC-modem , 0x00:CDC-serial*/ .idVendor = __constant_cpu_to_le16(CONFIG_USB_GADGET_VENDOR_NUM), - .idProduct = __constant_cpu_to_le16(CONFIG_USB_GADGET_PRODUCT_NUM), + .idProduct = __constant_cpu_to_le16(CONFIG_VAL(USB_GADGET_PRODUCT_NUM)), /* .iProduct = DYNAMIC */ /* .iSerialNumber = DYNAMIC */ .bNumConfigurations = 1, -- 2.32.0

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[PATCH] imx: spl: Default to SPD when booting from USB serial download
by Alban Bedel 16 Jun '22

16 Jun '22

On the iMX platforms the USB boot is in fact boot from USB serial download and not from a USB mass storage. So returning BOOT_DEVICE_USB typically doesn't make sense as USB SPD is then used to continue booting, for this we need to return BOOT_DEVICE_BOARD. Still return BOOT_DEVICE_USB when USB mass storage support has been built in the SPL. With USB-C on both side, the programmer could switch back to device mode and use the exposed mass storage device after the serial download finished. Signed-off-by: Alban Bedel <alban.bedel(a)aerq.com> --- arch/arm/mach-imx/spl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 64ca29677212..2c2b2b126ad7 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -177,7 +177,8 @@ u32 spl_boot_device(void) case QSPI_BOOT: return BOOT_DEVICE_NOR; case USB_BOOT: - return BOOT_DEVICE_USB; + return IS_ENABLED(CONFIG_SPL_USB_STORAGE) ? + BOOT_DEVICE_USB : BOOT_DEVICE_BOARD; default: return BOOT_DEVICE_NONE; } -- 2.32.0

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[PATCH v2 0/2] usb: dwc3: Fix build without driver model
by Alban Bedel 16 Jun '22

16 Jun '22

Hi everyone, Platform with DWC3 that need USB support in the SPL might not be able to use the driver model there while the main u-boot is using driver model. This series allow building with such a configuration, it first fix 2 warnings when the core is built without driver model and then fix the SPL linking when one of the glue driver is enabled for the main u-boot. Changelog: v2: Use __maybe_unused instead of an #ifdef Alban Bedel (2): usb: dwc3: core: fix warnings when building without driver model usb: dwc3: Don't build DM drivers in SPL unless DM USB is available drivers/usb/dwc3/Makefile | 9 ++++++--- drivers/usb/dwc3/core.c | 5 ++--- 2 files changed, 8 insertions(+), 6 deletions(-) -- 2.32.0

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[PATCH] ddr:altera:soc64: Integer fix overflow that caused DDR size mismatched
by dinesh.maniyam＠intel.com 16 Jun '22

16 Jun '22

From: Dinesh Maniyam <dinesh.maniyam(a)intel.com> Convert the constant integer to 'phys_size_t' to avoid overflow when calculating the SDRAM size. Signed-off-by: Chee Hong Ang <chee.hong.ang(a)intel.com> Signed-off-by: Dinesh Maniyam <dinesh.maniyam(a)intel.com> --- drivers/ddr/altera/sdram_soc64.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index d6baac2410..1f479c514d 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -239,7 +239,8 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat) { u32 dramaddrw = hmc_readl(plat, DRAMADDRW); - phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + + phys_size_t size = (phys_size_t)1 << + (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + -- 2.26.2

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[PATCH] drivers: cache: ncore: Disable snoop filter
by dinesh.maniyam＠intel.com 16 Jun '22

16 Jun '22

From: Dinesh Maniyam <dinesh.maniyam(a)intel.com> There is hardware bug in NCORE CCU IP and it is causing an issue in the coherent directory tracking of outstanding cache lines. The workaround is disabling snoop filter. Signed-off-by: Dinesh Maniyam <dinesh.maniyam(a)intel.com> --- drivers/cache/cache-ncore.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/cache/cache-ncore.c b/drivers/cache/cache-ncore.c index 3beff780de..117d2b91ab 100644 --- a/drivers/cache/cache-ncore.c +++ b/drivers/cache/cache-ncore.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2019 Intel Corporation <www.intel.com> + * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> * */ #include <dm.h> @@ -81,8 +81,8 @@ static void ncore_ccu_init_dirs(void __iomem *base) hang(); } - /* Enable snoop filter, a bit per snoop filter */ - setbits_le32((ulong)CCU_DIR_REG_ADDR(base, DIRUSFER, i), + /* Disable snoop filter, a bit per snoop filter */ + clrbits_le32((ulong)CCU_DIR_REG_ADDR(base, DIRUSFER, i), BIT(f)); } } -- 2.25.1

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[PATCH] arch: arm: socfpga: timer_s10: Override udelay for secure section
by dinesh.maniyam＠intel.com 16 Jun '22

16 Jun '22

From: Dinesh Maniyam <dinesh.maniyam(a)intel.com> Override __udelay() as 'always inlined' function so that PSCI code run in '__secure' section can call this delay function as well. Signed-off-by: Chee Hong Ang <chee.hong.ang(a)intel.com> Signed-off-by: Dinesh Maniyam <dinesh.maniyam(a)intel.com> --- arch/arm/mach-socfpga/timer_s10.c | 35 ++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/timer_s10.c b/arch/arm/mach-socfpga/timer_s10.c index 7d5598e1a3..33afc87749 100644 --- a/arch/arm/mach-socfpga/timer_s10.c +++ b/arch/arm/mach-socfpga/timer_s10.c @@ -1,11 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2017-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2017-2022 Intel Corporation <www.intel.com> * */ #include <common.h> #include <init.h> +#include <div64.h> #include <asm/io.h> #include <asm/arch/timer.h> @@ -26,3 +27,35 @@ int timer_init(void) #endif return 0; } + +__always_inline u64 __get_time_stamp(void) +{ + u64 cntpct; + + isb(); + asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct)); + + return cntpct; +} + +__always_inline uint64_t __usec_to_tick(unsigned long usec) +{ + u64 tick = usec; + u64 cntfrq; + + asm volatile("mrs %0, cntfrq_el0" : "=r" (cntfrq)); + tick *= cntfrq; + do_div(tick, 1000000); + + return tick; +} + +__always_inline void __udelay(unsigned long usec) +{ + /* get current timestamp */ + u64 tmp = __get_time_stamp() + __usec_to_tick(usec); + + while (__get_time_stamp() < tmp + 1) /* loop till event */ + ; +} + -- 2.25.1

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[PATCH] arm: dts: socfpga: stratix10: Add freeze controller node
by dinesh.maniyam＠intel.com 16 Jun '22

16 Jun '22

From: Dinesh Maniyam <dinesh.maniyam(a)intel.com> The freeze controller is required for FPGA partial reconfig. This node is disable on default. Enable this node via u-boot fdt command when needed. Signed-off-by: Yau Wai Gan <yau.wai.gan(a)intel.com> Signed-off-by: Dinesh Maniyam <dinesh.maniyam(a)intel.com> --- arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi index 61df425f14..75a29045da 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi @@ -2,7 +2,7 @@ /* * U-Boot additions * - * Copyright (C) 2019-2020 Intel Corporation <www.intel.com> + * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> */ #include "socfpga_stratix10-u-boot.dtsi" @@ -10,6 +10,15 @@ /{ aliases { spi0 = &qspi; + freeze_br0 = &freeze_controller; + }; + + soc { + freeze_controller: freeze_controller@f9000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0xf9000450 0x00000010>; + status = "disabled"; + }; }; }; -- 2.25.1

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