June 2022 - U-Boot

[PATCH 0/3] arm64: zynqmp: Some DT updates
by Michal Simek 24 Jun '22

24 Jun '22

Hi, I am sending DT series to fix some DT issues which were found. Thanks, Michal Michal Simek (3): arm64: zynqmp: Fix i2c addresses for vck190 SC arm64: zynqmp: Update tps53681 i2c address arm64: zynqmp: Fix tps544/u3007 node description arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 6 +++--- arch/arm/dts/zynqmp-g-a2197-00-revA.dts | 4 ++-- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 4 ++-- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 8 ++------ arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 8 ++++---- 5 files changed, 13 insertions(+), 17 deletions(-) -- 2.36.1

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[PATCH] pinctrl: zynqmp: Add support for output-enable and bias-high-impedance
by Michal Simek 24 Jun '22

24 Jun '22

From: Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> Add support to handle 'output-enable' and 'bias-high-impedance' configurations. DT property output-enable brings out the pins from tri-state, whereas bias-high-impedance changes the pins state to tri-state. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- drivers/pinctrl/pinctrl-zynqmp.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index 7c5a02db1b98..52d428f566fc 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -467,6 +467,10 @@ static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin, pin); break; case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + param = PM_PINCTRL_CONFIG_TRI_STATE; + arg = PM_PINCTRL_TRI_STATE_ENABLE; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; case PIN_CONFIG_LOW_POWER_MODE: /* * This cases are mentioned in dts but configurable @@ -475,6 +479,11 @@ static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin, */ ret = 0; break; + case PIN_CONFIG_OUTPUT_ENABLE: + param = PM_PINCTRL_CONFIG_TRI_STATE; + arg = PM_PINCTRL_TRI_STATE_DISABLE; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; default: dev_warn(dev, "unsupported configuration parameter '%u'\n", param); -- 2.36.1

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[PATCH] arm64: zynqmp: Enable DP for kv260-revA board
by Michal Simek 24 Jun '22

24 Jun '22

DP is enabled for revB and should be enabled for kv260-revA too. Changes in other boards were done by commit 8b82a3a7feb0 ("arm64: zynqmp: Enable DP driver for SOMs"). Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/dts/zynqmp-sck-kv-g-revA.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts index 85994bef7cc0..8250a493c8a0 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts @@ -112,7 +112,7 @@ }; &zynqmp_dpsub { - status = "disabled"; + status = "okay"; phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; -- 2.36.1

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[PATCH] toradex: apalis/colibri_imx6: Fix CLKO1/CLKO2 output
by Francesco Dolcini 24 Jun '22

24 Jun '22

Set CLK01 and CLK02 to 24MHz and enable it in CCM_CCOSR register. This clock is used by both the audio codec (CLKO1) and by the CSI camera (CLKO2) and is expected to be 24MHz. Despite the wrong 16.5MHz there was no real issue because of the wrong frequency since Linux reconfigures the clocks afterward, however this was triggering an issue with noise coming from the SGTL5000 audio codec. The problem is that the SGTL5000 does not have a reset pin and after it is configured if the input MCLK clock is disabled it produces a constant noise on its output, this was happening on software reboot. Forcing the clock to be enabled in U-Boot prevent the problem by making sure that the clock is always available, without this change as soon as Linux was changing the clock tree (setting clk_out_sel=1 without setting clko2_en=1) the noise would start till the actual clock was enabled (clko2_en=1) during the SGTL5000 driver probe. Signed-off-by: Francesco Dolcini <francesco.dolcini(a)toradex.com> --- board/toradex/apalis_imx6/apalis_imx6.c | 14 +++++++++----- board/toradex/colibri_imx6/colibri_imx6.c | 14 +++++++++----- 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 5604c4646cff..ea20de6b573e 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -1024,13 +1024,17 @@ static void ccgr_init(void) /* * Setup CCM_CCOSR register as follows: * - * cko1_en = 1 --> CKO1 enabled - * cko1_div = 111 --> divide by 8 - * cko1_sel = 1011 --> ahb_clk_root + * clko2_en = 1 --> CKO2 enabled + * clko2_div = 000 --> divide by 1 + * clko2_sel = 01110 --> osc_clk (24MHz) * - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + * clk_out_sel = 1 --> Output CKO2 to CKO1 + * + * This sets both CLKO2/CLKO1 output to 24MHz, + * CLKO1 configuration not relevant because of clk_out_sel + * (CLKO1 set to default) */ - writel(0x000000FB, &ccm->ccosr); + writel(0x010E0101, &ccm->ccosr); } static void ddr_init(int *table, int size) diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index 38ff637054aa..ab2ab587ffb6 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -980,13 +980,17 @@ static void ccgr_init(void) /* * Setup CCM_CCOSR register as follows: * - * cko1_en = 1 --> CKO1 enabled - * cko1_div = 111 --> divide by 8 - * cko1_sel = 1011 --> ahb_clk_root + * clko2_en = 1 --> CKO2 enabled + * clko2_div = 000 --> divide by 1 + * clko2_sel = 01110 --> osc_clk (24MHz) * - * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + * clk_out_sel = 1 --> Output CKO2 to CKO1 + * + * This sets both CLKO2/CLKO1 output to 24MHz, + * CLKO1 configuration not relevant because of clk_out_sel + * (CLKO1 set to default) */ - writel(0x000000FB, &ccm->ccosr); + writel(0x010E0101, &ccm->ccosr); } static void ddr_init(int *table, int size) -- 2.25.1

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[PATCH RESEND] riscv: fix compitible with binutils 2.38
by Coelacanthus 24 Jun '22

24 Jun '22

commit 6df2a016c0c8a3d0933ef33dd192ea6606b115e3 from linux kernel Since binutils 2.38, default ISA spec version switch to 20191213, in this version, original I extension be split into I, Zicsr and Zifencei. Zicsr is csr read/write (csrr*/csrw*) instructions, and Zifencei is fence.i instruction. This will cause compile error like this: Error: unrecognized opcode `csrr a5,0xc01' Error: unrecognized opcode `fence.i' This commit add code to detect new Zicsr and Zifencei extensions, and enable it when needed. Signed-off-by: Coelacanthus <coelacanthus(a)outlook.com> Cc: Rick Chen <rick(a)andestech.com> Cc: Leo <ycliang(a)andestech.com> --- arch/riscv/Makefile | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index 0b80eb8d86..62712f8d38 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -24,7 +24,14 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y) CMODEL = medany endif -ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \ +RISCV_MARCH_y = $(ARCH_BASE)$(ARCH_A)$(ARCH_C) + +# Newer binutils versions default to ISA spec version 20191213 which moves some +# instructions from the I extension to the Zicsr and Zifencei extensions. +toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH_y)_zicsr_zifencei) +RISCV_MARCH_$(toolchain-need-zicsr-zifencei) := $(RISCV_MARCH_y)_zicsr_zifencei + +ARCH_FLAGS = -march=$(RISCV_MARCH_y) -mabi=$(ABI) \ -mcmodel=$(CMODEL) PLATFORM_CPPFLAGS += $(ARCH_FLAGS) -- 2.36.1

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[PATCH v2] arm: dts: imx8mn-evk: sync dts from Linux Kernel
by Heiko Thiery 24 Jun '22

24 Jun '22

Sync dts for imx8mn-evk with Linux Kernel and change name for PMIC used in spl. This was synced with linux 5.19-rc3 and contains the following changes: commit 1cfa1e68af8d40ab233d5d27bc8446e4c5107571("arm64: dts: imx8mn-evk: fix the min/max voltages of the PMIC") commit bc046b952a5494b0dc53be28779460cee1214a3f("arm64: dts: imx8mn-evk: use proper names for PMIC outputs") Signed-off-by: Heiko Thiery <heiko.thiery(a)gmail.com> --- v2: - stated the kernel version the sync was done from (thanks Fabio) - update the patch subject to clarify that changes the evk dts (thanks Tim) arch/arm/dts/imx8mn-evk.dts | 56 ++++++++++++++++---------------- board/freescale/imx8mn_evk/spl.c | 4 +-- 2 files changed, 30 insertions(+), 30 deletions(-) diff --git a/arch/arm/dts/imx8mn-evk.dts b/arch/arm/dts/imx8mn-evk.dts index cd11fb28f5..4eb467df5b 100644 --- a/arch/arm/dts/imx8mn-evk.dts +++ b/arch/arm/dts/imx8mn-evk.dts @@ -31,7 +31,7 @@ }; &i2c1 { - pmic: pca9450@25 { + pmic: pmic@25 { compatible = "nxp,pca9450b"; reg = <0x25>; pinctrl-names = "default"; @@ -41,18 +41,18 @@ regulators { buck1: BUCK1{ - regulator-name = "BUCK1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; + regulator-name = "VDD_SOC"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; }; buck2: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; + regulator-name = "VDD_ARM_0V9"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; @@ -61,63 +61,63 @@ }; buck4: BUCK4{ - regulator-name = "BUCK4"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; buck5: BUCK5{ - regulator-name = "BUCK5"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; buck6: BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-name = "NVCC_DRAM_1V1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; regulator-boot-on; regulator-always-on; }; ldo1: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; + regulator-name = "NVCC_SNVS_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; ldo2: LDO2 { - regulator-name = "LDO2"; + regulator-name = "VDD_SNVS_0V8"; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; + regulator-max-microvolt = <800000>; regulator-boot-on; regulator-always-on; }; ldo3: LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; ldo4: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; + regulator-name = "VDD_PHY_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; regulator-boot-on; regulator-always-on; }; ldo5: LDO5 { - regulator-name = "LDO5"; + regulator-name = "NVCC_SD2"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c index 0d9909a662..a830407997 100644 --- a/board/freescale/imx8mn_evk/spl.c +++ b/board/freescale/imx8mn_evk/spl.c @@ -69,9 +69,9 @@ int power_init_board(void) struct udevice *dev; int ret; - ret = pmic_get("pca9450@25", &dev); + ret = pmic_get("pmic@25", &dev); if (ret == -ENODEV) { - puts("No pca9450@25\n"); + puts("No pmci@25\n"); return 0; } if (ret != 0) -- 2.30.2

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[PATCH 1/4] smccc: define generic IDs for feature discovery
by Etienne Carriere 23 Jun '22

23 Jun '22

Defines function IDs ARM_SMCCC_ARCH_FEATURES used to query SMCCC feature support, applicable from Arm SMCCC v1.1 specification. Defines macro ARM_SMCCC_RET_NOT_SUPPORTED as generic return identifier for when a SMCCC feature is not supported. Signed-off-by: Etienne Carriere <etienne.carriere(a)linaro.org> --- include/linux/arm-smccc.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index 7f2be23394..94a20c9793 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -51,6 +51,10 @@ #define ARM_SMCCC_QUIRK_NONE 0 #define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */ +#define ARM_SMCCC_ARCH_FEATURES 0x80000001 + +#define ARM_SMCCC_RET_NOT_SUPPORTED ((unsigned long)-1) + #ifndef __ASSEMBLY__ #include <linux/linkage.h> -- 2.25.1

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[PATCH 1/3] mmc: stm32_sdmmc2: cosmetic: rename stm32_sdmmc_bind
by Patrick Delaunay 23 Jun '22

23 Jun '22

Rename stm32_sdmmc_bind to stm32_sdmmc2_bind as all oter function in SDMMCv2 driver Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- drivers/mmc/stm32_sdmmc2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index 81b07609a91..e3853b7fbfb 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -763,7 +763,7 @@ clk_free: return ret; } -static int stm32_sdmmc_bind(struct udevice *dev) +static int stm32_sdmmc2_bind(struct udevice *dev) { struct stm32_sdmmc2_plat *plat = dev_get_plat(dev); @@ -781,7 +781,7 @@ U_BOOT_DRIVER(stm32_sdmmc2) = { .of_match = stm32_sdmmc2_ids, .ops = &stm32_sdmmc2_ops, .probe = stm32_sdmmc2_probe, - .bind = stm32_sdmmc_bind, + .bind = stm32_sdmmc2_bind, .priv_auto = sizeof(struct stm32_sdmmc2_priv), .plat_auto = sizeof(struct stm32_sdmmc2_plat), }; -- 2.25.1

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[PATCH 1/2] pmic: pca9450: Add optional SD_VSEL GPIO for LDO5
by Frieder Schrempf 23 Jun '22

23 Jun '22

From: Frieder Schrempf <frieder.schrempf(a)kontron.de> LDO5 has two separate control registers. LDO5CTRL_L is used if the input signal SD_VSEL is low and LDO5CTRL_H if it is high. The current driver implementation only uses LDO5CTRL_H. To make this work on boards that have SD_VSEL connected to a GPIO, we add support for specifying an optional GPIO and setting it to high at probe time. In the future we might also want to add support for boards that have SD_VSEL set to a fixed low level. In this case we need to change the driver to be able to use the LDO5CTRL_L register. This is a port of the same change in the Linux kernel: 8c67a11bae88 ("regulator: pca9450: Add SD_VSEL GPIO for LDO5") Signed-off-by: Frieder Schrempf <frieder.schrempf(a)kontron.de> --- drivers/power/pmic/pca9450.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index 116ac49a8db..6b9befba18c 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -7,9 +7,12 @@ #include <fdtdec.h> #include <errno.h> #include <dm.h> +#include <dm/device_compat.h> #include <i2c.h> +#include <linux/err.h> #include <log.h> #include <asm/global_data.h> +#include <asm-generic/gpio.h> #include <power/pmic.h> #include <power/regulator.h> #include <power/pca9450.h> @@ -26,6 +29,10 @@ static const struct pmic_child_info pmic_children_info[] = { { }, }; +struct pca9450_priv { + struct gpio_desc *sd_vsel_gpio; +}; + static int pca9450_reg_count(struct udevice *dev) { return PCA9450_REG_NUM; @@ -76,6 +83,24 @@ static int pca9450_bind(struct udevice *dev) return 0; } +static int pca9450_probe(struct udevice *dev) +{ + struct pca9450_priv *priv = dev_get_priv(dev); + int ret = 0; + + if (IS_ENABLED(CONFIG_DM_GPIO) && IS_ENABLED(CONFIG_DM_REGULATOR_PCA9450)) { + priv->sd_vsel_gpio = devm_gpiod_get_optional(dev, "sd-vsel", + GPIOD_IS_OUT | + GPIOD_IS_OUT_ACTIVE); + if (IS_ERR(priv->sd_vsel_gpio)) { + ret = PTR_ERR(priv->sd_vsel_gpio); + dev_err(dev, "Failed to request SD_VSEL GPIO: %d\n", ret); + } + } + + return ret; +} + static struct dm_pmic_ops pca9450_ops = { .reg_count = pca9450_reg_count, .read = pca9450_read, @@ -94,5 +119,7 @@ U_BOOT_DRIVER(pmic_pca9450) = { .id = UCLASS_PMIC, .of_match = pca9450_ids, .bind = pca9450_bind, + .probe = pca9450_probe, .ops = &pca9450_ops, + .priv_auto = sizeof(struct pca9450_priv), }; -- 2.36.1

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[PATCH 1/2] imx: kontron-sl-mx8mm: Sync dts files and fix ethernet
by Frieder Schrempf 23 Jun '22

23 Jun '22

From: Frieder Schrempf <frieder.schrempf(a)kontron.de> This syncs the devicetree files with the latest Linux kernel (5.19-rc2). This also fixes the currently broken ethernet support: Before: Net: Could not get PHY for FEC0: addr 0 After: Net: eth0: ethernet@30be0000 Signed-off-by: Frieder Schrempf <frieder.schrempf(a)kontron.de> --- arch/arm/dts/imx8mm-kontron-n801x-s.dts | 48 +++------------------- arch/arm/dts/imx8mm-kontron-n801x-som.dtsi | 6 +-- 2 files changed, 8 insertions(+), 46 deletions(-) diff --git a/arch/arm/dts/imx8mm-kontron-n801x-s.dts b/arch/arm/dts/imx8mm-kontron-n801x-s.dts index c796d144e22..23be1ec538b 100644 --- a/arch/arm/dts/imx8mm-kontron-n801x-s.dts +++ b/arch/arm/dts/imx8mm-kontron-n801x-s.dts @@ -6,7 +6,6 @@ /dts-v1/; #include "imx8mm-kontron-n801x-som.dtsi" -#include <dt-bindings/net/mscc-phy-vsc8531.h> / { model = "Kontron i.MX8MM N801X S"; @@ -81,7 +80,6 @@ regulator-name = "vdd-5v"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - regulator-always-on; }; }; @@ -124,38 +122,14 @@ #size-cells = <0>; ethphy: ethernet-phy@0 { - compatible = "ethernet-phy-id0007.0570"; reg = <0>; - reset-assert-us = <100>; - reset-deassert-us = <100>; + reset-assert-us = <1>; + reset-deassert-us = <15000>; reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; - vsc8531,led-0-mode = <VSC8531_LINK_100_1000_ACTIVITY>; - vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>; - vsc8531,led-0-combine-disable; }; }; }; -&gpio4 { - dsi_mux_sel: dsi_mux_sel { - gpio-hog; - gpios = <14 GPIO_ACTIVE_HIGH>; - output-high; - line-name = "dsi-mux-sel"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dsi_sel>; - }; - - dsi_mux_oe { - gpio-hog; - gpios = <15 GPIO_ACTIVE_LOW>; - output-high; - line-name = "dsi-mux-oe"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dsi_oe>; - }; -}; - &i2c4 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -208,7 +182,7 @@ #address-cells = <1>; #size-cells = <0>; - usbnet: usbether@1 { + usbnet: ethernet@1 { compatible = "usb424,ec00"; reg = <1>; local-mac-address = [ 00 00 00 00 00 00 ]; @@ -237,18 +211,6 @@ >; }; - pinctrl_dsi_sel: dsiselgrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 - >; - }; - - pinctrl_dsi_oe: dsioegrp { - fsl,pins = < - MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 - >; - }; - pinctrl_ecspi2: ecspi2grp { fsl,pins = < MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 @@ -362,7 +324,7 @@ >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 @@ -374,7 +336,7 @@ >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 diff --git a/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi b/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi index c3418d263eb..8f90eb02550 100644 --- a/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi +++ b/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi @@ -63,10 +63,10 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; status = "okay"; - spi-flash@0 { + flash@0 { compatible = "mxicy,mx25r1635f", "jedec,spi-nor"; spi-max-frequency = <80000000>; reg = <0>; @@ -154,7 +154,7 @@ reg_vdd_snvs: LDO2 { regulator-name = "ldo2"; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <800000>; + regulator-max-microvolt = <900000>; regulator-boot-on; regulator-always-on; }; -- 2.36.1

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