May 2022 - U-Boot

[PATCH] ARM: stm32mp: correctly handle Silicon revision
by Patrick Delaunay 10 May '22

10 May '22

Handle correctly the silicon revision = REV_ID[15:0] of Device Version and the associated device marking, A to Z on STMicroelectronics STM32MP SOCs. This patch prepare the introduction of next STM32MP family, with STM32MP13x Rev.Z for REV_ID = 1.1. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/mach-stm32mp/cpu.c | 6 +++--- arch/arm/mach-stm32mp/include/mach/sys_proto.h | 9 +++++---- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index 325d710100..0ad5f307db 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -432,13 +432,13 @@ static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg, /* Revision */ switch (get_cpu_rev()) { - case CPU_REVA: + case CPU_REV1: *rev = 1; break; - case CPU_REVB: + case CPU_REV2: *rev = 2; break; - case CPU_REVZ: + case CPU_REV2_1: *rev = 3; break; default: diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index 4149d3a133..b91f98eb45 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -25,11 +25,12 @@ u32 get_cpu_type(void); /* return CPU_DEV constants */ u32 get_cpu_dev(void); -#define CPU_REVA 0x1000 -#define CPU_REVB 0x2000 -#define CPU_REVZ 0x2001 +#define CPU_REV1 0x1000 +#define CPU_REV1_1 0x1001 +#define CPU_REV2 0x2000 +#define CPU_REV2_1 0x2001 -/* return CPU_REV constants */ +/* return Silicon revision = REV_ID[15:0] of Device Version */ u32 get_cpu_rev(void); /* Get Package options from OTP */ -- 2.25.1

2 2

[PATCH] ARM: stm32mp: skip ft_system_setup when the soc node is absent
by Patrick Delaunay 10 May '22

10 May '22

The function ft_system_setup should don't return an error when the /soc node is absent in the provided device tree but just skip the updates. This patch solves an issue when the U-Boot pytest is executed on board. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/mach-stm32mp/fdt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c index 91330a68a4..b1a4b76566 100644 --- a/arch/arm/mach-stm32mp/fdt.c +++ b/arch/arm/mach-stm32mp/fdt.c @@ -260,6 +260,9 @@ int ft_system_setup(void *blob, struct bd_info *bd) char name[SOC_NAME_SIZE]; soc = fdt_path_offset(blob, "/soc"); + /* when absent, nothing to do */ + if (soc == -FDT_ERR_NOTFOUND) + return 0; if (soc < 0) return soc; -- 2.25.1

2 3

[PATCH 1/2] configs: stm32mp1: set the console variable for extlinux.conf
by Patrick Delaunay 10 May '22

10 May '22

Set the environment variable "console", used in extlinux.conf file when it is generated by YOCTO distribution with: UBOOT_EXTLINUX_CONSOLE ??= "console=${console},${baudrate}" With these 2 variables, U-Boot give dynamically the used console and baudrate in the Linux kernel bootargs. For the STMicroelectronics boards, the used console is ttySTM0. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- include/configs/stm32mp15_st_common.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h index 10248bffc1..e8dad004c6 100644 --- a/include/configs/stm32mp15_st_common.h +++ b/include/configs/stm32mp15_st_common.h @@ -8,6 +8,9 @@ #ifndef __CONFIG_STM32MP15_ST_COMMON_H__ #define __CONFIG_STM32MP15_ST_COMMON_H__ +#define STM32MP_BOARD_EXTRA_ENV \ + "console=ttySTM0\0" + #include <configs/stm32mp15_common.h> #ifdef CONFIG_EXTRA_ENV_SETTINGS -- 2.25.1

2 5

[PATCH] board: st: common: fix the error messages in stboard command
by Patrick Delaunay 10 May '22

10 May '22

Add missing \n at the end of the error trace Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- board/st/common/cmd_stboard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/st/common/cmd_stboard.c b/board/st/common/cmd_stboard.c index c1ecd643b0..e12669b862 100644 --- a/board/st/common/cmd_stboard.c +++ b/board/st/common/cmd_stboard.c @@ -92,14 +92,14 @@ static int do_stboard(struct cmd_tbl *cmdtp, int flag, int argc, &otp, sizeof(otp)); if (ret != sizeof(otp)) { - puts("OTP read error"); + puts("OTP read error\n"); return CMD_RET_FAILURE; } ret = misc_read(dev, STM32_BSEC_LOCK(BSEC_OTP_BOARD), &lock, sizeof(lock)); if (ret != sizeof(lock)) { - puts("LOCK read error"); + puts("LOCK read error\n"); return CMD_RET_FAILURE; } -- 2.25.1

2 2

[PATCH] video: stm32: stm32_ltdc: support several hardware versions
by Yannick Fertre 10 May '22

10 May '22

Register mapping & pixel formats depend on version of ltdc display controller. Signed-off-by: Yannick Fertre <yannick.fertre(a)foss.st.com> --- drivers/video/stm32/stm32_ltdc.c | 245 +++++++++++++++++++++++++++---- 1 file changed, 216 insertions(+), 29 deletions(-) diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c index e741e74739..60bfd2390d 100644 --- a/drivers/video/stm32/stm32_ltdc.c +++ b/drivers/video/stm32/stm32_ltdc.c @@ -25,8 +25,114 @@ struct stm32_ltdc_priv { void __iomem *regs; enum video_log2_bpp l2bpp; u32 bg_col_argb; + const u32 *layer_regs; + const u32 *pix_fmt_hw; u32 crop_x, crop_y, crop_w, crop_h; u32 alpha; + u32 hw_version; +}; + +/* Layer register offsets */ +static const u32 layer_regs_a0[] = { + 0x80, /* L1 configuration 0 */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x84, /* L1 control register */ + 0x88, /* L1 window horizontal position configuration */ + 0x8c, /* L1 window vertical position configuration */ + 0x90, /* L1 color keying configuration */ + 0x94, /* L1 pixel format configuration */ + 0x98, /* L1 constant alpha configuration */ + 0x9c, /* L1 default color configuration */ + 0xa0, /* L1 blending factors configuration */ + 0x00, /* not available */ + 0x00, /* not available */ + 0xac, /* L1 color frame buffer address */ + 0xb0, /* L1 color frame buffer length */ + 0xb4, /* L1 color frame buffer line number */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0xc4, /* L1 CLUT write */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00 /* not available */ +}; + +static const u32 layer_regs_a1[] = { + 0x80, /* L1 configuration 0 */ + 0x84, /* L1 configuration 1 */ + 0x00, /* L1 reload control */ + 0x88, /* L1 control register */ + 0x8c, /* L1 window horizontal position configuration */ + 0x90, /* L1 window vertical position configuration */ + 0x94, /* L1 color keying configuration */ + 0x98, /* L1 pixel format configuration */ + 0x9c, /* L1 constant alpha configuration */ + 0xa0, /* L1 default color configuration */ + 0xa4, /* L1 blending factors configuration */ + 0xa8, /* L1 burst length configuration */ + 0x00, /* not available */ + 0xac, /* L1 color frame buffer address */ + 0xb0, /* L1 color frame buffer length */ + 0xb4, /* L1 color frame buffer line number */ + 0xb8, /* L1 auxiliary frame buffer address 0 */ + 0xbc, /* L1 auxiliary frame buffer address 1 */ + 0xc0, /* L1 auxiliary frame buffer length */ + 0xc4, /* L1 auxiliary frame buffer line number */ + 0xc8, /* L1 CLUT write */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00, /* not available */ + 0x00 /* not available */ +}; + +static const u32 layer_regs_a2[] = { + 0x100, /* L1 configuration 0 */ + 0x104, /* L1 configuration 1 */ + 0x108, /* L1 reload control */ + 0x10c, /* L1 control register */ + 0x110, /* L1 window horizontal position configuration */ + 0x114, /* L1 window vertical position configuration */ + 0x118, /* L1 color keying configuration */ + 0x11c, /* L1 pixel format configuration */ + 0x120, /* L1 constant alpha configuration */ + 0x124, /* L1 default color configuration */ + 0x128, /* L1 blending factors configuration */ + 0x12c, /* L1 burst length configuration */ + 0x130, /* L1 planar configuration */ + 0x134, /* L1 color frame buffer address */ + 0x138, /* L1 color frame buffer length */ + 0x13c, /* L1 color frame buffer line number */ + 0x140, /* L1 auxiliary frame buffer address 0 */ + 0x144, /* L1 auxiliary frame buffer address 1 */ + 0x148, /* L1 auxiliary frame buffer length */ + 0x14c, /* L1 auxiliary frame buffer line number */ + 0x150, /* L1 CLUT write */ + 0x154, /* not available */ + 0x158, /* not available */ + 0x15c, /* not available */ + 0x160, /* not available */ + 0x164, /* not available */ + 0x168, /* not available */ + 0x16c, /* L1 Conversion YCbCr RGB 0 */ + 0x170, /* L1 Conversion YCbCr RGB 1 */ + 0x174, /* L1 Flexible Pixel Format 0 */ + 0x178 /* L1 Flexible Pixel Format 1 */ }; /* LTDC main registers */ @@ -49,26 +155,32 @@ struct stm32_ltdc_priv { #define LTDC_CPSR 0x44 /* Current Position Status */ #define LTDC_CDSR 0x48 /* Current Display Status */ -/* LTDC layer 1 registers */ -#define LTDC_L1LC1R 0x80 /* L1 Layer Configuration 1 */ -#define LTDC_L1LC2R 0x84 /* L1 Layer Configuration 2 */ -#define LTDC_L1CR 0x84 /* L1 Control */ -#define LTDC_L1WHPCR 0x88 /* L1 Window Hor Position Config */ -#define LTDC_L1WVPCR 0x8C /* L1 Window Vert Position Config */ -#define LTDC_L1CKCR 0x90 /* L1 Color Keying Configuration */ -#define LTDC_L1PFCR 0x94 /* L1 Pixel Format Configuration */ -#define LTDC_L1CACR 0x98 /* L1 Constant Alpha Config */ -#define LTDC_L1DCCR 0x9C /* L1 Default Color Configuration */ -#define LTDC_L1BFCR 0xA0 /* L1 Blend Factors Configuration */ -#define LTDC_L1FBBCR 0xA4 /* L1 FrameBuffer Bus Control */ -#define LTDC_L1AFBCR 0xA8 /* L1 AuxFB Control */ -#define LTDC_L1CFBAR 0xAC /* L1 Color FrameBuffer Address */ -#define LTDC_L1CFBLR 0xB0 /* L1 Color FrameBuffer Length */ -#define LTDC_L1CFBLNR 0xB4 /* L1 Color FrameBuffer Line Nb */ -#define LTDC_L1AFBAR 0xB8 /* L1 AuxFB Address */ -#define LTDC_L1AFBLR 0xBC /* L1 AuxFB Length */ -#define LTDC_L1AFBLNR 0xC0 /* L1 AuxFB Line Number */ -#define LTDC_L1CLUTWR 0xC4 /* L1 CLUT Write */ +/* Layer register offsets */ +#define LTDC_L1C0R (priv->layer_regs[0]) /* L1 configuration 0 */ +#define LTDC_L1C1R (priv->layer_regs[1]) /* L1 configuration 1 */ +#define LTDC_L1RCR (priv->layer_regs[2]) /* L1 reload control */ +#define LTDC_L1CR (priv->layer_regs[3]) /* L1 control register */ +#define LTDC_L1WHPCR (priv->layer_regs[4]) /* L1 window horizontal position configuration */ +#define LTDC_L1WVPCR (priv->layer_regs[5]) /* L1 window vertical position configuration */ +#define LTDC_L1CKCR (priv->layer_regs[6]) /* L1 color keying configuration */ +#define LTDC_L1PFCR (priv->layer_regs[7]) /* L1 pixel format configuration */ +#define LTDC_L1CACR (priv->layer_regs[8]) /* L1 constant alpha configuration */ +#define LTDC_L1DCCR (priv->layer_regs[9]) /* L1 default color configuration */ +#define LTDC_L1BFCR (priv->layer_regs[10]) /* L1 blending factors configuration */ +#define LTDC_L1BLCR (priv->layer_regs[11]) /* L1 burst length configuration */ +#define LTDC_L1PCR (priv->layer_regs[12]) /* L1 planar configuration */ +#define LTDC_L1CFBAR (priv->layer_regs[13]) /* L1 color frame buffer address */ +#define LTDC_L1CFBLR (priv->layer_regs[14]) /* L1 color frame buffer length */ +#define LTDC_L1CFBLNR (priv->layer_regs[15]) /* L1 color frame buffer line number */ +#define LTDC_L1AFBA0R (priv->layer_regs[16]) /* L1 auxiliary frame buffer address 0 */ +#define LTDC_L1AFBA1R (priv->layer_regs[17]) /* L1 auxiliary frame buffer address 1 */ +#define LTDC_L1AFBLR (priv->layer_regs[18]) /* L1 auxiliary frame buffer length */ +#define LTDC_L1AFBLNR (priv->layer_regs[19]) /* L1 auxiliary frame buffer line number */ +#define LTDC_L1CLUTWR (priv->layer_regs[20]) /* L1 CLUT write */ +#define LTDC_L1CYR0R (priv->layer_regs[27]) /* L1 Conversion YCbCr RGB 0 */ +#define LTDC_L1CYR1R (priv->layer_regs[28]) /* L1 Conversion YCbCr RGB 1 */ +#define LTDC_L1FPF0R (priv->layer_regs[29]) /* L1 Flexible Pixel Format 0 */ +#define LTDC_L1FPF1R (priv->layer_regs[30]) /* L1 Flexible Pixel Format 1 */ /* Bit definitions */ #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ @@ -144,15 +256,60 @@ struct stm32_ltdc_priv { #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ #define BF2_1CA 0x005 /* 1 - Constant Alpha */ +#define NB_PF 8 /* Max nb of HW pixel format */ + +#define HWVER_10200 0x010200 +#define HWVER_10300 0x010300 +#define HWVER_20101 0x020101 +#define HWVER_40100 0x040100 + enum stm32_ltdc_pix_fmt { - PF_ARGB8888 = 0, - PF_RGB888, - PF_RGB565, - PF_ARGB1555, - PF_ARGB4444, - PF_L8, - PF_AL44, - PF_AL88 + PF_ARGB8888 = 0, /* ARGB [32 bits] */ + PF_ABGR8888, /* ABGR [32 bits] */ + PF_BGRA8888, /* BGRA [32 bits] */ + PF_RGBA8888, /* RGBA [32 bits] */ + PF_RGB888, /* RGB [24 bits] */ + PF_BGR565, /* RGB [16 bits] */ + PF_RGB565, /* RGB [16 bits] */ + PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ + PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ + PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ + PF_AL88, /* Alpha:8 bits + indexed 8 bits [16 bits] */ + PF_L8, /* Indexed 8 bits [8 bits] */ + PF_NONE +}; + +static const enum stm32_ltdc_pix_fmt pix_fmt_a0[NB_PF] = { + PF_ARGB8888, /* 0x00 */ + PF_RGB888, /* 0x01 */ + PF_RGB565, /* 0x02 */ + PF_ARGB1555, /* 0x03 */ + PF_ARGB4444, /* 0x04 */ + PF_L8, /* 0x05 */ + PF_AL44, /* 0x06 */ + PF_AL88 /* 0x07 */ +}; + +static const enum stm32_ltdc_pix_fmt pix_fmt_a1[NB_PF] = { + PF_ARGB8888, /* 0x00 */ + PF_RGB888, /* 0x01 */ + PF_RGB565, /* 0x02 */ + PF_RGBA8888, /* 0x03 */ + PF_AL44, /* 0x04 */ + PF_L8, /* 0x05 */ + PF_ARGB1555, /* 0x06 */ + PF_ARGB4444 /* 0x07 */ +}; + +static const enum stm32_ltdc_pix_fmt pix_fmt_a2[NB_PF] = { + PF_ARGB8888, /* 0x00 */ + PF_ABGR8888, /* 0x01 */ + PF_RGBA8888, /* 0x02 */ + PF_BGRA8888, /* 0x03 */ + PF_RGB565, /* 0x04 */ + PF_BGR565, /* 0x05 */ + PF_RGB888, /* 0x06 */ + PF_NONE /* 0x07 (flexible pixel format) */ }; /* TODO add more color format support */ @@ -306,7 +463,16 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr) /* Pixel format */ format = stm32_ltdc_get_pixel_format(priv->l2bpp); - clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, format); + for (val = 0; val < NB_PF; val++) + if (priv->pix_fmt_hw[val] == format) + break; + + if (val >= NB_PF) { + log_err("invalid pixel format\n"); + return; + } + + clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, val); /* Constant alpha value */ clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha); @@ -359,6 +525,27 @@ static int stm32_ltdc_probe(struct udevice *dev) return ret; } + priv->hw_version = readl(priv->regs + LTDC_IDR); + debug("%s: LTDC hardware 0x%x\n", __func__, priv->hw_version); + + switch (priv->hw_version) { + case HWVER_10200: + case HWVER_10300: + priv->layer_regs = layer_regs_a0; + priv->pix_fmt_hw = pix_fmt_a0; + break; + case HWVER_20101: + priv->layer_regs = layer_regs_a1; + priv->pix_fmt_hw = pix_fmt_a1; + break; + case HWVER_40100: + priv->layer_regs = layer_regs_a2; + priv->pix_fmt_hw = pix_fmt_a2; + break; + default: + return -ENODEV; + } + ret = uclass_first_device_err(UCLASS_PANEL, &panel); if (ret) { if (ret != -ENODEV) -- 2.25.1

2 2

[PATCH] video: stm32: stm32_ltdc: fix data enable polarity
by Yannick FERTRE 10 May '22

10 May '22

Wrong DISPLAY_FLAGS used to set the data enable polarity. Signed-off-by: Yannick FERTRE <yannick.fertre(a)foss.st.com> --- drivers/video/stm32/stm32_ltdc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c index e741e74739..9269d4bfb4 100644 --- a/drivers/video/stm32/stm32_ltdc.c +++ b/drivers/video/stm32/stm32_ltdc.c @@ -255,7 +255,7 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv, val |= GCR_HSPOL; if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH) val |= GCR_VSPOL; - if (timings->flags & DISPLAY_FLAGS_DE_HIGH) + if (timings->flags & DISPLAY_FLAGS_DE_LOW) val |= GCR_DEPOL; if (timings->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) val |= GCR_PCPOL; -- 2.25.1

2 2

[PATCH 0/8] stm32mp: command stm32prog improvements
by Patrick Delaunay 10 May '22

10 May '22

Several patches to improve the command stm32prog command. This command is used to program the STMicroelectronics boards with the tools STM32CubeProgrammer and flashlayout file. Patrick Delaunay (8): stm32mp: stm32prog: fix comment stm32mp: stm32prog: add CONFIG_CMD_STM32PROG_OTP stm32mp: stm32prog: add TEE support in stm32prog command stm32mp: stm32prog: add support of STM32IMAGE version 2 stm32mp: stm32prog: add support of UUID for FIP partition stm32mp: stm32prog: handle interruption during the first enumeration stm32mp: stm32prog: handle U-Boot script in flashlayout alternate stm32mp: stm32prog: handle flashlayout without STM32 image header arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig | 7 + .../cmd_stm32prog/cmd_stm32prog.c | 13 +- .../mach-stm32mp/cmd_stm32prog/stm32prog.c | 418 ++++++++++++++---- .../mach-stm32mp/cmd_stm32prog/stm32prog.h | 47 +- .../cmd_stm32prog/stm32prog_usb.c | 9 +- 5 files changed, 378 insertions(+), 116 deletions(-) -- 2.25.1

2 24

[PATCH 1/1] cmd/sbi: add implementation ID 6 - Coffer
by Heinrich Schuchardt 10 May '22

10 May '22

The sbi command displays the ID of the implementation of the RISC-V Supervisor Binary Interface Specification. A new ID for Coffer has recently been added. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- cmd/riscv/sbi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index 8fc8ab0ac5..ee11e0f88e 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -26,6 +26,7 @@ static struct sbi_imp implementations[] = { { 3, "KVM" }, { 4, "RustSBI" }, { 5, "Diosix" }, + { 6, "Coffer" }, }; static struct sbi_ext extensions[] = { -- 2.34.1

2 1

[PATCH] Nokia RX-51: Enable CONFIG_SUPPORT_RAW_INITRD
by Pali Rohár 09 May '22

09 May '22

This enable booting of Debian systems which use raw initrd image (instead of uInitrd created by mkimage). This change increase size of u-boot.bin binary by just 64 bytes. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- Debian has for this support own custom patch: https://sources.debian.org/patches/u-boot/2022.04+dfsg-2/n900/bootz_and_raw… --- configs/nokia_rx51_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig index d5688c7a212b..2e8068876eae 100644 --- a/configs/nokia_rx51_defconfig +++ b/configs/nokia_rx51_defconfig @@ -18,6 +18,7 @@ CONFIG_OPTIMIZE_INLINING=y CONFIG_LTO=y # CONFIG_SYS_MALLOC_F is not set # CONFIG_FIT is not set +CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOOTDELAY=30 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_MENU_SHOW=y -- 2.20.1

2 1

[PATCH 1/3] ARM: dts: am335x: guardian: switch to AM33XX_PADCONF
by Gireesh.Hiremath＠in.bosch.com 09 May '22

09 May '22

From: Gireesh Hiremath <Gireesh.Hiremath(a)in.bosch.com> switch the pin definitions from AM33XX_IOPAD to AM33XX_PADCONF macro Signed-off-by: Gireesh Hiremath <Gireesh.Hiremath(a)in.bosch.com> --- arch/arm/dts/am335x-guardian-u-boot.dtsi | 2 +- arch/arm/dts/am335x-guardian.dts | 214 +++++++++++++---------- 2 files changed, 119 insertions(+), 97 deletions(-) diff --git a/arch/arm/dts/am335x-guardian-u-boot.dtsi b/arch/arm/dts/am335x-guardian-u-boot.dtsi index a1a7913de8..29d8147014 100644 --- a/arch/arm/dts/am335x-guardian-u-boot.dtsi +++ b/arch/arm/dts/am335x-guardian-u-boot.dtsi @@ -82,7 +82,7 @@ lcd0_pins: pinmux_lcd0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLUP | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLUP, MUX_MODE7) >; }; }; diff --git a/arch/arm/dts/am335x-guardian.dts b/arch/arm/dts/am335x-guardian.dts index 69bee45848..067c402885 100644 --- a/arch/arm/dts/am335x-guardian.dts +++ b/arch/arm/dts/am335x-guardian.dts @@ -388,167 +388,189 @@ clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < - AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) + AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) >; }; dmtimer7_pins: pinmux_dmtimer7_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5) + AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE5) >; }; guardian_button_pins: pinmux_gpio_keys_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x884, PIN_INPUT | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT, MUX_MODE7) >; }; guardian_interface_pins: pinmux_guardian_interface_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x990, PIN_OUTPUT_PULLUP | MUX_MODE7) - AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE7) - AM33XX_IOPAD(0x90c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x944, PIN_OUTPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x91c, PIN_INPUT | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_OUTPUT_PULLDOWN | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLUP, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_OUTPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT, MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_OUTPUT_PULLDOWN, MUX_MODE7) >; }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) >; }; lcd_disen_pins: pinmux_lcd_disen_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_MCASP0_FSR, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW, MUX_MODE7) >; }; lcd_pins_default: pinmux_lcd_pins_default { pinctrl-single,pins = < - AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1) - AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) - AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) + AM33XX_PADCONF + (AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT | SLEWCTRL_SLOW, MUX_MODE0) >; }; lcd_pins_sleep: pinmux_lcd_pins_sleep { pinctrl-single,pins = < - AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) - AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_LCD_DATA0, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_LCD_DATA1, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_LCD_DATA2, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_LCD_DATA3, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_LCD_DATA4, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_LCD_DATA5, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_LCD_DATA6, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_LCD_DATA7, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_LCD_DATA8, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_LCD_DATA9, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_LCD_DATA10, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_LCD_DATA11, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_LCD_DATA12, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_LCD_DATA13, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_LCD_DATA14, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_LCD_DATA15, PULL_DISABLE | SLEWCTRL_SLOW, MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW, MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW, MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW, MUX_MODE7) + AM33XX_PADCONF + (AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW, MUX_MODE7) >; }; guardian_led_pins: pinmux_leds_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_OUTPUT, MUX_MODE7) >; }; mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) >; }; spi0_pins: pinmux_spi0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0) - AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT_PULLUP, MUX_MODE0) >; }; uart0_pins: pinmux_uart0_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) >; }; uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE1) - AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) + AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) >; }; nandflash_pins: pinmux_nandflash_pins { pinctrl-single,pins = < - AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0) - AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0) - AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) - AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) + AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) >; }; }; -- 2.20.1

2 8