May 2022 - U-Boot

[PATCH] phy: zynqmp: Increase timeout value to 10ms
by Ashok Reddy Soma 16 May '22

16 May '22

Observing psgtr pll timeouts with some usb hubs and devices behind it. Increase timeout to 10ms to take care of it. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> --- drivers/phy/phy-zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/phy-zynqmp.c b/drivers/phy/phy-zynqmp.c index 08c1b6efcf..d1288bb17f 100644 --- a/drivers/phy/phy-zynqmp.c +++ b/drivers/phy/phy-zynqmp.c @@ -168,7 +168,7 @@ enum { }; /* Timeout values */ -#define TIMEOUT_US 1000 +#define TIMEOUT_US 10000 #define IOU_SLCR_GEM_CLK_CTRL 0x308 #define GEM_CTRL_GEM_SGMII_MODE BIT(2) -- 2.17.1

2 1

[PATCH 0/3] xilinx: Swith platforms to DM_ETH_PHY
by Michal Simek 16 May '22

16 May '22

This patch series adds support for shared MDIO by using generic phy framework. Also enable DM_ETH_PHY config for all xilinx platforms. Thanks, Michal T Karthik Reddy (3): net: xilinx: axi_emac: Use shared MDIO bus support for axi emac driver net: xilinx: axi_emaclite: Use shared MDIO bus support for axi emaclite driver xilinx: Add CONFIG_DM_ETH_PHY config configs/microblaze-generic_defconfig | 1 + configs/xilinx_versal_virt_defconfig | 1 + configs/xilinx_zynq_virt_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 1 + drivers/net/xilinx_axi_emac.c | 38 ++++++++++++++++-------- drivers/net/xilinx_emaclite.c | 43 ++++++++++++++++++---------- 6 files changed, 58 insertions(+), 27 deletions(-) -- 2.36.0

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[PATCH] arm64: zynqmp: Set qspi tx-buswidth to 4
by Michal Simek 16 May '22

16 May '22

From: Amit Kumar Mahapatra <amit.kumar-mahapatra(a)xilinx.com> In all the ZynqMP boards dts files tx-buswidth is by default set to 1. Due to this the framework only issues 1-1-1 write commands to the GQSPI driver. But the GQSPI controller is capable of handling 1-4-4 write commands, so updated the tx-buswidth to 4 in ZynqMP boards dts files. This would enable the spi-nor framework to issue 1-4-4 write commands instead of 1-1-1. This will increase the tx data transfer rate, as now the tx data will be transferred on four lines instead on single line. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra(a)xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/dts/zynqmp-m-a2197-01-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-02-revA.dts | 2 +- arch/arm/dts/zynqmp-m-a2197-03-revA.dts | 2 +- arch/arm/dts/zynqmp-mini-qspi.dts | 2 +- arch/arm/dts/zynqmp-sm-k26-revA.dts | 2 +- arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts | 2 +- arch/arm/dts/zynqmp-zc1232-revA.dts | 2 +- arch/arm/dts/zynqmp-zc1254-revA.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts | 2 +- arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts | 2 +- arch/arm/dts/zynqmp-zcu102-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu104-revC.dts | 2 +- arch/arm/dts/zynqmp-zcu106-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu111-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu1275-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu208-revA.dts | 2 +- arch/arm/dts/zynqmp-zcu216-revA.dts | 2 +- 18 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index 86f2ccf4d951..7b3722f0808b 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -77,7 +77,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index e980fb07fc30..11b2a58a0f06 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -73,7 +73,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index c8c5100672fe..db199c467b0d 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -73,7 +73,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; }; diff --git a/arch/arm/dts/zynqmp-mini-qspi.dts b/arch/arm/dts/zynqmp-mini-qspi.dts index 9b4320fe6e20..20c21deb6673 100644 --- a/arch/arm/dts/zynqmp-mini-qspi.dts +++ b/arch/arm/dts/zynqmp-mini-qspi.dts @@ -68,7 +68,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; }; diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 14ab31685dfe..e904cd8ea093 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -117,7 +117,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ partition@0 { diff --git a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts index 300e2ebe96e8..3750bb38b585 100644 --- a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts +++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts @@ -61,7 +61,7 @@ compatible = "st,m25p80", "n25q256a", "jedec,spi-nor"; m25p,fast-read; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <166000000>; #address-cells = <1>; diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts index 7543855c9fda..63c553f77242 100644 --- a/arch/arm/dts/zynqmp-zc1232-revA.dts +++ b/arch/arm/dts/zynqmp-zc1232-revA.dts @@ -44,7 +44,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts index 9cc1c0c6c5a7..343033cc7e88 100644 --- a/arch/arm/dts/zynqmp-zc1254-revA.dts +++ b/arch/arm/dts/zynqmp-zc1254-revA.dts @@ -45,7 +45,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 4a87bd6a6aaf..d20f6675687b 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -351,7 +351,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index f420f83ad208..e153a64f4fb6 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -173,7 +173,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 1b1cabb004ff..aac798d6e74a 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -948,7 +948,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 9cd30447eb3e..50bf47908913 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -434,7 +434,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 45191569c101..752a9e38f3d3 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -446,7 +446,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 50cc72eb9240..03624648cd71 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -942,7 +942,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index 2b15ce1ea847..021fe88670fb 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -784,7 +784,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index 10d8bc8f9a19..e88fc23b1f14 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -50,7 +50,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ partition@0 { /* for testing purpose */ diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 32a6e6fb55e2..c5cdd58af6ed 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -642,7 +642,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index 1e347036d0a7..caae16965d6f 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -653,7 +653,7 @@ #address-cells = <1>; #size-cells = <1>; reg = <0x0>; - spi-tx-bus-width = <1>; + spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ }; -- 2.36.0

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[PATCH] xilinx: zynqmp: Do not guard SPL_FS_LOAD_PAYLOAD_NAME by SDHCI driver
by Michal Simek 16 May '22

16 May '22

CONFIG_SPL_FS_LOAD_PAYLOAD_NAME is used by set_dfu_alt_info() for string generation. It doesn't depend on SDHCI because the same file can be stored to other non volatile memories like qspi. Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- include/configs/xilinx_zynqmp.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 8eb44b18d20c..f25d796a1e72 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -226,7 +226,6 @@ #define CONFIG_SPL_FS_LOAD_KERNEL_NAME "atf-uboot.ub" /* MMC support */ -#ifdef CONFIG_MMC_SDHCI_ZYNQ # define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* unused */ # define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* unused */ # if defined(CONFIG_SPL_LOAD_FIT) @@ -234,7 +233,6 @@ # else # define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" # endif -#endif #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU) # define CONFIG_SPL_HASH -- 2.36.0

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[PATCH] arm64: zynqmp: Fix split mode reset functionality
by Michal Simek 16 May '22

16 May '22

From: Neal Frager <neal.frager(a)amd.com> This patch fixes two issues in the set_r5_reset function. 1. When in split mode, the lpd_amba_rst bit should only be set when both r5 cpu cores are in reset. Otherwise, if one r5 core is still running, setting the lpd_amba_rst bit will cause an error for the running core. The set_r5_reset function has been modified to check if the other r5 core is still running before setting the lpd_amba_rst bit. 2. The cpu_disable function was always assuming that the r5 cores are in split mode when resetting either core 4 or 5. This is incorrect for lockstep functionality. This patch adds a function check_r5_mode to handle the cpu_disable function correctly for the r5 cores by checking the mode and handling the reset appropriately. Signed-off-by: Neal Frager <neal.frager(a)amd.com> Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- arch/arm/mach-zynqmp/mp.c | 31 +++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index 704520e7a3c9..4f1ed44afb6b 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -102,13 +102,21 @@ static void set_r5_reset(u32 nr, u8 mode) u32 tmp; tmp = readl(&crlapb_base->rst_lpd_top); - if (mode == LOCK || nr == ZYNQMP_CORE_RPU0) - tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | - ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK); - - if (mode == LOCK || nr == ZYNQMP_CORE_RPU1) + if (mode == LOCK) { tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK | + ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK | ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK); + } else { + if (nr == ZYNQMP_CORE_RPU0) { + tmp |= ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK; + if (tmp & ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK) + tmp |= ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK; + } else { + tmp |= ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK; + if (tmp & ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK) + tmp |= ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK; + } + } writel(tmp, &crlapb_base->rst_lpd_top); } @@ -142,6 +150,17 @@ static void enable_clock_r5(void) udelay(0x500); } +static int check_r5_mode(void) +{ + u32 tmp; + + tmp = readl(&rpu_base->rpu_glbl_ctrl); + if (tmp & ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK) + return SPLIT; + + return LOCK; +} + int cpu_disable(u32 nr) { if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { @@ -149,7 +168,7 @@ int cpu_disable(u32 nr) val |= 1 << nr; writel(val, &crfapb_base->rst_fpd_apu); } else { - set_r5_reset(nr, SPLIT); + set_r5_reset(nr, check_r5_mode()); } return 0; -- 2.36.0

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[PATCH] arm64: zynqmp: zynqmp-zcu102-revA: Fix DP PLL configuration
by Michal Simek 16 May '22

16 May '22

From: Neal Frager <neal.frager(a)amd.com> This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu102-revA evaluation board. The Linux DP driver expects the DP to be using the following PLL config: - DP video PLL should use the VPLL (0x0) - DP audio PLL should use the RPLL (0x3) Register 0xFD1A0070 configures the DP video PLL. Register 0xFD1A0074 configures the DP audio PLL. Signed-off-by: Neal Frager <neal.frager(a)amd.com> Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c index 8ecd9ee90b5a..f99e06acf6ee 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zcu102-revA/psu_init_gpl.c @@ -85,8 +85,8 @@ static unsigned long psu_clock_init_data(void) psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010303U); - psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01012700U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U); psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011103U); psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); psu_mask_write(0xFD1A0064, 0x01003F07U, 0x01000200U); -- 2.36.0

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[PATCH] arm64: zynqmp: zynqmp-zcu106-revA: Fix DP PLL configuration
by Michal Simek 16 May '22

16 May '22

From: Neal Frager <neal.frager(a)amd.com> This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu106-revA evaluation board. The Linux DP driver expects the DP to be using the following PLL config: - DP video PLL should use the VPLL (0x0) - DP audio PLL should use the RPLL (0x3) Register 0xFD1A0070 configures the DP video PLL. Register 0xFD1A0074 configures the DP audio PLL. Signed-off-by: Neal Frager <neal.frager(a)amd.com> Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c index 15f0be1a43ad..cbc436289f55 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zcu106-revA/psu_init_gpl.c @@ -81,8 +81,8 @@ static unsigned long psu_clock_init_data(void) psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010203U); - psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C00U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U); psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011303U); psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); -- 2.36.0

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[PATCH] arm64: zynqmp: zynqmp-zcu106-rev1.0: Fix DP PLL configuration
by Michal Simek 16 May '22

16 May '22

From: Neal Frager <neal.frager(a)amd.com> This patch fixes the DP audio and video PLL configurations for the zynqmp-zcu106-rev1.0 evaluation board. The Linux DP driver expects the DP to be using the following PLL config: - DP video PLL should use the VPLL (0x0) - DP audio PLL should use the RPLL (0x3) Register 0xFD1A0070 configures the DP video PLL. Register 0xFD1A0074 configures the DP audio PLL. Signed-off-by: Neal Frager <neal.frager(a)amd.com> Signed-off-by: Michal Simek <michal.simek(a)amd.com> --- board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c index 2ac4e035d887..3dc9bf8f3a83 100644 --- a/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-zcu106-rev1.0/psu_init_gpl.c @@ -81,8 +81,8 @@ static unsigned long psu_clock_init_data(void) psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U); - psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010203U); - psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C00U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U); psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01011303U); psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); -- 2.36.0

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[PATCH v5 00/17] enable menu-driven boot device selection
by Masahisa Kojima 16 May '22

16 May '22

This patch series adds the menu-driven boot device selection, by extending the existing "bootmenu" to include UEFI and distro_boot related entries, and supports menu-driven UEFI boot variable maintenance. This patch series also includes the removable media support that UEFI specification requires to support. The menu example is as follows. *** U-Boot Boot Menu *** bootmenu_00 : Boot 1. kernel bootmenu_01 : Boot 2. kernel bootmenu_02 : Reset board UEFI BOOT0000 : debian UEFI BOOT0001 : ubuntu UEFI BOOT0002 : mmc0:1 UEFI BOOT0003 : mmc0:2 UEFI BOOT0004 : nvme0:1 UEFI BOOT0005 : nvme0:2 UEFI BOOT0006 : usb0:2 UEFI BOOT0007 : usb1:1 UEFI BOOT0008 : usb1:2 distro_boot : usb0 distro_boot : scsi0 distro_boot : virtio0 distro_boot : dhcp Press UP/DOWN to move, ENTER to select, ESC/CTRL+C to quit [How to run on QEMU(arm64)] 1) clone source code $ git clone https://git.linaro.org/people/masahisa.kojima/u-boot.git \ -b kojima/bootmenu_v5_upstream_0428 --depth 1 2) prepare U-Boot .config $ make qemu_arm64_menuconfig then, enable CONFIG_CMD_BOOTMENU and CONFIG_AUTOBOOT_MENU_SHOW 3) run on QEMU(arm64) example $ qemu-system-aarch64 -machine virt,gic-version=3 -cpu cortex-a57 -m 4G -nographic \ -no-acpi -bios ./u-boot.bin -hda xxx.img [Major Changes] - rebased to v2022.07-rc1 - there is detailed changelog in each commit AKASHI Takahiro (2): efi_loader: export efi_locate_device_handle() efi_loader: bootmgr: add booting from removable media Masahisa Kojima (15): lib/charset: add u16_strlcat() function test: unit test for u16_strlcat() menu: always show the menu regardless of the number of entry menu: menu_get_choice() return -ENOENT if menu item is empty bootmenu: flush input buffer before waiting user key input bootmenu: update bootmenu_entry structure bootmenu: add UEFI boot entry into bootmenu bootmenu: add distro boot entry bootmenu: add Kconfig option not to enter U-Boot console bootmenu: factor out the user input handling efi_loader: menu-driven addition of UEFI boot option efi_loader: menu-driven deletion of UEFI boot variable efi_loader: menu-driven update of UEFI bootorder variable bootmenu: add removable media entries doc:bootmenu: add UEFI boot and distro boot support description cmd/Kconfig | 10 + cmd/bootmenu.c | 807 +++++++++---- common/menu.c | 142 ++- doc/usage/cmd/bootmenu.rst | 78 +- include/charset.h | 17 + include/config_distro_bootcmd.h | 14 +- include/efi_default_filename.h | 33 + include/efi_loader.h | 61 + include/menu.h | 20 + lib/charset.c | 22 + lib/efi_loader/Makefile | 1 + lib/efi_loader/efi_bootmenu_maintenance.c | 1245 +++++++++++++++++++++ lib/efi_loader/efi_bootmgr.c | 50 +- lib/efi_loader/efi_boottime.c | 59 +- lib/efi_loader/efi_console.c | 81 ++ lib/efi_loader/efi_disk.c | 11 + lib/efi_loader/efi_file.c | 75 +- test/unicode_ut.c | 50 + 18 files changed, 2518 insertions(+), 258 deletions(-) create mode 100644 include/efi_default_filename.h create mode 100644 lib/efi_loader/efi_bootmenu_maintenance.c -- 2.17.1

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Clarification on mtd: nand: mxs_nand_spl: Remove the page aligned access
by Michael Nazzareno Trimarchi 16 May '22

16 May '22

Hi Tim and Ye Can I know if this was a fix, a cleanup or other? The commit message is not clear to me. Michael -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 michael(a)amarulasolutions.com __________________________________ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 info(a)amarulasolutions.com www.amarulasolutions.com

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