May 2022 - U-Boot

[PATCH v6 00/25] Add support for MediaTek MT7621 SoC - v6
by Weijie Gao 08 Jul '22

08 Jul '22

This series will add support for MediaTek MT7621 SoC with two reference boards and related drivers. The MediaTek MT7621 is a network processor integrating a dual-core dual-threaded MIPS 1004Kc processor running at a normal frequency of 880MHz. This chip can be found in many wireless routers. This series add all basic drivers which are useful in u-boot, like usb, sdxc, ethernet, spi, nand and serial. Building the u-boot requires external binary blob which is described in doc/board/mediatek/mt7621.rst Thanks, Weijie v6 changes: - Use FIELD_GET/FIELD_PREP for register fields instead of shift opertations - Rename fixed clock node name in mt7621.dtsi - Panic if dram binary blob is wrong in spl - Remove redundant nop's if noreorder is not used - Use execution_hazard_barrier() in tpl v5 changes: - Adjust mt7621.dtsi, clkctrl node moved to sysc, pinctrl default states moved to board dts files - Modify clk driver due to its node changed in mt7621.dtsi - Minor fixes v4 changes: - Add full support for booting from flash v3 changes: - Rewrite clk driver to follow definitions from upstream kernel - Implement noncached_alloc() for MIPS platform - Update register remap for mtk-eth driver needed by mt7621 v2 changes: - Add a kconfig for max supported ram size - Remove network configs from default config file - Add config file for mt7621-rfb boards Weijie Gao (25): mips: add asm/mipsmtregs.h for MIPS multi-threading mips: add more definitions for asm/cm.h mips: add __image_copy_len for SPL linker script mips: add support for noncached_alloc() mips: mtmips: add support for MediaTek MT7621 SoC mips: mtmips: add two reference boards for mt7621 doc: mediatek: add documentation for mt7621 reference boards clk: mtmips: add clock driver for MediaTek MT7621 SoC reset: mtmips: add reset controller support for MediaTek MT7621 SoC pinctrl: mtmips: add support for MediaTek MT7621 SoC usb: xhci-mtk: add support for MediaTek MT7621 SoC phy: mtk-tphy: add support for MediaTek MT7621 SoC spi: add support for MediaTek MT7621 SoC gpio: add support for MediaTek MT7621 SoC watchdog: add support for MediaTek MT7621 SoC mmc: mediatek: add support for MediaTek MT7621 SoC net: mediatek: remap iobase address net: mediatek: use regmap api to modify ethsys registers net: mediatek: add support for MediaTek MT7621 SoC nand: raw: add support for MediaTek MT7621 SoC spl: allow using nand base without standard nand driver spl: spl_legacy: fix the use of SPL_COPY_PAYLOAD_ONLY spl: nand: support loading legacy image with payload compressed tools: mtk_image: add support for MT7621 NAND images MAINTAINERS: update maintainer for MediaTek MIPS platform MAINTAINERS | 8 + arch/mips/cpu/u-boot-spl.lds | 3 + arch/mips/dts/Makefile | 2 + arch/mips/dts/mediatek,mt7621-nand-rfb.dts | 67 + arch/mips/dts/mediatek,mt7621-rfb.dts | 82 ++ arch/mips/dts/mt7621-u-boot.dtsi | 111 ++ arch/mips/dts/mt7621.dtsi | 349 +++++ arch/mips/include/asm/cm.h | 67 + arch/mips/include/asm/mipsmtregs.h | 142 ++ arch/mips/include/asm/system.h | 20 + arch/mips/lib/cache.c | 43 + arch/mips/mach-mtmips/Kconfig | 49 +- arch/mips/mach-mtmips/Makefile | 4 + arch/mips/mach-mtmips/cpu.c | 2 +- arch/mips/mach-mtmips/mt7621/Kconfig | 115 ++ arch/mips/mach-mtmips/mt7621/Makefile | 14 + arch/mips/mach-mtmips/mt7621/init.c | 246 ++++ arch/mips/mach-mtmips/mt7621/mt7621.h | 229 ++++ arch/mips/mach-mtmips/mt7621/serial.c | 23 + arch/mips/mach-mtmips/mt7621/spl/Makefile | 9 + arch/mips/mach-mtmips/mt7621/spl/cps.c | 153 +++ arch/mips/mach-mtmips/mt7621/spl/dram.c | 153 +++ arch/mips/mach-mtmips/mt7621/spl/dram.h | 39 + arch/mips/mach-mtmips/mt7621/spl/launch.c | 100 ++ arch/mips/mach-mtmips/mt7621/spl/launch.h | 52 + arch/mips/mach-mtmips/mt7621/spl/launch_ll.S | 339 +++++ arch/mips/mach-mtmips/mt7621/spl/serial.c | 24 + arch/mips/mach-mtmips/mt7621/spl/spl.c | 95 ++ arch/mips/mach-mtmips/mt7621/spl/start.S | 226 ++++ arch/mips/mach-mtmips/mt7621/sram_init.S | 22 + arch/mips/mach-mtmips/mt7621/tpl/Makefile | 4 + arch/mips/mach-mtmips/mt7621/tpl/start.S | 161 +++ arch/mips/mach-mtmips/mt7621/tpl/tpl.c | 144 ++ board/mediatek/mt7621/MAINTAINERS | 8 + board/mediatek/mt7621/Makefile | 3 + board/mediatek/mt7621/board.c | 6 + common/spl/Kconfig | 2 +- common/spl/spl_legacy.c | 21 +- common/spl/spl_nand.c | 27 + configs/mt7621_nand_rfb_defconfig | 83 ++ configs/mt7621_rfb_defconfig | 82 ++ doc/board/mediatek/mt7621.rst | 48 + drivers/clk/mtmips/Makefile | 1 + drivers/clk/mtmips/clk-mt7621.c | 288 ++++ drivers/gpio/Kconfig | 2 +- drivers/mmc/mtk-sd.c | 13 + drivers/mtd/nand/raw/Kconfig | 17 +- drivers/mtd/nand/raw/Makefile | 2 + drivers/mtd/nand/raw/mt7621_nand.c | 1205 +++++++++++++++++ drivers/mtd/nand/raw/mt7621_nand.h | 29 + drivers/mtd/nand/raw/mt7621_nand_spl.c | 237 ++++ drivers/net/mtk_eth.c | 45 +- drivers/phy/Kconfig | 2 +- drivers/pinctrl/mtmips/Kconfig | 9 + drivers/pinctrl/mtmips/Makefile | 1 + drivers/pinctrl/mtmips/pinctrl-mt7621.c | 306 +++++ .../pinctrl/mtmips/pinctrl-mtmips-common.c | 4 +- .../pinctrl/mtmips/pinctrl-mtmips-common.h | 12 + drivers/spi/Kconfig | 2 +- drivers/usb/host/Kconfig | 2 +- drivers/watchdog/Kconfig | 2 +- include/configs/mt7621.h | 67 + include/dt-bindings/clock/mt7621-clk.h | 46 + include/dt-bindings/reset/mt7621-reset.h | 38 + tools/mtk_image.c | 182 +++ tools/mtk_image.h | 24 + 66 files changed, 5877 insertions(+), 36 deletions(-) create mode 100644 arch/mips/dts/mediatek,mt7621-nand-rfb.dts create mode 100644 arch/mips/dts/mediatek,mt7621-rfb.dts create mode 100644 arch/mips/dts/mt7621-u-boot.dtsi create mode 100644 arch/mips/dts/mt7621.dtsi create mode 100644 arch/mips/include/asm/mipsmtregs.h create mode 100644 arch/mips/mach-mtmips/mt7621/Kconfig create mode 100644 arch/mips/mach-mtmips/mt7621/Makefile create mode 100644 arch/mips/mach-mtmips/mt7621/init.c create mode 100644 arch/mips/mach-mtmips/mt7621/mt7621.h create mode 100644 arch/mips/mach-mtmips/mt7621/serial.c create mode 100644 arch/mips/mach-mtmips/mt7621/spl/Makefile create mode 100644 arch/mips/mach-mtmips/mt7621/spl/cps.c create mode 100644 arch/mips/mach-mtmips/mt7621/spl/dram.c create mode 100644 arch/mips/mach-mtmips/mt7621/spl/dram.h create mode 100644 arch/mips/mach-mtmips/mt7621/spl/launch.c create mode 100644 arch/mips/mach-mtmips/mt7621/spl/launch.h create mode 100644 arch/mips/mach-mtmips/mt7621/spl/launch_ll.S create mode 100644 arch/mips/mach-mtmips/mt7621/spl/serial.c create mode 100644 arch/mips/mach-mtmips/mt7621/spl/spl.c create mode 100644 arch/mips/mach-mtmips/mt7621/spl/start.S create mode 100644 arch/mips/mach-mtmips/mt7621/sram_init.S create mode 100644 arch/mips/mach-mtmips/mt7621/tpl/Makefile create mode 100644 arch/mips/mach-mtmips/mt7621/tpl/start.S create mode 100644 arch/mips/mach-mtmips/mt7621/tpl/tpl.c create mode 100644 board/mediatek/mt7621/MAINTAINERS create mode 100644 board/mediatek/mt7621/Makefile create mode 100644 board/mediatek/mt7621/board.c create mode 100644 configs/mt7621_nand_rfb_defconfig create mode 100644 configs/mt7621_rfb_defconfig create mode 100644 doc/board/mediatek/mt7621.rst create mode 100644 drivers/clk/mtmips/clk-mt7621.c create mode 100644 drivers/mtd/nand/raw/mt7621_nand.c create mode 100644 drivers/mtd/nand/raw/mt7621_nand.h create mode 100644 drivers/mtd/nand/raw/mt7621_nand_spl.c create mode 100644 drivers/pinctrl/mtmips/pinctrl-mt7621.c create mode 100644 include/configs/mt7621.h create mode 100644 include/dt-bindings/clock/mt7621-clk.h create mode 100644 include/dt-bindings/reset/mt7621-reset.h -- 2.17.1

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[PATCH] Kconfig: Fix SYS_MALLOC_F_LEN for i.MX8MQ
by Peng Fan (OSS) 07 Jul '22

07 Jul '22

From: Peng Fan <peng.fan(a)nxp.com> i.MX8MQ use SYS_MALLOC_F_LEN 0x2000, not 0x10000. The OCRAM_S only has 32KB memory, use 0x10000 will make SPL not bootable. Signed-off-by: Peng Fan <peng.fan(a)nxp.com> --- Kconfig | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Kconfig b/Kconfig index 6b1ddfc549e..3e95ec9d7b9 100644 --- a/Kconfig +++ b/Kconfig @@ -251,8 +251,10 @@ config SYS_MALLOC_F_LEN default 0x4000 if SANDBOX || RISCV default 0x2000 if (ARCH_MX7 || ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5 || \ ARCH_QEMU || ARCH_SUNXI || ARCH_OWL) - default 0x10000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_LS1012A || \ - ARCH_LS1021A || ARCH_LS1043A || ARCH_LS1046A) + default 0x10000 if (ARCH_IMX8 || (ARCH_IMX8M && !IMX8MQ) || \ + ARCH_LS1012A || ARCH_LS1021A || ARCH_LS1043A || \ + ARCH_LS1046A) + default 0x2000 if IMX8MQ default 0x400 help Before relocation, memory is very limited on many platforms. Still, -- 2.35.1

6 9

[ANN] U-Boot v2022.01-rc3 released
by Tom Rini 06 Jul '22

06 Jul '22

Hey all, It's been two weeks since v2022.01-rc2, so here's -rc3. To repeat what I said with -rc2, we've enabled issue tracking on our gitlab instance. You can sign up and then be able to file issues at: https://source.denx.de/groups/u-boot/-/issues This is intended for everyone to be able to use, both custodians for their own needs (you can see for example Heinrich has filed something for UEFI and LMB) as well as users to just report bugs so they don't feel like they're lost in the mailing list. As noted with the last release, the -next branch is open and I'll sync in -rc3 shortly. Please feel free to get a PR ready now if you're able. In terms of a changelog, git log --merges v2022.01-rc2..v2022.01-rc3 contains what I've pulled but as always, better PR messages and tags will provide better results here. So we're now looking at regular releases every other Monday, and with final release on January 10th, 2022. Thanks all! -- Tom

2 5

[PATCH 0/9] dm: core: Support collecting and reporting stats
by Simon Glass 06 Jul '22

06 Jul '22

Driver model can use a lot of memory, as it is the core of all drivers and devices in U-Boot. Add a command to show how much is in use, along with the sizes of various data structures. This patch can be used to analyse the impact of various potential changes to driver model for SPL, none of which has been implemented. Most involve shrinking the size of struct udevice, which is a particular problem on 64-bit machines since their pointers are so unnecessarily large in SPL. To try this out, enable SPL_DM_STATS and then build and run on your board. You should see output for SPL and U-Boot proper, like this: Struct sizes: udevice 90, driver 78, uclass 30, uc_driver 78 Memory: device 11:990, device names 111, uclass a:1e0 Attached type Count Size Cur Tags Save --------------- ----- ----- ----- ----- ----- plat 3 e0 990 914 7c (124) parent_plat 2 40 990 910 80 (128) uclass_plat 1 10 990 90c 84 (132) priv 6 13d 990 920 70 (112) parent_priv 0 0 990 908 88 (136) uclass_priv 3 38 990 914 7c (124) driver_data 0 0 990 908 88 (136) uclass 0 0 Attached total f 2a5 37c (892) tags 0 0 Total size: e15 (3605) With tags: a99 (2713) - singly-linked: 901 (2305) - driver index: 88a (2186) - uclass index: 813 (2067) Drop device name (not SRAM): 111 (273) Simon Glass (9): dm: core: Rename dm_dump_all() dm: core: Sort dm subcommands dm: core: Fix addresses in the dm static command dm: core: Add documentation for the dm command dm: core: Switch the testbus driver to use a new struct dm: core: Support accessing core tags dm: core: Add a way to collect memory usage dm: core: Add a command to show driver model statistics dm: spl: Allow SPL to show memory usage cmd/dm.c | 69 ++++-- common/spl/spl.c | 9 + doc/usage/cmd/dm.rst | 487 ++++++++++++++++++++++++++++++++++++++++ doc/usage/index.rst | 1 + drivers/core/Kconfig | 21 ++ drivers/core/device.c | 65 ++++++ drivers/core/dump.c | 79 ++++++- drivers/core/root.c | 53 +++++ drivers/core/tag.c | 29 +++ drivers/misc/test_drv.c | 6 +- include/dm/device.h | 25 +++ include/dm/root.h | 45 ++++ include/dm/tag.h | 32 ++- include/dm/test.h | 7 + include/dm/util.h | 11 +- test/dm/core.c | 91 ++++++++ tools/dtoc/test_dtoc.py | 6 +- 17 files changed, 1004 insertions(+), 32 deletions(-) create mode 100644 doc/usage/cmd/dm.rst -- 2.36.0.512.ge40c2bad7a-goog

3 24

[RFC] Data structure for information handoff between firmware boot stages
by Jose Marinho 05 Jul '22

05 Jul '22

Hi All, The topic of information handoff between TF-A's BL31 and BL33 (e.g. U-boot proper, EDK2) was discussed last year in the TF-A and U-boot mailing lists [1], [2]. Examples of information to be handed off between firmware stages are the TPM log, HOB nodes, etc. Having a standard data structure which is usable/supported by every community contributes to code reuse and leads to simpler codebase maintenance. Some already existing data structures, such as the UEFI HOB list [3], and the Bloblist from U-boot, were proposed to be employed for the handoffs. There are pros and cons with both HOBs and Bloblist. The discussion settled with a consensus that a data structure ought to be defined which encapsulates the best traits of HOBs and Bloblist. Properties that the data structure should have: - node types identified by an integer, - easily relocatable, - straightforward to append new nodes, - easy to read and append to from resource constrained environments. The data structure should be suitable to pass information between different firmware stages, such as: U-boot SPL -> BL31 -> U-boot BL1 -> BL2 -> BL31 -> U-boot As requested in the ML, an initial proposal was drafted [4]. The document [4] is an initial proposal (at an alpha stage). The document [4] is being circulated for the purpose of gathering initial feedback. This proposal is closely aligned with an ongoing effort in the u-boot mailing list [5]. The proposal defines 1) a set of standard nodes and 2) the registers used at the handoff boundary. Standard nodes: - fdt node: HW description fdt, - HOB node, - ACPI table node: the main use-case for this node is to carry the TPM log. The document [4] accommodates an OEM range, which enables IMPDEF nodes to be caried in the handoff list. By definition, the nodes in the OEM range are not standard and can be defined per-platform. Note: the document [4] encapsulates the standard node definition as that is the simplest approach for feedback gathering. Once there is sufficient consensus around the proposal, the standard node definitions should be moved to a project independent repository. The repository location is TBD. The list of standard nodes is expected to grow with community contribution. Kind Regards, Jose [1] https://lists.trustedfirmware.org/archives/list/tf-a@lists.trustedfirmware.… [2] https://lore.kernel.org/u-boot/CAODwPW_FwFN1E84cV1+nC1aiahiwOL-TV=mP_6o8h0y… [3] https://uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf [4] https://developer.arm.com/documentation/den0135/a [5] https://lore.kernel.org/u-boot/20220113022625.413990-1-sjg@chromium.org/

2 6

[PATCH 0/5] Add support for versal specific cadence ospi driver
by Ashok Reddy Soma 04 Jul '22

04 Jul '22

This patch series does the following: * Move macros from cadence driver to cadence header file * Add new versal specific cadence ospi driver * Reset qspi flash in when driver probed * Enable/Disable apb linear mode based on dma usage * Fix cadence qspi flash speed programming T Karthik Reddy (5): spi: cadence-qspi: move cadence qspi macros to header file arm64: versal: Add versal specific cadence ospi driver spi: cadence-qspi: reset qspi flash for versal platform spi: cadence_qspi: Enable apb linear mode for apb read & write operations spi: cadence-qspi: Fix programming ospi flash speed MAINTAINERS | 1 + arch/arm/mach-versal/include/mach/hardware.h | 15 ++ configs/xilinx_versal_virt_defconfig | 2 + drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/cadence_ospi_versal.c | 237 +++++++++++++++++++ drivers/spi/cadence_qspi.c | 40 +++- drivers/spi/cadence_qspi.h | 189 +++++++++++++++ drivers/spi/cadence_qspi_apb.c | 163 +------------ include/zynqmp_firmware.h | 9 + 10 files changed, 510 insertions(+), 155 deletions(-) create mode 100644 drivers/spi/cadence_ospi_versal.c -- 2.17.1

3 7

[PATCH] mtd: spi-nor-ids: Add support for flashes tested by xilinx
by Ashok Reddy Soma 04 Jul '22

04 Jul '22

Add support for various flashes from below manufacturers which are tested by xilinx for years. EON: en25q128b GIGA: gd25lx256e ISSI: is25lp008 is25lp016 is25lp01g is25wp008 is25wp016 is25wp01g is25wx256 MACRONIX: mx25u51245f mx66u1g45g mx66l2g45g MICRON: mt35xl512aba mt35xu01g SPANSION: s70fs01gs_256k SST: sst26wf016b WINBOND: w25q16dw w25q16jv w25q512jv w25q32bv w25h02jv Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma(a)xilinx.com> --- drivers/mtd/spi/spi-nor-ids.c | 37 +++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 7050ddc397..5d8bf05ff8 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -82,6 +82,7 @@ const struct flash_info spi_nor_ids[] = { /* EON -- en25xxx */ { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) }, { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, + { INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) }, { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) }, { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, #endif @@ -127,11 +128,17 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) + }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ { INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25lp008", 0x9d6014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) }, + { INFO("is25lp016", 0x9d6015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) }, { INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) }, { INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) }, { INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256, @@ -140,6 +147,10 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ) }, { INFO("is25lp512", 0x9d601a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wp008", 0x9d7014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) }, + { INFO("is25wp016", 0x9d7015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) }, { INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128, @@ -151,6 +162,10 @@ const struct flash_info spi_nor_ids[] = { SPI_NOR_4B_OPCODES) }, { INFO("is25wp512", 0x9d701a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256, + SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */ /* Macronix */ @@ -176,8 +191,11 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) }, { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx25u51245f", 0xc2953a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx66u1g45g", 0xc2253b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, { INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) }, { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, @@ -208,8 +226,10 @@ const struct flash_info spi_nor_ids[] = { { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) }, #ifdef CONFIG_SPI_FLASH_MT35XU + { INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) }, #endif /* CONFIG_SPI_FLASH_MT35XU */ + { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, { INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */ @@ -225,6 +245,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO("s70fs01gs_256k", 0x010221, 0x4d00, 256 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) }, { INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) }, { INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, @@ -275,6 +296,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) }, { INFO("sst25wf080", 0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) }, { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("sst26wf016b", 0xbf2641, 0, 64 * 1024, 32, SECT_4K) }, { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_SST26LOCK) }, @@ -311,11 +333,19 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25q20bw", 0xef5012, 0, 64 * 1024, 4, SECT_4K) }, { INFO("w25q20ew", 0xef6012, 0, 64 * 1024, 4, SECT_4K) }, { INFO("w25q32", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { + INFO("w25q16dw", 0xef6015, 0, 64 * 1024, 32, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + }, { INFO("w25q32dw", 0xef6016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("w25q16jv", 0xef7015, 0, 64 * 1024, 32, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) + }, { INFO("w25q32jv", 0xef7016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | @@ -362,6 +392,11 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("w25q512jv", 0xef7119, 0, 64 * 1024, 512, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, { INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | @@ -370,6 +405,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) }, { INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("w25q32bv", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q64cv", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25q128", 0xef4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | @@ -378,6 +414,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif #ifdef CONFIG_SPI_FLASH_XMC /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ -- 2.17.1

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[PATCH 1/1] cmd: simplify do_adc_single()
by Heinrich Schuchardt 03 Jul '22

03 Jul '22

If argc is not < 3, it must be >= 3. If argc >= 3, argv[2] cannot be NULL. Fixes: 9de612ae4ded ("cmd: adc: Add support for storing ADC result in env variable") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- cmd/adc.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/cmd/adc.c b/cmd/adc.c index 8de9121cad..195efa8661 100644 --- a/cmd/adc.c +++ b/cmd/adc.c @@ -71,7 +71,6 @@ static int do_adc_info(struct cmd_tbl *cmdtp, int flag, int argc, static int do_adc_single(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - char *varname = NULL; struct udevice *dev; unsigned int data; int ret, uV, val; @@ -79,9 +78,6 @@ static int do_adc_single(struct cmd_tbl *cmdtp, int flag, int argc, if (argc < 3) return CMD_RET_USAGE; - if (argc >= 3) - varname = argv[2]; - ret = adc_channel_single_shot(argv[1], simple_strtol(argv[2], NULL, 0), &data); if (ret) { @@ -99,8 +95,7 @@ static int do_adc_single(struct cmd_tbl *cmdtp, int flag, int argc, printf("%u\n", data); } - if (varname) - env_set_ulong(varname, val); + env_set_ulong(argv[2], val); return CMD_RET_SUCCESS; } -- 2.34.1

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[PATCH v2] sunxi: psci: Fix sunxi_power_switch on sun8i-r40 platform
by qianfanguijin＠163.com 02 Jul '22

02 Jul '22

From: qianfan Zhao <qianfanguijin(a)163.com> linux system will die if we offline one of the cpu on R40 based board: eg: echo 0 > /sys/devices/system/cpu/cpu3/online Fixed sunxi_power_switch based on allwinner lichee 3.10 kernel driver. Signed-off-by: qianfan Zhao <qianfanguijin(a)163.com> --- v2 changes: Fix the commit message, the source code doesn't change. arch/arm/cpu/armv7/sunxi/psci.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index 1ac50f558a..63186a9388 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -79,8 +79,7 @@ static void __secure __mdelay(u32 ms) static void __secure clamp_release(u32 __maybe_unused *clamp) { #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \ - defined(CONFIG_MACH_SUN8I_H3) || \ - defined(CONFIG_MACH_SUN8I_R40) + defined(CONFIG_MACH_SUN8I_H3) u32 tmp = 0x1ff; do { tmp >>= 1; @@ -88,15 +87,30 @@ static void __secure clamp_release(u32 __maybe_unused *clamp) } while (tmp); __mdelay(10); +#elif defined(CONFIG_MACH_SUN8I_R40) + u8 i, tmp = 0xfe; + + for (i = 0; i < 5; i++) { /* 0xfe, 0xf8, 0xe0, 0x80, 0x00 */ + writel(tmp, clamp); + tmp <<= 2; + } + + while (0x00 != readl(clamp)) { + ; + } #endif } static void __secure clamp_set(u32 __maybe_unused *clamp) { #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || \ - defined(CONFIG_MACH_SUN8I_H3) || \ - defined(CONFIG_MACH_SUN8I_R40) + defined(CONFIG_MACH_SUN8I_H3) writel(0xff, clamp); +#elif defined(CONFIG_MACH_SUN8I_R40) + writel(0xff, clamp); + while (0xff != readl(clamp)) { + ; + } #endif } @@ -153,7 +167,7 @@ static void __secure sunxi_cpu_set_power(int cpu, bool on) sunxi_power_switch((void *)cpucfg + SUN8I_R40_PWR_CLAMP(cpu), (void *)cpucfg + SUN8I_R40_PWROFF, - on, 0); + on, cpu); } #else /* ! CONFIG_MACH_SUN7I && ! CONFIG_MACH_SUN8I_R40 */ static void __secure sunxi_cpu_set_power(int cpu, bool on) -- 2.25.1

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[PATCH v7 0/4] Add octal DTR support for Macronix flash
by JaimeLiao 01 Jul '22

01 Jul '22

This series add support for Macronix octal DTR flash, add flag for Softreset with "INVERT" command extension type on boot and follow linux kernel to enable 4byte opcode when possible. v7: Correct title and description of patchworks. Correct description for spi_nor_macronix_octal_dtr_enable. Add SFDP informations for flashes in commit log. v6: Parcing SCCR 22nd dword for checking Octal DTR mode support v5: Replace SPI_FLASH_MACRONIX_OCTAL with SPI_FLASH_MACRONIX. Remove patch of set_4byte opcode. v4: Add flag SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT to seperate command extension types. Replace ifdef with CONFIG_IS_ENABLED and modify uncorrect descriptions. v3: Add flag SPI_NOR_CMD_EXT_INVERT to seperate command extension types. replace CONFIG_SPI_FLASH_MACRONIX with SPI_FLASH_MACRONIX_OCTAL for spi_nor_macronix_octal_dtr_enable function. v2: add ret checking for write enable in spi_nor_macronix_octal_dtr_enable function. JaimeLiao (4): mtd: spi-nor: add support for Macronix Octal flash mtd: spi-nor-core: Adding different type of command extension in Soft Reset mtd: spi-nor: Parse SFDP SCCR Map mtd: spi-nor-core: Add support for Macronix Octal flash drivers/mtd/spi/Kconfig | 7 ++ drivers/mtd/spi/spi-nor-core.c | 141 ++++++++++++++++++++++++++++++++- drivers/mtd/spi/spi-nor-ids.c | 19 ++++- include/linux/mtd/spi-nor.h | 13 ++- 4 files changed, 176 insertions(+), 4 deletions(-) -- 2.17.1

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