May 2022 - U-Boot

[PATCH v2] spi: npcm-fiu: add NPCM7xx FIU controller driver
by Jagan Teki 04 May '22

04 May '22

From: Jim Liu <JJLIU0(a)nuvoton.com> Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI master controller driver using SPI-MEM interface. The FIU supports single, dual or quad communication interface. The FIU controller driver provides flash access in UMA(User Mode Access) mode by using an indirect address/data mechanism. the dts node is followed upstream kernel dts name. Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> Signed-off-by: Stanley Chu <yschu(a)nuvoton.com> Reviewed-by: Jagan Teki <jagan(a)amarulasolutions.com> [Jagan: fixed the Kconfig, Makefile order] Signed-off-by: Jagan Teki <jagan(a)amarulasolutions.com> --- Changes for v2: - fixed author e-mail - fixed Makefile and Kconfig order drivers/spi/Kconfig | 6 + drivers/spi/Makefile | 1 + drivers/spi/npcm_fiu_spi.c | 387 +++++++++++++++++++++++++++++++++++++ 3 files changed, 394 insertions(+) create mode 100644 drivers/spi/npcm_fiu_spi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 8dba95ae4e..a1e515cb2b 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -283,6 +283,12 @@ config SPI_MXIC can be used to access the SPI flash on platforms embedding this Macronix IP core. +config NPCM_FIU_SPI + bool "FIU driver for Nuvoton NPCM SoC" + help + This enables support for the Flash Interface Unit SPI controller + in master mode. + config NXP_FSPI bool "NXP FlexSPI driver" depends on SPI_MEM diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 7f43f843ca..06e81b465b 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o obj-$(CONFIG_MXC_SPI) += mxc_spi.o obj-$(CONFIG_MXS_SPI) += mxs_spi.o +obj-$(CONFIG_NPCM_FIU_SPI) += npcm_fiu_spi.o obj-$(CONFIG_NXP_FSPI) += nxp_fspi.o obj-$(CONFIG_ATCSPI200_SPI) += atcspi200_spi.o obj-$(CONFIG_OCTEON_SPI) += octeon_spi.o diff --git a/drivers/spi/npcm_fiu_spi.c b/drivers/spi/npcm_fiu_spi.c new file mode 100644 index 0000000000..7000fe5860 --- /dev/null +++ b/drivers/spi/npcm_fiu_spi.c @@ -0,0 +1,387 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Nuvoton Technology Corp. + * NPCM Flash Interface Unit(FIU) SPI master controller driver. + */ + +#include <clk.h> +#include <dm.h> +#include <spi.h> +#include <spi-mem.h> +#include <linux/bitfield.h> +#include <linux/log2.h> +#include <linux/iopoll.h> + +#define DW_SIZE 4 +#define CHUNK_SIZE 16 +#define XFER_TIMEOUT 1000000 + +/* FIU UMA Configuration Register (UMA_CFG) */ +#define UMA_CFG_RDATSIZ_MASK GENMASK(28, 24) +#define UMA_CFG_DBSIZ_MASK GENMASK(23, 21) +#define UMA_CFG_WDATSIZ_MASK GENMASK(20, 16) +#define UMA_CFG_ADDSIZ_MASK GENMASK(13, 11) +#define UMA_CFG_RDBPCK_MASK GENMASK(9, 8) +#define UMA_CFG_DBPCK_MASK GENMASK(7, 6) +#define UMA_CFG_WDBPCK_MASK GENMASK(5, 4) +#define UMA_CFG_ADBPCK_MASK GENMASK(3, 2) +#define UMA_CFG_CMBPCK_MASK GENMASK(1, 0) +#define UMA_CFG_CMDSIZ_SHIFT 10 + +/* FIU UMA Control and Status Register (UMA_CTS) */ +#define UMA_CTS_SW_CS BIT(16) +#define UMA_CTS_EXEC_DONE BIT(0) +#define UMA_CTS_RDYST BIT(24) +#define UMA_CTS_DEV_NUM_MASK GENMASK(9, 8) + +struct npcm_fiu_regs { + unsigned int drd_cfg; + unsigned int dwr_cfg; + unsigned int uma_cfg; + unsigned int uma_cts; + unsigned int uma_cmd; + unsigned int uma_addr; + unsigned int prt_cfg; + unsigned char res1[4]; + unsigned int uma_dw0; + unsigned int uma_dw1; + unsigned int uma_dw2; + unsigned int uma_dw3; + unsigned int uma_dr0; + unsigned int uma_dr1; + unsigned int uma_dr2; + unsigned int uma_dr3; + unsigned int prt_cmd0; + unsigned int prt_cmd1; + unsigned int prt_cmd2; + unsigned int prt_cmd3; + unsigned int prt_cmd4; + unsigned int prt_cmd5; + unsigned int prt_cmd6; + unsigned int prt_cmd7; + unsigned int prt_cmd8; + unsigned int prt_cmd9; + unsigned int stuff[4]; + unsigned int fiu_cfg; +}; + +struct npcm_fiu_priv { + struct npcm_fiu_regs *regs; + struct clk clk; +}; + +static int npcm_fiu_spi_set_speed(struct udevice *bus, uint speed) +{ + struct npcm_fiu_priv *priv = dev_get_priv(bus); + int ret; + + debug("%s: set speed %u\n", bus->name, speed); + ret = clk_set_rate(&priv->clk, speed); + if (ret < 0) + return ret; + + return 0; +} + +static int npcm_fiu_spi_set_mode(struct udevice *bus, uint mode) +{ + return 0; +} + +static inline void activate_cs(struct npcm_fiu_regs *regs, int cs) +{ + writel(FIELD_PREP(UMA_CTS_DEV_NUM_MASK, cs), &regs->uma_cts); +} + +static inline void deactivate_cs(struct npcm_fiu_regs *regs, int cs) +{ + writel(FIELD_PREP(UMA_CTS_DEV_NUM_MASK, cs) | UMA_CTS_SW_CS, &regs->uma_cts); +} + +static int fiu_uma_read(struct udevice *bus, u8 *buf, u32 size) +{ + struct npcm_fiu_priv *priv = dev_get_priv(bus); + struct npcm_fiu_regs *regs = priv->regs; + u32 data_reg[4]; + u32 val; + int ret; + + /* Set data size */ + writel(FIELD_PREP(UMA_CFG_RDATSIZ_MASK, size), &regs->uma_cfg); + + /* Initiate the read */ + writel(readl(&regs->uma_cts) | UMA_CTS_EXEC_DONE, &regs->uma_cts); + + /* Wait for completion */ + ret = readl_poll_timeout(&regs->uma_cts, val, + !(val & UMA_CTS_EXEC_DONE), XFER_TIMEOUT); + if (ret) { + printf("npcm_fiu: read timeout\n"); + return ret; + } + + /* Copy data from data registers */ + if (size) + data_reg[0] = readl(&regs->uma_dr0); + if (size > DW_SIZE) + data_reg[1] = readl(&regs->uma_dr1); + if (size > DW_SIZE * 2) + data_reg[2] = readl(&regs->uma_dr2); + if (size > DW_SIZE * 3) + data_reg[3] = readl(&regs->uma_dr3); + memcpy(buf, data_reg, size); + + return 0; +} + +static int fiu_uma_write(struct udevice *bus, const u8 *buf, u32 size) +{ + struct npcm_fiu_priv *priv = dev_get_priv(bus); + struct npcm_fiu_regs *regs = priv->regs; + u32 data_reg[4]; + u32 val; + int ret; + + /* Set data size */ + writel(FIELD_PREP(UMA_CFG_WDATSIZ_MASK, size), &regs->uma_cfg); + + /* Write data to data registers */ + memcpy(data_reg, buf, size); + if (size) + writel(data_reg[0], &regs->uma_dw0); + if (size > DW_SIZE) + writel(data_reg[1], &regs->uma_dw1); + if (size > DW_SIZE * 2) + writel(data_reg[2], &regs->uma_dw2); + if (size > DW_SIZE * 3) + writel(data_reg[3], &regs->uma_dw3); + + /* Initiate the transaction */ + writel(readl(&regs->uma_cts) | UMA_CTS_EXEC_DONE, &regs->uma_cts); + + /* Wait for completion */ + ret = readl_poll_timeout(&regs->uma_cts, val, + !(val & UMA_CTS_EXEC_DONE), XFER_TIMEOUT); + if (ret) + printf("npcm_fiu: write timeout\n"); + + return ret; +} + +static int npcm_fiu_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct npcm_fiu_priv *priv = dev_get_priv(bus); + struct npcm_fiu_regs *regs = priv->regs; + struct dm_spi_slave_plat *slave_plat = + dev_get_parent_plat(dev); + const u8 *tx = dout; + u8 *rx = din; + int bytes = bitlen / 8; + int ret = 0; + int len; + + if (flags & SPI_XFER_BEGIN) + activate_cs(regs, slave_plat->cs); + + while (bytes) { + len = (bytes > CHUNK_SIZE) ? CHUNK_SIZE : bytes; + if (tx) { + ret = fiu_uma_write(bus, tx, len); + if (ret) + break; + tx += len; + } else { + ret = fiu_uma_read(bus, rx, len); + if (ret) + break; + rx += len; + } + bytes -= len; + } + + if (flags & SPI_XFER_END) + deactivate_cs(regs, slave_plat->cs); + + return ret; +} + +static int npcm_fiu_uma_operation(struct npcm_fiu_priv *priv, const struct spi_mem_op *op, + u32 addr, const u8 *tx, u8 *rx, u32 nbytes, bool started) +{ + struct npcm_fiu_regs *regs = priv->regs; + u32 uma_cfg = 0, val; + u32 data_reg[4]; + int ret; + + debug("fiu_uma: opcode 0x%x, dir %d, addr 0x%x, %d bytes\n", + op->cmd.opcode, op->data.dir, addr, nbytes); + debug(" buswidth cmd:%d, addr:%d, dummy:%d, data:%d\n", + op->cmd.buswidth, op->addr.buswidth, op->dummy.buswidth, + op->data.buswidth); + debug(" size cmd:%d, addr:%d, dummy:%d, data:%d\n", + 1, op->addr.nbytes, op->dummy.nbytes, op->data.nbytes); + debug(" tx %p, rx %p\n", tx, rx); + + if (!started) { + /* Send cmd/addr in the begin of an transaction */ + writel(op->cmd.opcode, &regs->uma_cmd); + + uma_cfg |= FIELD_PREP(UMA_CFG_CMBPCK_MASK, ilog2(op->cmd.buswidth)) | + (1 << UMA_CFG_CMDSIZ_SHIFT); + /* Configure addr bytes */ + if (op->addr.nbytes) { + uma_cfg |= FIELD_PREP(UMA_CFG_ADBPCK_MASK, ilog2(op->addr.buswidth)) | + FIELD_PREP(UMA_CFG_ADDSIZ_MASK, op->addr.nbytes); + writel(addr, &regs->uma_addr); + } + /* Configure dummy bytes */ + if (op->dummy.nbytes) + uma_cfg |= FIELD_PREP(UMA_CFG_DBPCK_MASK, ilog2(op->dummy.buswidth)) | + FIELD_PREP(UMA_CFG_DBSIZ_MASK, op->dummy.nbytes); + } + /* Set data bus width and data size */ + if (op->data.dir == SPI_MEM_DATA_IN && nbytes) + uma_cfg |= FIELD_PREP(UMA_CFG_RDBPCK_MASK, ilog2(op->data.buswidth)) | + FIELD_PREP(UMA_CFG_RDATSIZ_MASK, nbytes); + else if (op->data.dir == SPI_MEM_DATA_OUT && nbytes) + uma_cfg |= FIELD_PREP(UMA_CFG_WDBPCK_MASK, ilog2(op->data.buswidth)) | + FIELD_PREP(UMA_CFG_WDATSIZ_MASK, nbytes); + writel(uma_cfg, &regs->uma_cfg); + + if (op->data.dir == SPI_MEM_DATA_OUT && nbytes) { + memcpy(data_reg, tx, nbytes); + + if (nbytes) + writel(data_reg[0], &regs->uma_dw0); + if (nbytes > DW_SIZE) + writel(data_reg[1], &regs->uma_dw1); + if (nbytes > DW_SIZE * 2) + writel(data_reg[2], &regs->uma_dw2); + if (nbytes > DW_SIZE * 3) + writel(data_reg[3], &regs->uma_dw3); + } + /* Initiate the transaction */ + writel(readl(&regs->uma_cts) | UMA_CTS_EXEC_DONE, &regs->uma_cts); + + /* Wait for completion */ + ret = readl_poll_timeout(&regs->uma_cts, val, + !(val & UMA_CTS_EXEC_DONE), XFER_TIMEOUT); + if (ret) { + printf("npcm_fiu: UMA op timeout\n"); + return ret; + } + + if (op->data.dir == SPI_MEM_DATA_IN && nbytes) { + if (nbytes) + data_reg[0] = readl(&regs->uma_dr0); + if (nbytes > DW_SIZE) + data_reg[1] = readl(&regs->uma_dr1); + if (nbytes > DW_SIZE * 2) + data_reg[2] = readl(&regs->uma_dr2); + if (nbytes > DW_SIZE * 3) + data_reg[3] = readl(&regs->uma_dr3); + + memcpy(rx, data_reg, nbytes); + } + + return 0; +} + +static int npcm_fiu_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + struct udevice *bus = slave->dev->parent; + struct npcm_fiu_priv *priv = dev_get_priv(bus); + struct npcm_fiu_regs *regs = priv->regs; + struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(slave->dev); + u32 bytes, len, addr; + const u8 *tx; + u8 *rx; + bool started = false; + int ret; + + bytes = op->data.nbytes; + addr = (u32)op->addr.val; + if (!bytes) { + activate_cs(regs, slave_plat->cs); + ret = npcm_fiu_uma_operation(priv, op, addr, NULL, NULL, 0, false); + deactivate_cs(regs, slave_plat->cs); + return ret; + } + + tx = op->data.buf.out; + rx = op->data.buf.in; + /* + * Use SW-control CS for write to extend the transaction and + * keep the Write Enable state. + * Use HW-control CS for read to avoid clock and timing issues. + */ + if (op->data.dir == SPI_MEM_DATA_OUT) + activate_cs(regs, slave_plat->cs); + else + writel(FIELD_PREP(UMA_CTS_DEV_NUM_MASK, slave_plat->cs) | UMA_CTS_SW_CS, + &regs->uma_cts); + while (bytes) { + len = (bytes > CHUNK_SIZE) ? CHUNK_SIZE : bytes; + ret = npcm_fiu_uma_operation(priv, op, addr, tx, rx, len, started); + if (ret) + return ret; + + /* CS is kept low for uma write, extend the transaction */ + if (op->data.dir == SPI_MEM_DATA_OUT) + started = true; + + bytes -= len; + addr += len; + if (tx) + tx += len; + if (rx) + rx += len; + } + if (op->data.dir == SPI_MEM_DATA_OUT) + deactivate_cs(regs, slave_plat->cs); + + return 0; +} + +static int npcm_fiu_spi_probe(struct udevice *bus) +{ + struct npcm_fiu_priv *priv = dev_get_priv(bus); + int ret; + + priv->regs = (struct npcm_fiu_regs *)dev_read_addr_ptr(bus); + + ret = clk_get_by_index(bus, 0, &priv->clk); + if (ret < 0) + return ret; + + return 0; +} + +static const struct spi_controller_mem_ops npcm_fiu_mem_ops = { + .exec_op = npcm_fiu_exec_op, +}; + +static const struct dm_spi_ops npcm_fiu_spi_ops = { + .xfer = npcm_fiu_spi_xfer, + .set_speed = npcm_fiu_spi_set_speed, + .set_mode = npcm_fiu_spi_set_mode, + .mem_ops = &npcm_fiu_mem_ops, +}; + +static const struct udevice_id npcm_fiu_spi_ids[] = { + { .compatible = "nuvoton,npcm845-fiu" }, + { .compatible = "nuvoton,npcm750-fiu" }, + { } +}; + +U_BOOT_DRIVER(npcm_fiu_spi) = { + .name = "npcm_fiu_spi", + .id = UCLASS_SPI, + .of_match = npcm_fiu_spi_ids, + .ops = &npcm_fiu_spi_ops, + .priv_auto = sizeof(struct npcm_fiu_priv), + .probe = npcm_fiu_spi_probe, +}; -- 2.25.1

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[PATCH 0/8] Add ASPEED SPI controller driver
by Chin-Ting Kuo 04 May '22

04 May '22

This patch series aims to porting ASPEED FMC/SPI memory controller driver with spi-mem interface. spi-mem dirmap framework is also synchronized from Linux. These patches have been verified on both AST2600 and AST2500 EVBs. Chin-Ting Kuo (8): clk: aspeed: Get HCLK frequency support pinctrl: aspeed: FWSPICS1 and SPI1CS1 pin support spi: aspeed: Add ASPEED SPI controller driver MAINTAINERS: Add ASPEED SPI driver file arm: dts: aspeed: Update SPI flash node settings spi-mem: Add dirmap API from Linux mtd: spi-nor: use spi-mem dirmap API spi: aspeed: SPI dirmap read support MAINTAINERS | 7 + arch/arm/dts/ast2500-evb.dts | 33 + arch/arm/dts/ast2500.dtsi | 23 +- arch/arm/dts/ast2600-evb.dts | 8 - arch/arm/dts/ast2600.dtsi | 34 +- configs/evb-ast2500_defconfig | 14 + configs/evb-ast2600_defconfig | 14 + drivers/clk/aspeed/clk_ast2500.c | 24 + drivers/mtd/spi/sf_probe.c | 82 ++ drivers/mtd/spi/spi-nor-core.c | 55 +- drivers/pinctrl/aspeed/pinctrl_ast2500.c | 2 + drivers/spi/Kconfig | 18 + drivers/spi/Makefile | 1 + drivers/spi/spi-aspeed.c | 915 +++++++++++++++++++++++ drivers/spi/spi-mem.c | 270 +++++++ include/linux/mtd/spi-nor.h | 18 + include/spi-mem.h | 98 +++ 17 files changed, 1570 insertions(+), 46 deletions(-) create mode 100644 drivers/spi/spi-aspeed.c -- 2.25.1

3 15

[PATCH v3 00/18] virtio: pci: Add and fix consistency checks
by Andrew Scull 04 May '22

04 May '22

The virtio PCI drivers forgo a number of consistency checks, particularly around pointer validation and bounds checking. This series focuses on the modern driver to add those checks. The start of the series adds and fixes some basic bounds checks. Later patches ensure PCI addresses fall within the expected regions rather than any arbitrary address. This is acheived by introducing range parameters to a few of the dm_pci_* functions that allow the ranges to be checked. The series also adds a few new configs to allow parts of virtio and PCI to be disabled where the features may be unused and the current implementations don't have the needed consistencty checks. Changelog: v2: - Refactor dm_pci_* functions, not adding new ones - Reorder patches per request in v1 v3: - Use CI to test more targets - Move EA config patch to end for dropping if needed Andrew Scull (18): virtio: pci: Allow exclusion of legacy driver virtio: pci: Fix discovery of device config length virtio: pci: Bounds check device config access virtio: pci: Bounds check notification writes virtio: pci: Check virtio common config size virtio: pci: Check virtio capability is in bounds virtio: pci: Read entire capability into memory pci: Fix use of flags in dm_pci_map_bar() pci: Check region ranges are addressable pci: Range check address conversions test: pci: Test PCI address conversion functions pci: Map bars with offset and length pci: Match region flags using a mask pci: Update dm_pci_bus_to_virt() parameters pci: Add mask parameter to dm_pci_map_bar() virtio: pci: Check virtio configs are mapped virtio: pci: Make use of dm_pci_map_bar() pci: Add config for Enhanced Allocation arch/sandbox/dts/test.dts | 2 +- arch/x86/cpu/baytrail/cpu.c | 2 +- drivers/ata/ahci.c | 9 +- drivers/ata/sata_sil.c | 6 +- drivers/bios_emulator/atibios.c | 4 +- drivers/gpio/octeon_gpio.c | 2 +- drivers/i2c/designware_i2c_pci.c | 3 +- drivers/i2c/intel_i2c.c | 2 +- drivers/i2c/octeon_i2c.c | 2 +- drivers/mmc/octeontx_hsmmc.c | 2 +- drivers/mmc/pci_mmc.c | 2 +- drivers/mtd/nand/raw/octeontx_bch.c | 6 +- drivers/mtd/nand/raw/octeontx_nand.c | 2 +- drivers/net/bnxt/bnxt.c | 9 +- drivers/net/e1000.c | 4 +- drivers/net/fsl_enetc.c | 2 +- drivers/net/fsl_enetc_mdio.c | 2 +- drivers/net/mscc_eswitch/felix_switch.c | 4 +- drivers/net/octeontx/bgx.c | 2 +- drivers/net/octeontx/nic_main.c | 2 +- drivers/net/octeontx/nicvf_main.c | 2 +- drivers/net/octeontx/smi.c | 2 +- drivers/net/octeontx2/cgx.c | 2 +- drivers/net/octeontx2/rvu_af.c | 2 +- drivers/net/octeontx2/rvu_pf.c | 3 +- drivers/net/pch_gbe.c | 2 +- drivers/nvme/nvme_pci.c | 4 +- drivers/pci/Kconfig | 7 + drivers/pci/pci-uclass.c | 185 +++++++++++------------- drivers/spi/octeon_spi.c | 2 +- drivers/usb/host/ehci-pci.c | 3 +- drivers/usb/host/ohci-pci.c | 2 +- drivers/usb/host/xhci-pci.c | 3 +- drivers/virtio/Kconfig | 9 ++ drivers/virtio/Makefile | 3 +- drivers/virtio/virtio_pci_legacy.c | 3 +- drivers/virtio/virtio_pci_modern.c | 143 ++++++++++++------ include/pci.h | 46 ++++-- test/dm/pci.c | 118 ++++++++++++++- 39 files changed, 401 insertions(+), 209 deletions(-) -- 2.36.0.rc2.479.g8af0fa9b8e-goog

3 24

[PATCH] CI: Azure: Rework how we update MSYS2
by Tom Rini 03 May '22

03 May '22

Based on reading https://www.msys2.org/docs/ci/ and "Other Systems" rework how we update MSYS2 to the current version. We run it once, to perform nothing other than being the first run, then we run pacman twice. Signed-off-by: Tom Rini <trini(a)konsulko.com> --- .azure-pipelines.yml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index f9acb9898ea9..3f211b86e4b2 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -22,8 +22,9 @@ stages: displayName: 'Install MSYS2' - script: | sfx.exe -y -o%CD:~0,2%\ - %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Syyuu" - %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Su" + %CD:~0,2%\msys64\usr\bin\bash -lc " " + %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Syuu" + %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm -Syuu" displayName: 'Update MSYS2' - script: | %CD:~0,2%\msys64\usr\bin\bash -lc "pacman --noconfirm --needed -Sy make gcc bison flex diffutils openssl-devel libgnutls-devel libutil-linux-devel" -- 2.25.1

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[PATCH v8 00/13] vpl: Introduce a verifying program loader
by Simon Glass 03 May '22

03 May '22

U-Boot provides a verified-boot feature based around FIT, but there is no standard way of implementing it for a board. At present the various required pieces must be built up separately, to produce a working implementation. In particular, there is no built-in support for selecting A/B boot or recovery mode. This series introduces VPL, a verified program loader phase for U-Boot. Its purpose is to run the verified-boot process and decide which SPL binary should be run. It is critical that this decision happens before SPL runs, since SPL sets up SDRAM and we need to be able to update the SDRAM-init code in the field. Adding VPL into the boot flow provides a standard place to implement verified boot. This series includes the phase itself, some useful Kconfig options and a sandbox_vpl build for sandbox. No verfied-boot support is provided in this series. Most of the patches in this series are fixes and improvements to docs and various Kconfig conditions for SPL. This series requires the earlier sandbox fix patches[1] to be applied first. A test is included to make sure that VPL runs correctly for sandbox, i.e. that the TPL -> VPL -> SPL -> U-Boot flow works. Future work will add an implementation of verified boot into VPL. [1] https://patchwork.ozlabs.org/project/uboot/list/?series=297248 Changes in v8: - Rename the VPL symbols in spl.c - Support SYSCON and REGMAP too - Update defconfig to account for option changes - Drop reference to old OF_HOSTFILE option - Add new patch to support running vpl tests Changes in v7: - Add a few more options - Rebase to master - Update some options based on settings in master Changes in v6: - Add docs for sandbox_vpl build - Drop TPL_HASH_SUPPORT patch since we only have SPL_HASH now Changes in v5: - Rebase this patch on mainline (for GPIO and MISC Kconfig renames) Changes in v4: - Add new patch to correct bloblist Kconfig dependencies - Add new patch to avoid building avb in SPL - Update spl_phase_prefix() for VPL - Tidy up some of the Makefile rules - Add options for blk, core, misc and tpl also - Add VPL_SIZE_LIMIT - Add a sandbox_vpl build - Update cover letter Changes in v3: - Move VPL Kconfig options to a separate patch - Add full build support for VPL - Add a VPL size check (Kconfig option in next patch) Changes in v2: - Add some more VPL Kconfig options Simon Glass (13): doc: Convert SPL documentation to ReST doc: Expand SPL docs to explain the phase and config test: Tidy up test building with SPL bloblist: Correct Kconfig dependencies avb: Don't build in SPL Makefile: Simplify devicetree rules for SPL/TPL Makefile: Tidy up the TPL build rules Introduce Verifying Program Loader (VPL) vpl: Add Kconfig options for VPL sandbox: Add a build for VPL vpl: Support running vpl tests vpl: Test that VPL runs correctly through to U-Boot proper CI: Run VPL tests .azure-pipelines.yml | 3 + .gitlab-ci.yml | 6 + Kconfig | 10 ++ Makefile | 28 +++- arch/sandbox/Kconfig | 8 + arch/sandbox/cpu/spl.c | 12 +- arch/sandbox/dts/sandbox.dtsi | 10 +- board/sandbox/MAINTAINERS | 7 + common/Kconfig | 71 +++++++- common/Makefile | 2 +- common/spl/Kconfig | 234 +++++++++++++++++++++++++- common/spl/spl.c | 25 ++- configs/sandbox_vpl_defconfig | 251 ++++++++++++++++++++++++++++ doc/arch/sandbox.rst | 13 ++ doc/develop/index.rst | 1 + doc/{README.SPL => develop/spl.rst} | 75 +++++++-- drivers/Makefile | 2 + drivers/block/Kconfig | 12 ++ drivers/clk/Kconfig | 26 +++ drivers/core/Kconfig | 54 +++++- drivers/core/Makefile | 2 +- drivers/gpio/Kconfig | 11 ++ drivers/i2c/Kconfig | 11 ++ drivers/misc/Kconfig | 28 ++++ drivers/pinctrl/Kconfig | 18 +- drivers/rtc/Kconfig | 9 + drivers/serial/Kconfig | 20 +++ drivers/sysreset/Kconfig | 10 ++ drivers/timer/Kconfig | 10 ++ drivers/tpm/Kconfig | 30 ++++ dts/Kconfig | 17 ++ include/bootstage.h | 2 + include/linux/kconfig.h | 3 + include/spl.h | 22 ++- lib/Kconfig | 62 +++++++ scripts/Kbuild.include | 4 + scripts/Makefile.autoconf | 12 ++ scripts/Makefile.build | 4 + scripts/Makefile.lib | 5 + scripts/Makefile.spl | 37 ++-- test/py/conftest.py | 7 +- test/py/tests/test_help.py | 12 ++ test/py/tests/test_vpl.py | 34 ++++ test/py/u_boot_console_sandbox.py | 7 +- 44 files changed, 1167 insertions(+), 60 deletions(-) create mode 100644 configs/sandbox_vpl_defconfig rename doc/{README.SPL => develop/spl.rst} (68%) create mode 100644 test/py/tests/test_vpl.py -- 2.36.0.464.gb9c8b46e94-goog

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Please pull u-boot-marvell/master
by Stefan Roese 03 May '22

03 May '22

Hi Tom, please pull this next batch of Marvell related patches: ---------------------------------------------------------------- - Misc turris_omnia/mox related Fixes and impovements (Pali) - Turris Omnia: Add support for configuring mSATA and WWAN slots via env variables (Pali) - net: mvgbe: Set PHY page 0 before phy_connect (Tony) - kirkwood: nsa310s: Use Marvell uclass mvgbe and PHY driver (Tony) - mvebu: turris_omnia: Fix SYS_RSTOUT_* macro names (Pali) - mvebu: clearfog_defconfig: enable setexpr command (Josef) - mvebu: x530: set MPP55 to gpio (Chris) ---------------------------------------------------------------- Here the Azure build, without any issues: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=179&view=results Thanks, Stefan The following changes since commit c70c0102af5413cadde6bf90044cb75aefef0584: Merge tag 'efi-2022-07-rc2' of https://source.denx.de/u-boot/custodians/u-boot-efi (2022-04-29 14:04:08 -0400) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-marvell.git for you to fetch changes up to 08dc62c1527ec7401cc98719cde50ca47533a7c2: ARM: mvebu: x530: set MPP55 to gpio (2022-05-02 07:47:26 +0200) ---------------------------------------------------------------- Chris Packham (1): ARM: mvebu: x530: set MPP55 to gpio Josef Schlehofer (1): arm: mvebu: clearfog_defconfig: enable setexpr command Pali Rohár (14): env: sf: Allow to use env_sf_init_addr() at any stage arm: mvebu: turris_omnia: Provide env_sf_get_env_addr() function arm: mvebu: turris_omnia: Enable ENV support in SPL arm: mvebu: turris_omnia: Define only one serdes map variable arm: mvebu: turris_omnia: Allow to configure mSATA slot via env variable arm: mvebu: turris_omnia: Extract code for disabling sata/pcie arm: mvebu: turris_omnia: Signal error when sata/pcie DT mode arm: mvebu: turris_omnia: Add support for USB3.0 mode in WWAN MiniPCIe slot arm: mvebu: turris_omnia: Fix RESET button message arm: mvebu: turris_omnia: Define CONFIG_ETHPRIME instead of ethact= ENV arm: mvebu: turris_omnia: Always enable MMC, SCSI and USB boot targets arm: mvebu: turris_omnia: Add NVMe to boot targets arm: mvebu: turris_mox: Add NVMe and SCSI to boot targets arm: mvebu: turris_omnia: Fix SYS_RSTOUT_* macro names Tony Dinh (2): net: marvell: mvgbe: Set PHY page 0 before phy_connect arm: kirkwood: nsa310s: Use Marvell uclass mvgbe and PHY driver for DM Ethernet arch/arm/dts/kirkwood-nsa310s.dts | 1 + board/CZ.NIC/turris_omnia/turris_omnia.c | 215 ++++++++++++++++++++++--------- board/alliedtelesis/x530/x530.c | 2 +- board/zyxel/nsa310s/nsa310s.c | 119 +++++------------ board/zyxel/nsa310s/nsa310s.h | 46 ------- configs/clearfog_defconfig | 1 - configs/nsa310s_defconfig | 6 +- configs/turris_omnia_defconfig | 3 + drivers/net/mvgbe.c | 4 + env/sf.c | 22 ++-- include/configs/nsa310s.h | 11 +- include/configs/turris_mox.h | 2 + include/configs/turris_omnia.h | 26 +--- 13 files changed, 221 insertions(+), 237 deletions(-) delete mode 100644 board/zyxel/nsa310s/nsa310s.h

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[PATCH v2 0/2] sf: dataflash: add support for AT45DB641E
by Luca Ellero 03 May '22

03 May '22

Since AT45DB641E uses "extended device information" for reading JEDEC ID we must first introduce support for this feature. All code is borrowed from Linux kernel source code: drivers/mtd/devices/mtd_dataflash.c commit 1da8869a428317a6d3cd8d47184cf87feb34a98b Author: Andrey Smirnov <andrew.smirnov(a)gmail.com> Changes for v2: - add reference to Linux kernel commit Luca Ellero (2): sf: dataflash: add support for "extended ID" sf: dataflash: add support for AT45DB641E drivers/mtd/spi/sf_dataflash.c | 101 ++++++++++++++++++++++----------- 1 file changed, 67 insertions(+), 34 deletions(-) -- 2.17.1

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[PATCH v1] imx: enable ahab on imx8qm-rom7720
by Oliver Graute 03 May '22

03 May '22

enable ahab on imx8qm-rom7720 Signed-off-by: Oliver Graute <oliver.graute(a)kococonnector.com> --- configs/imx8qm_rom7720_a1_4G_defconfig | 1 + include/configs/imx8qm_rom7720.h | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/configs/imx8qm_rom7720_a1_4G_defconfig b/configs/imx8qm_rom7720_a1_4G_defconfig index d9997cfa82..49deb283ff 100644 --- a/configs/imx8qm_rom7720_a1_4G_defconfig +++ b/configs/imx8qm_rom7720_a1_4G_defconfig @@ -85,4 +85,5 @@ CONFIG_SPL_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_SPL_TINY_MEMSET=y +CONFIG_AHAB_BOOT=y # CONFIG_EFI_LOADER is not set diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index 81ab5d8caa..b98e739e00 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -22,6 +22,12 @@ #define CONFIG_SYS_BOOTM_LEN SZ_64M +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + /* FUSE command */ /* Boot M4 */ @@ -54,6 +60,7 @@ /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ + AHAB_ENV \ CONFIG_MFG_ENV_SETTINGS \ M4_BOOT_ENV \ "script=boot.scr\0" \ -- 2.17.1

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[PATCH] mtd: spi-nor-ids: add Macronix flash entry
by tien.fong.chee＠intel.com 03 May '22

03 May '22

From: Tien Fong Chee <tien.fong.chee(a)intel.com> Add Macronix mx25u51245g flash entry, so this can be used on SoCFPGA devices. Signed-off-by: Tien Fong Chee <tien.fong.chee(a)intel.com> --- drivers/mtd/spi/spi-nor-ids.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 763bab04c6..94cf7a3a44 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -166,6 +166,8 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) }, { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K) }, { INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) }, + { INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) }, { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) }, -- 2.19.0

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Help porting U-Boot to samsung-espresso3g
by Mighty M 03 May '22

03 May '22

Hello! I am trying to get u boot running on the samsung-espresso3g (https://wiki.postmarketos.org/wiki/Samsung_Galaxy_Tab_2_7.0%22_(samsung-esp…) but it gets stuck at the bootsplash (ie the Samsung logo). Here is my fork https://github.com/MightyM17/u-boot/tree/espresso-dev. Any guidance on what i should do?

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