May 2022 - U-Boot

[PATCH v2 00/12] stm32: add new board support, defconfig and documentation
by Patrice Chotard 10 May '22

10 May '22

Add new stm32746g-eval board support Add defconfig for SPL and none SPL mode for STM32F7 boards. Add documentation on how to build and flash STM32 MCUs. Changes in v2: - fix documentation file stm32_MCU.rst Patrice Chotard (12): configs: stm32f746-disco: Concatenate spl and u-boot binaries configs: stm32f746-disco: Rename stm32f746-disco_defconfig to stm32f746-disco_spl_defconfig configs: stm32f746-disco: Add stm32f746-disco_defconfig configs: stm32f769-disco: Rename stm32f769-disco_defconfig to stm32f769-disco_spl_defconfig configs: stm32f769-disco: Add stm32f769-disco_defconfig configs: stm32f769-disco: Migrate SPL flags to defconfig configs: stm32f746-disco: Migrate SPL flags to defconfig board: stm32f746-disco: Fix dram_init() in none SPL config configs: stm32f746-disco: use CONFIG_DEFAULT_DEVICE_TREE as fdtfile configs: stm32746g-eval: Add stm32746g-eval_defconfig configs: stm32746g-eval: Add stm32746g-eval_spl_defconfig doc: Add documentation for STM32 MCUs arch/arm/mach-stm32/Kconfig | 20 --- board/st/stm32f429-discovery/MAINTAINERS | 1 + board/st/stm32f429-evaluation/MAINTAINERS | 1 + board/st/stm32f469-discovery/MAINTAINERS | 1 + board/st/stm32f746-disco/MAINTAINERS | 5 + board/st/stm32f746-disco/stm32f746-disco.c | 2 +- board/st/stm32h743-disco/MAINTAINERS | 1 + board/st/stm32h743-eval/MAINTAINERS | 1 + board/st/stm32h750-art-pi/MAINTAINERS | 1 + configs/stm32746g-eval_defconfig | 64 +++++++ configs/stm32746g-eval_spl_defconfig | 86 ++++++++++ configs/stm32f746-disco_defconfig | 9 +- configs/stm32f746-disco_spl_defconfig | 86 ++++++++++ configs/stm32f769-disco_defconfig | 9 +- configs/stm32f769-disco_spl_defconfig | 87 ++++++++++ doc/board/st/index.rst | 1 + doc/board/st/stm32_MCU.rst | 186 +++++++++++++++++++++ include/configs/stm32f746-disco.h | 3 +- 18 files changed, 528 insertions(+), 36 deletions(-) create mode 100644 configs/stm32746g-eval_defconfig create mode 100644 configs/stm32746g-eval_spl_defconfig create mode 100644 configs/stm32f746-disco_spl_defconfig create mode 100644 configs/stm32f769-disco_spl_defconfig create mode 100644 doc/board/st/stm32_MCU.rst -- 2.25.1

3 25

[PATCH 1/2] misc: i2c_eeprom: add support for microchip 24aa025e48
by Eugen Hristev 10 May '22

10 May '22

24aa025e48 is a variant of 24aa02e48 that has a page size of 16 bytes. Signed-off-by: Eugen Hristev <eugen.hristev(a)microchip.com> --- drivers/misc/i2c_eeprom.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c index 89a450d0f8..265c1d0591 100644 --- a/drivers/misc/i2c_eeprom.c +++ b/drivers/misc/i2c_eeprom.c @@ -176,6 +176,13 @@ static const struct i2c_eeprom_drv_data mc24aa02e48_data = { .offset_len = 1, }; +static const struct i2c_eeprom_drv_data mc24aa025e48_data = { + .size = 256, + .pagesize = 16, + .addr_offset_mask = 0, + .offset_len = 1, +}; + static const struct i2c_eeprom_drv_data atmel24c01a_data = { .size = 128, .pagesize = 8, @@ -264,6 +271,7 @@ static const struct i2c_eeprom_drv_data atmel24c512_data = { static const struct udevice_id i2c_eeprom_std_ids[] = { { .compatible = "i2c-eeprom", (ulong)&eeprom_data }, { .compatible = "microchip,24aa02e48", (ulong)&mc24aa02e48_data }, + { .compatible = "microchip,24aa025e48", (ulong)&mc24aa025e48_data }, { .compatible = "atmel,24c01", (ulong)&atmel24c01a_data }, { .compatible = "atmel,24c01a", (ulong)&atmel24c01a_data }, { .compatible = "atmel,24c02", (ulong)&atmel24c02_data }, -- 2.25.1

4 5

[PATCH] board: st: stm32mp1: Consider USB cable connected when boot device is USB
by Patrice Chotard 10 May '22

10 May '22

Always consider USB cable is connected when USB boot device is detected. Signed-off-by: Patrice Chotard <patrice.chotard(a)foss.st.com> --- board/st/stm32mp1/stm32mp1.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index fff1880e5b..62a5fc23e6 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -199,6 +199,13 @@ int g_dnl_board_usb_cable_connected(void) if (!IS_ENABLED(CONFIG_USB_GADGET_DWC2_OTG)) return -ENODEV; + /* + * In case of USB boot device is detected, consider USB cable is + * connected + */ + if ((get_bootmode() & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_USB) + return true; + /* if typec stusb160x is present, means DK1 or DK2 board */ ret = stusb160x_cable_connected(); if (ret >= 0) -- 2.17.1

3 2

[PATCH 1/3] pinctrl: pinctrl_stm32: Update pinmux_mode definition
by Patrice Chotard 10 May '22

10 May '22

pinmux_mode[] is linked to gpio_function[] defined in gpio-uclass.c So reuse the same gpio_func_t enum value Signed-off-by: Patrice Chotard <patrice.chotard(a)foss.st.com> --- drivers/pinctrl/pinctrl_stm32.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 5729799b12..5d8e156d62 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -42,13 +42,12 @@ struct stm32_gpio_bank { #ifndef CONFIG_SPL_BUILD static char pin_name[PINNAME_SIZE]; -#define PINMUX_MODE_COUNT 5 -static const char * const pinmux_mode[PINMUX_MODE_COUNT] = { - "gpio input", - "gpio output", - "analog", - "unknown", - "alt function", +static const char * const pinmux_mode[GPIOF_COUNT] = { + [GPIOF_INPUT] = "gpio input", + [GPIOF_OUTPUT] = "gpio output", + [GPIOF_UNUSED] = "analog", + [GPIOF_UNKNOWN] = "unknown", + [GPIOF_FUNC] = "alt function", }; static const char * const pinmux_bias[] = { -- 2.17.1

3 8

[PATCH] ARM: stm32: Use CONFIG_TFTP_TSIZE on STMicroelectronics boards
by Patrick Delaunay 10 May '22

10 May '22

Long TFTP transfers lead to a wall of # characters on UART, which in the end may slow down the transfer itself. Use CONFIG_TFTP_TSIZE to print progress in fewer # characters. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- configs/stm32mp15_basic_defconfig | 1 + configs/stm32mp15_defconfig | 1 + configs/stm32mp15_trusted_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 5d1b2e0fd7..1b1c255b98 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -80,6 +80,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=-1 # CONFIG_SPL_ENV_IS_NOWHERE is not set # CONFIG_SPL_ENV_IS_IN_SPI_FLASH is not set +CONFIG_TFTP_TSIZE=y CONFIG_STM32_ADC=y CONFIG_SET_DFU_ALT_INFO=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index f6e7fc81b0..02b37e14ea 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -61,6 +61,7 @@ CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=-1 +CONFIG_TFTP_TSIZE=y CONFIG_STM32_ADC=y CONFIG_CLK_SCMI=y CONFIG_SET_DFU_ALT_INFO=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 855a394893..df31c0fbb1 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -62,6 +62,7 @@ CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=-1 +CONFIG_TFTP_TSIZE=y CONFIG_STM32_ADC=y CONFIG_CLK_SCMI=y CONFIG_SET_DFU_ALT_INFO=y -- 2.25.1

2 2

[PATCH] ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSI
by Marek Vasut 10 May '22

10 May '22

The Buck3 on DHCOR is used to supply IO voltage. It can output either 3V3 in the default DHCOR configuration, or 2V9 in case of AV96 DHCOR variant which has extra Empirion DCDC converter in front of the 1V8 IO supply, or outright 1V8 in case of 1V8 IO DHCOR without the Empirion DCDC converter. The 2V9 mode in case of AV96 DHCOR variant is used to reduce unnecessarily high input voltage to the Empirion DCDC converter, so move it into matching DTSI to stop confusing users. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi | 5 +++++ arch/arm/dts/stm32mp15xx-dhcor-som.dtsi | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi index 75172314d7a..9937b28548c 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi @@ -18,6 +18,11 @@ }; }; +&vdd { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; +}; + &pwr_regulators { vdd-supply = <&vdd_io>; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi index 44ecc470858..98033b51479 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi @@ -77,8 +77,8 @@ vdd: buck3 { regulator-name = "vdd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-always-on; regulator-initial-mode = <0>; regulator-over-current-protection; -- 2.35.1

3 3

[PATCH 1/2] ARM: stm32: Use default CONFIG_TFTP_BLOCKSIZE on DHSOM
by Marek Vasut 10 May '22

10 May '22

The DHCOM does ship with KS8851 with 1.5 kiB packet buffer. The DHSOM may be extended with other MAC options connected to FMC2 bus, like the DM9000, wih similar limitations. Use default CONFIG_TFTP_BLOCKSIZE of 1468 Bytes instead of 1536 Bytes, which always avoids overflowing the packet buffers of such limited MACs, which leads to e.g. TFTP timeouts. This also avoids receiving a short packet fragment at the end of each TFTP block, which led to reduced performance. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Ramon Fried <rfried.dev(a)gmail.com> --- configs/stm32mp15_dhcom_basic_defconfig | 1 - configs/stm32mp15_dhcor_basic_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index ec955eae200..0ff015cae49 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -80,7 +80,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_ENV_IS_NOWHERE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y -CONFIG_TFTP_BLOCKSIZE=1536 CONFIG_STM32_ADC=y CONFIG_SPL_BLOCK_CACHE=y CONFIG_DFU_MMC=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index 387e068155e..83614b9fc8e 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -77,7 +77,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_ENV_IS_NOWHERE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_IP_DEFRAG=y -CONFIG_TFTP_BLOCKSIZE=1536 CONFIG_STM32_ADC=y CONFIG_SPL_BLOCK_CACHE=y CONFIG_DFU_MMC=y -- 2.35.1

4 7

[PATCH v2] stm32mp: psci: Retain MCUDIVR, PLL3CR, PLL4CR, MSSCKSELR across suspend
by Marek Vasut 10 May '22

10 May '22

The SoC seems to lose the values of MCUDIVR, PLL3CR, PLL4CR, RCC_MSSCKSELR during suspend/resume cycle, cache them and reinstate their values on resume. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> --- V2: Cache MCUDIVR as well --- arch/arm/mach-stm32mp/psci.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c index 86c160987a9..1e69673e88b 100644 --- a/arch/arm/mach-stm32mp/psci.c +++ b/arch/arm/mach-stm32mp/psci.c @@ -26,6 +26,7 @@ #define PWR_MPUCR_CSSF BIT(9) /* RCC */ +#define RCC_MSSCKSELR 0x48 #define RCC_DDRITFCR 0xd8 #define RCC_DDRITFCR_DDRC1EN BIT(0) @@ -49,6 +50,10 @@ #define RCC_MP_CIFR 0x418 #define RCC_MP_CIFR_WKUPF BIT(20) +#define RCC_MCUDIVR 0x830 +#define RCC_PLL3CR 0x880 +#define RCC_PLL4CR 0x894 + /* SYSCFG */ #define SYSCFG_CMPCR 0x20 #define SYSCFG_CMPCR_SW_CTRL BIT(2) @@ -690,6 +695,7 @@ static void __secure ddr_sw_self_refresh_exit(void) void __secure psci_system_suspend(u32 __always_unused function_id, u32 ep, u32 context_id) { + u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr; u32 saved_pwrctl, reg; /* Disable IO compensation */ @@ -708,6 +714,11 @@ void __secure psci_system_suspend(u32 __always_unused function_id, setbits_le32(STM32_PWR_BASE + PWR_MPUCR, PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_PDDS); + saved_mcudivr = readl(STM32_RCC_BASE + RCC_MCUDIVR); + saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR); + saved_pll4cr = readl(STM32_RCC_BASE + RCC_PLL4CR); + saved_mssckselr = readl(STM32_RCC_BASE + RCC_MSSCKSELR); + psci_v7_flush_dcache_all(); ddr_sr_mode_ssr(&saved_pwrctl); ddr_sw_self_refresh_in(); @@ -724,6 +735,11 @@ void __secure psci_system_suspend(u32 __always_unused function_id, ddr_sw_self_refresh_exit(); ddr_sr_mode_restore(saved_pwrctl); + writel(saved_mcudivr, STM32_RCC_BASE + RCC_MCUDIVR); + writel(saved_pll3cr, STM32_RCC_BASE + RCC_PLL3CR); + writel(saved_pll4cr, STM32_RCC_BASE + RCC_PLL4CR); + writel(saved_mssckselr, STM32_RCC_BASE + RCC_MSSCKSELR); + writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR); clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); } -- 2.35.1

3 2

[PATCH v2] ram: stm32mp1: Conditionally enable ASR
by Marek Vasut 10 May '22

10 May '22

Enable DRAM ASR, auto self-refresh, conditionally, based on DT PWRCTL register bits. While ASR does save considerable amount of power at runtime automatically, it also causes LTDC underruns on large panels. Let user select whether or not ASR is required or not, generally ASR should be enabled on portable and battery operated devices. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> --- V2: Infer ASR settings from DT PWRCTL --- drivers/ram/stm32mp1/stm32mp1_ddr.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c index 528a171b454..ab913a68761 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr.c +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c @@ -653,10 +653,14 @@ static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, wait_sw_done_ack(ctl); } -static void stm32mp1_asr_enable(struct ddr_info *priv) +static void stm32mp1_asr_enable(struct ddr_info *priv, const u32 pwrctl) { struct stm32mp1_ddrctl *ctl = priv->ctl; + /* SSR is the best we can do. */ + if (!(pwrctl & DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE)) + return; + clrsetbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCKMOD_MASK, RCC_DDRITFCR_DDRCKMOD_ASR); @@ -666,8 +670,12 @@ static void stm32mp1_asr_enable(struct ddr_info *priv) writel(DDRCTRL_PWRTMG_POWERDOWN_TO_X32(0x10) | DDRCTRL_PWRTMG_SELFREF_TO_X32(0x01), &ctl->pwrtmg); + + /* HSR we can do. */ setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE); - setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN); + + if (pwrctl & DDRCTRL_PWRCTL_SELFREF_EN) /* ASR we can do. */ + setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN); setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); wait_sw_done_ack(ctl); @@ -845,7 +853,7 @@ start: config->c_reg.pwrctl); /* Enable auto-self-refresh, which saves a bit of power at runtime. */ - stm32mp1_asr_enable(priv); + stm32mp1_asr_enable(priv, config->c_reg.pwrctl); /* enable uMCTL2 AXI port 0 and 1 */ setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN); -- 2.35.1

3 2

[PATCH] arm: dts: stm32mp15: alignment with v5.18
by Patrick Delaunay 10 May '22

10 May '22

Device tree alignment with Linux kernel v5.18-rc2: - ARM: dts: stm32: Add support for the emtrion emSBC-Argon (only the pincontrol part) - ARM: dts: stm32: Drop duplicate status okay from DHCOM gpioc node - ARM: dts: stm32: add st,stm32-sdmmc2 compatible on stm32mp151 - ARM: dts: stm32: fix AV96 board SAI2 pin muxing on stm32mp15 - ARM: dts: stm32: use exti 19 as main interrupt to support RTC wakeup on stm32mp157 - ARM: dts: stm32: add DMA configuration to UART nodes on stm32mp151 - ARM: dts: stm32: keep uart4 behavior on * - ARM: dts: stm32: Correct masks for GIC PPI interrupts on stm32mp15 Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/dts/stm32mp15-pinctrl.dtsi | 92 +++++++++++++++++++ arch/arm/dts/stm32mp15-u-boot.dtsi | 12 --- arch/arm/dts/stm32mp151.dtsi | 37 ++++++-- arch/arm/dts/stm32mp153.dtsi | 7 ++ .../stm32mp157a-icore-stm32mp1-ctouch2.dts | 2 + .../stm32mp157a-icore-stm32mp1-edimm2.2.dts | 2 + ...157a-microgea-stm32mp1-microdev2.0-of7.dts | 4 + ...32mp157a-microgea-stm32mp1-microdev2.0.dts | 4 + arch/arm/dts/stm32mp157c-ed1.dts | 2 + arch/arm/dts/stm32mp157c-odyssey.dts | 2 + arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi | 4 + arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi | 4 + arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi | 4 + arch/arm/dts/stm32mp15xx-dhcom-som.dtsi | 3 +- arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi | 6 ++ arch/arm/dts/stm32mp15xx-dkx.dtsi | 4 + 16 files changed, 168 insertions(+), 21 deletions(-) diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi index 6161f5906e..f0d66d8c6e 100644 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi @@ -338,6 +338,47 @@ }; }; + ethernet0_rmii_pins_b: rmii-1 { + pins1 { + pinmux = <STM32_PINMUX('B', 5, AF0)>, /* ETH1_CLK */ + <STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */ + <STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */ + <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>; /* ETH1_RXD1 */ + bias-disable; + }; + pins4 { + pinmux = <STM32_PINMUX('B', 11, AF11)>; /* ETH1_TX_EN */ + }; + }; + + ethernet0_rmii_sleep_pins_b: rmii-sleep-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ + <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_CRS_DV */ + <STM32_PINMUX('B', 5, ANALOG)>, /* ETH1_CLK */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_EN */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */ + <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */ + }; + }; + fmc_pins_a: fmc-0 { pins1 { pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ @@ -927,6 +968,21 @@ }; }; + pwm1_pins_b: pwm1-1 { + pins { + pinmux = <STM32_PINMUX('E', 9, AF1)>; /* TIM1_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm1_sleep_pins_b: pwm1-sleep-1 { + pins { + pinmux = <STM32_PINMUX('E', 9, ANALOG)>; /* TIM1_CH1 */ + }; + }; + pwm2_pins_a: pwm2-0 { pins { pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */ @@ -2042,6 +2098,42 @@ }; }; + usart3_pins_d: usart3-3 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 9, AF7)>, /* USART3_RX */ + <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + + usart3_idle_pins_d: usart3-idle-3 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ + <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('D', 9, AF7)>; /* USART3_RX */ + bias-disable; + }; + }; + + usart3_sleep_pins_d: usart3-sleep-3 { + pins { + pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ + <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ + <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */ + <STM32_PINMUX('D', 9, ANALOG)>; /* USART3_RX */ + }; + }; + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index e23d6c7d7e..d9d04743ac 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -188,18 +188,6 @@ #size-cells = <0>; }; -&sdmmc1 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; -}; - -&sdmmc2 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; -}; - -&sdmmc3 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; -}; - &usart1 { resets = <&rcc USART1_R>; }; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index 5a2be00758..e74a5faf4a 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -63,10 +63,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; interrupt-parent = <&intc>; }; @@ -473,6 +473,9 @@ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART2_K>; wakeup-source; + dmas = <&dmamux1 43 0x400 0x15>, + <&dmamux1 44 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -482,6 +485,9 @@ interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART3_K>; wakeup-source; + dmas = <&dmamux1 45 0x400 0x15>, + <&dmamux1 46 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -491,6 +497,9 @@ interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART4_K>; wakeup-source; + dmas = <&dmamux1 63 0x400 0x15>, + <&dmamux1 64 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -500,6 +509,9 @@ interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART5_K>; wakeup-source; + dmas = <&dmamux1 65 0x400 0x15>, + <&dmamux1 66 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -606,6 +618,9 @@ interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART7_K>; wakeup-source; + dmas = <&dmamux1 79 0x400 0x15>, + <&dmamux1 80 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -615,6 +630,9 @@ interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc UART8_K>; wakeup-source; + dmas = <&dmamux1 81 0x400 0x15>, + <&dmamux1 82 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -696,6 +714,9 @@ interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART6_K>; wakeup-source; + dmas = <&dmamux1 71 0x400 0x15>, + <&dmamux1 72 0x400 0x11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1077,7 +1098,7 @@ }; sdmmc3: mmc@48004000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; reg = <0x48004000 0x400>; interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; @@ -1411,7 +1432,7 @@ }; sdmmc1: mmc@58005000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; reg = <0x58005000 0x1000>; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; @@ -1426,7 +1447,7 @@ }; sdmmc2: mmc@58007000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00253180>; reg = <0x58007000 0x1000>; interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; @@ -1590,7 +1611,7 @@ reg = <0x5c004000 0x400>; clocks = <&rcc RTCAPB>, <&rcc RTC>; clock-names = "pclk", "rtc_ck"; - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; diff --git a/arch/arm/dts/stm32mp153.dtsi b/arch/arm/dts/stm32mp153.dtsi index 1c1889b194..486084e0b8 100644 --- a/arch/arm/dts/stm32mp153.dtsi +++ b/arch/arm/dts/stm32mp153.dtsi @@ -22,6 +22,13 @@ interrupt-affinity = <&cpu0>, <&cpu1>; }; + timer { + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + soc { m_can1: can@4400e000 { compatible = "bosch,m_can"; diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts index d3058a036c..1f75f1d451 100644 --- a/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts +++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-ctouch2.dts @@ -43,5 +43,7 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts index ec9f1d1cd5..3a1295cfa9 100644 --- a/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts +++ b/arch/arm/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -43,5 +43,7 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts index 5670b23812..fae656edd8 100644 --- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts +++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts @@ -143,6 +143,8 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -150,5 +152,7 @@ &uart8 { pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts index 7a75868164..b9d0d3d6ad 100644 --- a/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts +++ b/arch/arm/dts/stm32mp157a-microgea-stm32mp1-microdev2.0.dts @@ -44,6 +44,8 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -51,5 +53,7 @@ &uart8 { pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index f62b46b8dd..fe5c8f25ce 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -392,6 +392,8 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts index 0e725498dd..17bcf56f74 100644 --- a/arch/arm/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/dts/stm32mp157c-odyssey.dts @@ -132,6 +132,8 @@ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi index 4b10b013ff..35b1034aa3 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-drc02.dtsi @@ -131,6 +131,8 @@ &usart3 { pinctrl-names = "default"; pinctrl-0 = <&usart3_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -144,6 +146,8 @@ pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a>; rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi index fbf3826933..5f586f0240 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -287,6 +287,8 @@ &usart3 { pinctrl-names = "default"; pinctrl-0 = <&usart3_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -294,6 +296,8 @@ pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi index ba816ef8b9..abc595350e 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-picoitx.dtsi @@ -105,12 +105,16 @@ &usart3 { pinctrl-names = "default"; pinctrl-0 = <&usart3_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; &uart8 { pinctrl-names = "default"; pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi index 8c41f819f7..83e2c87713 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi @@ -196,7 +196,6 @@ "", "", "DHCOM-E", "", "", "", "", "", "", "", "", ""; - status = "okay"; }; &gpiod { @@ -521,5 +520,7 @@ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi index 6885948f30..61e17f44ce 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -376,6 +376,8 @@ label = "LS-UART1"; pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -385,6 +387,8 @@ pinctrl-names = "default"; pinctrl-0 = <&uart7_pins_a>; uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -394,6 +398,8 @@ pinctrl-0 = <&usart2_pins_a>; pinctrl-1 = <&usart2_sleep_pins_a>; st,hw-flow-ctrl; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; bluetooth { diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index f8130bf445..3d36cac9ed 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -658,6 +658,8 @@ pinctrl-0 = <&uart4_pins_a>; pinctrl-1 = <&uart4_sleep_pins_a>; pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; status = "okay"; }; @@ -666,6 +668,8 @@ pinctrl-0 = <&uart7_pins_c>; pinctrl-1 = <&uart7_sleep_pins_c>; pinctrl-2 = <&uart7_idle_pins_c>; + /delete-property/dmas; + /delete-property/dma-names; status = "disabled"; }; -- 2.25.1

2 2