May 2022 - U-Boot

[PATCH 1/4] ARM: imx: imx8m: Introduce and use UART_BASE_ADDR(n)
by Marek Vasut 20 May '22

20 May '22

Introduce helper macro UART_BASE_ADDR(n), which returns Nth UART base address. Convert all board configurations to this new macro. This is the first step toward switching CONFIG_MXC_UART_BASE to Kconfig. This is a clean up, no functional change. The new macro contains compile-time test to verify N is in suitable range. The test works such that it multiplies constant N by constant double-negation of size of a non-empty structure, i.e. it multiplies constant N by constant 1 in each successful compilation case. The non-empty structure may contain C11 _Static_assert(), make use of this and place the kernel variant of static assert in there, so that it performs the compile-time check for N in the correct range. Note that it is not possible to directly use static_assert in compound statements, hence this convoluted construct. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)denx.de> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/include/asm/arch-imx8m/imx-regs.h | 10 ++++++++++ include/configs/imx8mm-cl-iot-gate.h | 2 +- include/configs/imx8mm_beacon.h | 2 +- include/configs/imx8mm_evk.h | 2 +- include/configs/imx8mm_icore_mx8mm.h | 2 +- include/configs/imx8mm_venice.h | 2 +- include/configs/imx8mn_beacon.h | 2 +- include/configs/imx8mn_evk.h | 2 +- include/configs/imx8mn_var_som.h | 2 +- include/configs/imx8mn_venice.h | 2 +- include/configs/imx8mp_evk.h | 2 +- include/configs/imx8mp_rsb3720.h | 2 +- include/configs/imx8mq_cm.h | 2 +- include/configs/imx8mq_evk.h | 2 +- include/configs/imx8mq_phanbell.h | 2 +- include/configs/kontron-sl-mx8mm.h | 2 +- include/configs/kontron_pitx_imx8m.h | 2 +- include/configs/phycore_imx8mm.h | 2 +- include/configs/phycore_imx8mp.h | 2 +- include/configs/pico-imx8mq.h | 2 +- include/configs/verdin-imx8mm.h | 2 +- include/configs/verdin-imx8mp.h | 2 +- 22 files changed, 31 insertions(+), 21 deletions(-) diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index b2a8ad77ae1..1da75528d46 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -48,6 +48,16 @@ #ifdef CONFIG_IMX8MM #define USDHC3_BASE_ADDR 0x30B60000 #endif +#define UART_BASE_ADDR(n) ( \ + !!sizeof(struct { \ + static_assert((n) >= 1 && (n) <= 4); \ + int pad; \ + }) * ( \ + (n) == 1 ? UART1_BASE_ADDR : \ + (n) == 2 ? UART2_BASE_ADDR : \ + (n) == 3 ? UART3_BASE_ADDR : \ + UART4_BASE_ADDR) \ + ) #define TZASC_BASE_ADDR 0x32F80000 diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index c20c32b6951..60746588b73 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -145,7 +145,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3) /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 7c17f14964f..573ddaf2952 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -91,7 +91,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index 42b78485cfc..bd10406d79d 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -68,7 +68,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index f521add5b04..b9b24a8c51d 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -66,7 +66,7 @@ #define CONFIG_SYS_BOOTM_LEN SZ_256M /* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 1b26e0280e1..f3dad256100 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -102,7 +102,7 @@ #define CONFIG_SYS_BOOTM_LEN SZ_256M /* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index 41ce3c1c8ce..79c6b1076ff 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -107,7 +107,7 @@ #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ #endif -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 034132225c6..805ae2a7518 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -75,7 +75,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h index 318289b76bc..00358892b28 100644 --- a/include/configs/imx8mn_var_som.h +++ b/include/configs/imx8mn_var_som.h @@ -64,7 +64,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */ -#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(4) /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index a4826779022..dcb5baf6eb4 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -98,7 +98,7 @@ #define CONFIG_SYS_BOOTM_LEN SZ_256M /* UART */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index cc8d65cb54e..908ed76f39e 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -80,7 +80,7 @@ #define PHYS_SDRAM_2 0x100000000 #define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */ -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(2) /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index c5dd545471e..c0f2824fd4c 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -169,7 +169,7 @@ #define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ #endif -#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3) /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 2048 diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 989486aa6dc..6eecfc813a4 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -71,7 +71,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */ -#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index f7929e5867e..8596d999257 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -78,7 +78,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ -#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index f6410114b76..9cf779b0752 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -106,7 +106,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ -#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index 1b429f7dbe2..8b2a10dda1f 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -28,7 +28,7 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* Board and environment settings */ -#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3) #define CONFIG_HOSTNAME "kontron-mx8mm" #ifdef CONFIG_USB_EHCI_HCD diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index e8e92920dcb..182ee590318 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -84,7 +84,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ -#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3) #define CONFIG_SYS_FSL_USDHC_NUM 2 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index 71f0c42ec0c..46fadd56106 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -84,7 +84,7 @@ #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ /* UART */ -#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3) /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index 0c963b62b3b..eb92c423392 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -84,7 +84,7 @@ #define PHYS_SDRAM_SIZE 0x80000000 /* UART */ -#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 95845276e7b..567b06c4f5d 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -85,7 +85,7 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2 GiB DDR */ -#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 1024 diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index da3dc95f9ee..130a1ed54d1 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -84,7 +84,7 @@ #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */ /* UART */ -#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1) /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index 7b7407752c1..33cfd3d2d73 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -101,7 +101,7 @@ #define PHYS_SDRAM_2_SIZE (SZ_4G + SZ_1G) /* UART */ -#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR +#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3) /* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE SZ_2K -- 2.35.1

5 16

[PATCH V2 00/16] imx: imx8m: clean up wdog code
by Peng Fan (OSS) 20 May '22

20 May '22

From: Peng Fan <peng.fan(a)nxp.com> V2: Drop patch 6 in V1 Update commit log Add R-b/T-b tag Enable pinctrl wdog to clean up board level code imx_watchdog.c already has function of set_wdog_reset, so after watchdog driver enabled, no need that. Note: I only have NXP EVK board, so please help test if possible. Based on: https://patchwork.ozlabs.org/project/uboot/cover/20220505074341.24086-1-pen… Peng Fan (16): imx: imx8mn_evk: enable pinctrl_wdog in SPL imx: imx8mm_evk: enable pinctrl_wdog in SPL imx: imx8mp_evk: enable pinctrl_wdog in SPL imx: imx8mm_beacon: enable pinctrl_wdog in SPL imx: imx8mm-cl-iot-gate: enable pinctrl_wdog in SPL imx: engicam-imx8mm: drop unused macro imx: imx8mm-mx8menlo: drop unneeded watchdog settings imx: imx8mm/n/p-venice: enable pinctrl_wdog in SPL imx: imx8mn-beacon: enable pinctrl_wdog in SPL imx: imx8mn_smm_s2: clean up board watchdog code imx: imx8mn_var_som: clean up board watchdog code imx: imx8mp_rsb7320a1: enable wdog driver model in SPL imx: imx8mn-kontron-n801x: enable pinctrl_wdog in SPL imx: phycore_imx8mm/p: clean up board watchdog code imx: verdin-imx8mm/p: cleanup board watchdog code imx: toradex/verdin-imx8mm/p: cleanup board watchdog code arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mm-evk-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mm-kontron-n801x-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mm-venice-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mn-beacon-kit-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mn-venice-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mp-evk-u-boot.dtsi | 4 +++ arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi | 8 +++++ arch/arm/dts/imx8mp-venice-u-boot.dtsi | 4 +++ .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 12 -------- board/beacon/imx8mm/spl.c | 19 ------------ board/beacon/imx8mn/spl.c | 10 ------- board/bsh/imx8mn_smm_s2/spl.c | 11 ------- board/compulab/imx8mm-cl-iot-gate/spl.c | 19 ------------ board/engicam/imx8mm/spl.c | 2 -- board/freescale/imx8mm_evk/spl.c | 19 ------------ board/freescale/imx8mn_evk/spl.c | 19 ------------ board/freescale/imx8mp_evk/imx8mp_evk.c | 17 ----------- board/freescale/imx8mp_evk/spl.c | 2 -- board/gateworks/venice/spl.c | 30 ------------------- board/kontron/sl-mx8mm/spl.c | 18 ----------- board/menlo/mx8menlo/mx8menlo.c | 12 -------- board/phytec/phycore_imx8mm/spl.c | 19 ------------ board/phytec/phycore_imx8mp/spl.c | 19 ------------ board/toradex/verdin-imx8mm/spl.c | 11 ------- board/toradex/verdin-imx8mp/verdin-imx8mp.c | 11 ------- board/variscite/imx8mn_var_som/spl.c | 11 ------- configs/imx8mp_evk_defconfig | 1 - 30 files changed, 48 insertions(+), 262 deletions(-) -- 2.36.0

4 25

[PATCH v1] ARM: imx8mm: verdin-imx8mm: fix board hang in spl
by Marcel Ziswiler 20 May '22

20 May '22

From: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> Move the preloader_console_init() call after spl_early_init() to avoid board hang in SPL. While at it remove explicit in-code console/debug UART pinmuxing (uart1 and its pinmuxing are already marked as u-boot,dm-spl via device tree). Fixes: 4551e1898769 ("configs: verdin-imx8mm: verdin-imx8mp: enable dm serial") Signed-off-by: Marcel Ziswiler <marcel.ziswiler(a)toradex.com> --- I only very recently this weekend learned that verdin-imx8mm has such hang early in SPL issue due to it missing to move the preloader_console_init() call similar as to what Peng did in [1]. Unfortunately, this likely breaks Peng's [V2,00/14] imx8m: convert to DM_SERIAL series of late [2] and would need applying before ASAP. Sorry about that. [1] https://patchwork.ozlabs.org/project/uboot/patch/20220415043538.27868-3-pen… [2] https://patchwork.ozlabs.org/project/uboot/cover/20220505074341.24086-1-pen… board/toradex/verdin-imx8mm/spl.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c index 1f3f38351ef..f0361f93ea9 100644 --- a/board/toradex/verdin-imx8mm/spl.c +++ b/board/toradex/verdin-imx8mm/spl.c @@ -74,15 +74,8 @@ int board_fit_config_name_match(const char *name) } #endif -#define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) -/* Verdin UART_3, Console/Debug UART */ -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_SAI2_RXFS_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_SAI2_RXC_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; @@ -96,8 +89,6 @@ __weak void board_early_init(void) imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); set_wdog_reset(wdog); - - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); } int power_init_board(void) @@ -143,8 +134,6 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); @@ -162,6 +151,8 @@ void board_init_f(ulong dummy) hang(); } + preloader_console_init(); + enable_tzc380(); power_init_board(); -- 2.34.1

4 3

[PATCH] board: gateworks: venice: enable SPL_DM_SERIAL
by Tim Harvey 20 May '22

20 May '22

The uart2 and its pinmux are already marked with u-boot,dm-spl but we need to move the call to preloader_console_init() after spl_early_init() to avoid a board hang as dm can't be used until after spl_early_init() due to the uart driver not enabling the uart clock. Remove the manual config of the UART pinmux now that it is no longer needed. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- board/gateworks/venice/spl.c | 23 ++--------------------- configs/imx8mm_venice_defconfig | 1 - configs/imx8mn_venice_defconfig | 1 - configs/imx8mp_venice_defconfig | 1 - 4 files changed, 2 insertions(+), 24 deletions(-) diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index 223f22d3463c..6e6ce015f28a 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -87,37 +87,20 @@ static void spl_dram_init(int size) ddr_init(dram_timing); } -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) #ifdef CONFIG_IMX8MM -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static iomux_v3_cfg_t const wdog_pads[] = { IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; #elif CONFIG_IMX8MN -static const iomux_v3_cfg_t uart_pads[] = { - IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static const iomux_v3_cfg_t wdog_pads[] = { IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; #elif CONFIG_IMX8MP -static const iomux_v3_cfg_t uart_pads[] = { - MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - static const iomux_v3_cfg_t wdog_pads[] = { MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; - #endif int board_early_init_f(void) @@ -128,8 +111,6 @@ int board_early_init_f(void) set_wdog_reset(wdog); - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); - return 0; } @@ -276,8 +257,6 @@ void board_init_f(ulong dummy) timer_init(); - preloader_console_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); @@ -287,6 +266,8 @@ void board_init_f(ulong dummy) hang(); } + preloader_console_init(); + enable_tzc380(); /* need to hold PCIe switch in reset otherwise it can lock i2c bus EEPROM is on */ diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 76c5aaa413a3..e61464078fc4 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -114,7 +114,6 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index 867871373e2d..7b8be003369d 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -113,7 +113,6 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index e654762b8cb9..01d9f8b6698c 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -113,7 +113,6 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y -# CONFIG_SPL_DM_SERIAL is not set CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y -- 2.17.1

2 1

[PATCH] configs: imx8mp_venice: add FEC_QUIRK_ENET_MAC
by Tim Harvey 20 May '22

20 May '22

The IMX8MP SoC FEC needs to have the FEC_QUIRK_ENET_MAC defined. Fixes: commit 2395625209cc ("board: gateworks: venice: add imx8mp-venice-gw740x support") Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- include/configs/imx8mp_venice.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index aa0396db8b83..4120e4cc6bad 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -106,4 +106,8 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) + +/* FEC */ +#define FEC_QUIRK_ENET_MAC + #endif -- 2.17.1

2 2

[PATCH V4 0/5] MXS nand fixes in SPL
by Michael Trimarchi 20 May '22

20 May '22

Those patches come after some testing of failing in factory on some unit. We found out that the bootrom imx loader was not able to handling badblock. This can be a limit of the implementation right now in imx8mn. Anyway not all the imx platform has the support of this loader. I found some problems on the implementation so I have fixed it up according the experience of Sitara (coming from Dario). I tested only using a Fit Image as a flash container. This version add in the series the fix of cmd_nandbcb and the fix of spl_nand load. I can imagine that a lot of boards and users are affected. I have started to backport this changes in some older uboot and adapt it. Move BSH board using the spl loading instead the romapi Michael Trimarchi (5): nand: raw: mxs_nand: Fix specific hook registration mtd: nand: mxs_nand_spl: Fix bad block skipping arm: mach-imx: cmd_nandbcb fix bad block handling spl: spl_nand: Fix bad block handling in fitImage board: bsh: Switch to nand spl load instead of romapi arch/arm/mach-imx/cmd_nandbcb.c | 21 +++---- board/bsh/imx8mn_smm_s2/spl.c | 3 + common/spl/spl_nand.c | 5 +- drivers/mtd/nand/raw/mxs_nand.c | 32 +++++----- drivers/mtd/nand/raw/mxs_nand_spl.c | 90 ++++++++++++++++------------- 5 files changed, 76 insertions(+), 75 deletions(-) -- 2.25.1

5 12

[PATCH v2] mtd: rawnand: mxs_nand: Fix use_minimum_ecc for spl driver
by Ye Li 20 May '22

20 May '22

Because mxs_nand_spl driver does not support DM, to use the minimum ECC layout, it needs to handle the CONFIG_NAND_MXS_USE_MINIMUM_ECC. Signed-off-by: Ye Li <ye.li(a)nxp.com> Reviewed-by: Han Xu <han.xu(a)nxp.com> --- Changes in v2: - Use IS_ENABLED to replace #ifdef drivers/mtd/nand/raw/mxs_nand.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index ee5d7fd..0c4e559 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -1380,6 +1380,9 @@ int mxs_nand_init_spl(struct nand_chip *nand) else nand_info->max_ecc_strength_supported = 40; + if (IS_ENABLED(CONFIG_NAND_MXS_USE_MINIMUM_ECC)) + nand_info->use_minimum_ecc = true; + err = mxs_nand_alloc_buffers(nand_info); if (err) return err; -- 2.7.4

2 1

[PATCH] ARM: dts: imx: Use 100 kHz I2C2 on Data Modul i.MX8M Mini eDM SBC
by Marek Vasut 20 May '22

20 May '22

The I2C2 has SMBus device SMSC USB2514Bi connected to it, the device is capable of up to 100 kHz operation. Reduce the bus frequency to 100 kHz to guarantee this I2C device can work correctly. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)denx.de> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/dts/imx8mm-data-modul-edm-sbc.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts b/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts index 154116d01c9..5b022040902 100644 --- a/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts +++ b/arch/arm/dts/imx8mm-data-modul-edm-sbc.dts @@ -392,7 +392,7 @@ &i2c2 { /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */ - clock-frequency = <320000>; + clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; -- 2.35.1

2 1

[PATCH] board: gateworks: gw_ventana: remove obsolete file
by Tim Harvey 20 May '22

20 May '22

commit 61cf22505339 ("board: gateworks: gw_ventana: use comomn GSC driver") moved to the common GSC driver and moved remaining board-specific functions to eeprom.c. The functions in gsc.c are no longer used and it was removed from the Makefile but the file itself was not removed. Remove it now. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- board/gateworks/gw_ventana/gsc.c | 471 ------------------------------- 1 file changed, 471 deletions(-) delete mode 100644 board/gateworks/gw_ventana/gsc.c diff --git a/board/gateworks/gw_ventana/gsc.c b/board/gateworks/gw_ventana/gsc.c deleted file mode 100644 index 46448a54db90..000000000000 --- a/board/gateworks/gw_ventana/gsc.c +++ /dev/null @@ -1,471 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2013 Gateworks Corporation - * - * Author: Tim Harvey <tharvey(a)gateworks.com> - */ - -#include <common.h> -#include <command.h> -#include <log.h> -#include <linux/delay.h> -#include <linux/errno.h> -#include <common.h> -#include <i2c.h> -#include <linux/ctype.h> - -#include <asm/arch/sys_proto.h> -#include <asm/global_data.h> -#include <dm/device.h> -#include <dm/uclass.h> - -#include "ventana_eeprom.h" -#include "gsc.h" - -DECLARE_GLOBAL_DATA_PTR; - -#if CONFIG_IS_ENABLED(DM_I2C) -struct udevice *i2c_get_dev(int busno, int slave) -{ - struct udevice *dev, *bus; - int ret; - - ret = uclass_get_device_by_seq(UCLASS_I2C, busno, &bus); - if (ret) - return NULL; - ret = dm_i2c_probe(bus, slave, 0, &dev); - if (ret) - return NULL; - - return dev; -} -#endif - -/* - * The Gateworks System Controller will fail to ACK a master transaction if - * it is busy, which can occur during its 1HZ timer tick while reading ADC's. - * When this does occur, it will never be busy long enough to fail more than - * 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with - * 3 retries. - */ -int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) -{ - int retry = 3; - int n = 0; - int ret; -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - - dev = i2c_get_dev(CONFIG_I2C_GSC, chip); - if (!dev) - return -ENODEV; - ret = i2c_set_chip_offset_len(dev, alen); - if (ret) { - puts("EEPROM: Failed to set alen\n"); - return ret; - } -#else - i2c_set_bus_num(CONFIG_I2C_GSC); -#endif - - while (n++ < retry) { -#if CONFIG_IS_ENABLED(DM_I2C) - ret = dm_i2c_read(dev, addr, buf, len); -#else - ret = i2c_read(chip, addr, alen, buf, len); -#endif - if (!ret) - break; - debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, - n, ret); - if (ret != -EREMOTEIO) - break; - mdelay(10); - } - return ret; -} - -int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) -{ - int retry = 3; - int n = 0; - int ret; -#if CONFIG_IS_ENABLED(DM_I2C) - struct udevice *dev; - - dev = i2c_get_dev(CONFIG_I2C_GSC, chip); - if (!dev) - return -ENODEV; - ret = i2c_set_chip_offset_len(dev, alen); - if (ret) { - puts("EEPROM: Failed to set alen\n"); - return ret; - } -#endif - - while (n++ < retry) { -#if CONFIG_IS_ENABLED(DM_I2C) - ret = dm_i2c_write(dev, addr, buf, len); -#else - ret = i2c_write(chip, addr, alen, buf, len); -#endif - if (!ret) - break; - debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr, - n, ret); - if (ret != -EREMOTEIO) - break; - mdelay(10); - } - mdelay(100); - return ret; -} - -int gsc_get_board_temp(void) -{ - const void *fdt = gd->fdt_blob; - int node, reg, mode, val; - const char *label; - u8 buf[2]; - int ret; - - node = fdt_node_offset_by_compatible(fdt, -1, "gw,gsc-adc"); - if (node <= 0) - return node; - - /* iterate over hwmon nodes */ - node = fdt_first_subnode(fdt, node); - while (node > 0) { - reg = fdtdec_get_int(fdt, node, "reg", -1); - mode = fdtdec_get_int(fdt, node, "gw,mode", -1); - label = fdt_stringlist_get(fdt, node, "label", 0, NULL); - - if ((reg == -1) || (mode == -1) || !label) { - printf("invalid dt:%s\n", fdt_get_name(fdt, node, NULL)); - continue; - } - - if ((mode != 0) || strcmp(label, "temp")) - continue; - - memset(buf, 0, sizeof(buf)); - ret = gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, sizeof(buf)); - val = buf[0] | buf[1] << 8; - if (val >= 0) { - if (val > 0x8000) - val -= 0xffff; - return val; - } - node = fdt_next_subnode(fdt, node); - } - - return 0; -} - -/* display hardware monitor ADC channels */ -int gsc_hwmon(void) -{ - const void *fdt = gd->fdt_blob; - int node, reg, mode, len, val, offset; - const char *label; - u8 buf[2]; - int ret; - - node = fdt_node_offset_by_compatible(fdt, -1, "gw,gsc-adc"); - if (node <= 0) - return node; - - /* iterate over hwmon nodes */ - node = fdt_first_subnode(fdt, node); - while (node > 0) { - reg = fdtdec_get_int(fdt, node, "reg", -1); - mode = fdtdec_get_int(fdt, node, "gw,mode", -1); - offset = fdtdec_get_int(fdt, node, "gw,voltage-offset-microvolt", 0); - label = fdt_stringlist_get(fdt, node, "label", 0, NULL); - - if ((reg == -1) || (mode == -1) || !label) - printf("invalid dt:%s\n", fdt_get_name(fdt, node, NULL)); - - memset(buf, 0, sizeof(buf)); - ret = gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, sizeof(buf)); - val = buf[0] | buf[1] << 8; - if (val >= 0) { - const u32 *div; - int r[2]; - - switch (mode) { - case 0: /* temperature (C*10) */ - if (val > 0x8000) - val -= 0xffff; - printf("%-8s: %d.%ldC\n", label, val / 10, abs(val % 10)); - break; - case 1: /* prescaled voltage */ - if (val != 0xffff) - printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000); - break; - case 2: /* scaled based on ref volt and resolution */ - val *= 2500; - val /= 1 << 12; - - /* apply pre-scaler voltage divider */ - div = fdt_getprop(fdt, node, "gw,voltage-divider-ohms", &len); - if (div && (len == sizeof(uint32_t) * 2)) { - r[0] = fdt32_to_cpu(div[0]); - r[1] = fdt32_to_cpu(div[1]); - if (r[0] && r[1]) { - val *= (r[0] + r[1]); - val /= r[1]; - } - } - - /* adjust by offset */ - val += (offset / 1000); - - printf("%-8s: %d.%03dV\n", label, val / 1000, val % 1000); - break; - } - } - node = fdt_next_subnode(fdt, node); - } - - return 0; -} - -int gsc_info(int verbose) -{ - unsigned char buf[16]; - - if (gsc_i2c_read(GSC_SC_ADDR, 0, 1, buf, 16)) - return CMD_RET_FAILURE; - - printf("GSC: v%d", buf[GSC_SC_FWVER]); - printf(" 0x%04x", buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC+1]<<8); - printf(" WDT:%sabled", (buf[GSC_SC_CTRL1] & (1<<GSC_SC_CTRL1_WDEN)) - ? "en" : "dis"); - if (buf[GSC_SC_STATUS] & (1 << GSC_SC_IRQ_WATCHDOG)) { - buf[GSC_SC_STATUS] &= ~(1 << GSC_SC_IRQ_WATCHDOG); - puts(" WDT_RESET"); - gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, - &buf[GSC_SC_STATUS], 1); - } - printf(" board temp at %dC", gsc_get_board_temp() / 10); - puts("\n"); - if (!verbose) - return CMD_RET_SUCCESS; - - gsc_hwmon(); - - return 0; -} - -/* - * The Gateworks System Controller implements a boot - * watchdog (always enabled) as a workaround for IMX6 boot related - * errata such as: - * ERR005768 - no fix scheduled - * ERR006282 - fixed in silicon r1.2 - * ERR007117 - fixed in silicon r1.3 - * ERR007220 - fixed in silicon r1.3 - * ERR007926 - no fix scheduled - * see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf - * - * Disable the boot watchdog - */ -int gsc_boot_wd_disable(void) -{ - u8 reg; - - if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) { - reg |= (1 << GSC_SC_CTRL1_WDDIS); - if (!gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) - return 0; - } - puts("Error: could not disable GSC Watchdog\n"); - return 1; -} - -/* determine BOM revision from model */ -int get_bom_rev(const char *str) -{ - int rev_bom = 0; - int i; - - for (i = strlen(str) - 1; i > 0; i--) { - if (str[i] == '-') - break; - if (str[i] >= '1' && str[i] <= '9') { - rev_bom = str[i] - '0'; - break; - } - } - return rev_bom; -} - -/* determine PCB revision from model */ -char get_pcb_rev(const char *str) -{ - char rev_pcb = 'A'; - int i; - - for (i = strlen(str) - 1; i > 0; i--) { - if (str[i] == '-') - break; - if (str[i] >= 'A') { - rev_pcb = str[i]; - break; - } - } - return rev_pcb; -} - -/* - * get dt name based on model and detail level: - */ -const char *gsc_get_dtb_name(int level, char *buf, int sz) -{ - const char *model = (const char *)ventana_info.model; - const char *pre = is_mx6dq() ? "imx6q-" : "imx6dl-"; - int modelno, rev_pcb, rev_bom; - - /* a few board models are dt equivalents to other models */ - if (strncasecmp(model, "gw5906", 6) == 0) - model = "gw552x-d"; - else if (strncasecmp(model, "gw5908", 6) == 0) - model = "gw53xx-f"; - else if (strncasecmp(model, "gw5905", 6) == 0) - model = "gw5904-a"; - - modelno = ((model[2] - '0') * 1000) - + ((model[3] - '0') * 100) - + ((model[4] - '0') * 10) - + (model[5] - '0'); - rev_pcb = tolower(get_pcb_rev(model)); - rev_bom = get_bom_rev(model); - - /* compare model/rev/bom in order of most specific to least */ - snprintf(buf, sz, "%s%04d", pre, modelno); - switch (level) { - case 0: /* full model first (ie gw5400-a1) */ - if (rev_bom) { - snprintf(buf, sz, "%sgw%04d-%c%d", pre, modelno, rev_pcb, rev_bom); - break; - } - fallthrough; - case 1: /* don't care about bom rev (ie gw5400-a) */ - snprintf(buf, sz, "%sgw%04d-%c", pre, modelno, rev_pcb); - break; - case 2: /* don't care about the pcb rev (ie gw5400) */ - snprintf(buf, sz, "%sgw%04d", pre, modelno); - break; - case 3: /* look for generic model (ie gw540x) */ - snprintf(buf, sz, "%sgw%03dx", pre, modelno / 10); - break; - case 4: /* look for more generic model (ie gw54xx) */ - snprintf(buf, sz, "%sgw%02dxx", pre, modelno / 100); - break; - default: /* give up */ - return NULL; - } - - return buf; -} - -#if defined(CONFIG_CMD_GSC) && !defined(CONFIG_SPL_BUILD) -static int do_gsc_sleep(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - unsigned char reg; - unsigned long secs = 0; - - if (argc < 2) - return CMD_RET_USAGE; - - secs = dectoul(argv[1], NULL); - printf("GSC Sleeping for %ld seconds\n", secs); - - reg = (secs >> 24) & 0xff; - if (gsc_i2c_write(GSC_SC_ADDR, 9, 1, &reg, 1)) - goto error; - reg = (secs >> 16) & 0xff; - if (gsc_i2c_write(GSC_SC_ADDR, 8, 1, &reg, 1)) - goto error; - reg = (secs >> 8) & 0xff; - if (gsc_i2c_write(GSC_SC_ADDR, 7, 1, &reg, 1)) - goto error; - reg = secs & 0xff; - if (gsc_i2c_write(GSC_SC_ADDR, 6, 1, &reg, 1)) - goto error; - if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) - goto error; - reg |= (1 << 2); - if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) - goto error; - reg &= ~(1 << 2); - reg |= 0x3; - if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) - goto error; - - return CMD_RET_SUCCESS; - -error: - printf("i2c error\n"); - return CMD_RET_FAILURE; -} - -static int do_gsc_wd(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - unsigned char reg; - - if (argc < 2) - return CMD_RET_USAGE; - - if (strcasecmp(argv[1], "enable") == 0) { - int timeout = 0; - - if (argc > 2) - timeout = dectoul(argv[2], NULL); - if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) - return CMD_RET_FAILURE; - reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME)); - if (timeout == 60) - reg |= (1 << GSC_SC_CTRL1_WDTIME); - else - timeout = 30; - reg |= (1 << GSC_SC_CTRL1_WDEN); - if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) - return CMD_RET_FAILURE; - printf("GSC Watchdog enabled with timeout=%d seconds\n", - timeout); - } else if (strcasecmp(argv[1], "disable") == 0) { - if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) - return CMD_RET_FAILURE; - reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME)); - if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) - return CMD_RET_FAILURE; - printf("GSC Watchdog disabled\n"); - } else { - return CMD_RET_USAGE; - } - return CMD_RET_SUCCESS; -} - -static int do_gsc(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - if (argc < 2) - return gsc_info(1); - - if (strcasecmp(argv[1], "wd") == 0) - return do_gsc_wd(cmdtp, flag, --argc, ++argv); - else if (strcasecmp(argv[1], "sleep") == 0) - return do_gsc_sleep(cmdtp, flag, --argc, ++argv); - - return CMD_RET_USAGE; -} - -U_BOOT_CMD( - gsc, 4, 1, do_gsc, "GSC configuration", - "[wd enable [30|60]]|[wd disable]|[sleep <secs>]\n" - ); - -#endif /* CONFIG_CMD_GSC */ -- 2.17.1

2 1

[PATCH] imx8m: fix reading of DDR4 MR registers
by Rasmus Villemoes 20 May '22

20 May '22

I was trying to employ lpddr4_mr_read() to something similar to what the imx8mm-cl-iot-gate board is doing for auto-detecting the RAM type. However, the version in drivers/ddr/imx/imx8m/ddrphy_utils.c differs from the private one used by that board in how it extracts the byte value, and I was only getting zeroes. Adding a bit of debug printf'ing gives me tmp = 0x00ffff00 tmp = 0x00070700 tmp = 0x00000000 tmp = 0x00101000 and indeed I was expecting a (combined) value of 0xff070010 (0xff being Manufacturer ID for Micron). I can't find any documentation that says how the values are supposed to be read, but clearly the iot-gate definition is the right one, both for its use case as well as my imx8mp-based board. So lift the private definition of lpddr4_mr_read() from the imx8mm-cl-iot-gate board code to ddrphy_utils.c, and add a declaration in the ddr.h header where e.g. get_trained_CDD() is already declared. This has only been compile-tested for the imx8mm-cl-iot-gate board (since I don't have the hardware), but since I've merely moved its definition of lpddr4_mr_read(), I'd be surprised if it changed anything for that board. Signed-off-by: Rasmus Villemoes <rasmus.villemoes(a)prevas.dk> --- arch/arm/include/asm/arch-imx8m/ddr.h | 1 + board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c | 27 --------------------- drivers/ddr/imx/imx8m/ddrphy_utils.c | 9 +++++-- 3 files changed, 8 insertions(+), 29 deletions(-) diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h index 0f1e832c03..2ce8a8f2d4 100644 --- a/arch/arm/include/asm/arch-imx8m/ddr.h +++ b/arch/arm/include/asm/arch-imx8m/ddr.h @@ -723,6 +723,7 @@ void ddrphy_init_read_msg_block(enum fw_type type); void update_umctl2_rank_space_setting(unsigned int pstat_num); void get_trained_CDD(unsigned int fsp); +unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr); static inline void reg32_write(unsigned long addr, u32 val) { diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c index 5b93491923..b230478b61 100644 --- a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c +++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c @@ -24,33 +24,6 @@ #include <linux/delay.h> -static unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr) -{ - unsigned int tmp; - - reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1); - do { - tmp = reg32_read(DDRC_MRSTAT(0)); - } while (tmp & 0x1); - - reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1); - reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8)); - reg32setbit(DDRC_MRCTRL0(0), 31); - do { - tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0)); - } while ((tmp & 0x8) == 0); - tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0)); - reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4); - while (tmp) { //try to find a significant byte in the word - if (tmp & 0xff) { - tmp &= 0xff; - break; - } - tmp >>= 8; - } - return tmp; -} - struct lpddr4_desc { char name[16]; unsigned int id; diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c index a54449e5f1..975d553674 100644 --- a/drivers/ddr/imx/imx8m/ddrphy_utils.c +++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c @@ -198,9 +198,14 @@ unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr) tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0)); } while ((tmp & 0x8) == 0); tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0)); - tmp = tmp & 0xff; reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4); - + while (tmp) { //try to find a significant byte in the word + if (tmp & 0xff) { + tmp &= 0xff; + break; + } + tmp >>= 8; + } return tmp; } -- 2.31.1

5 4