May 2022 - U-Boot

[PULL] Pull request for u-boot master / v2022.07 = u-boot-stm32-20220520
by Patrick DELAUNAY 21 May '22

21 May '22

Hi Tom, Please pull the STM32 related fixes for u-boot/master, v2022.07: u-boot-stm32-20220520 - spi: fix busy bit check in stm32_qspi driver - stm32mp15: configure Buck3 voltage per PMIC NVM on Avenger96 board CI status: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/12043 Thanks, Patrick git request-pull origin/master https://source.denx.de/u-boot/custodians/u-boot-stm.git/ u-boot-stm32-20220520 The following changes since commit f83bd23e2a0e9861969c9d43395299a14f25ddda: Merge https://source.denx.de/u-boot/custodians/u-boot-marvell (2022-05-18 08:41:13 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-stm.git/ tags/u-boot-stm32-20220520 for you to fetch changes up to b6a469360a0dec01dbbf087c5184a59dda494569: spi: stm32_qspi: Remove SR_BUSY bit check before sending command (2022-05-19 18:54:18 +0200) ---------------------------------------------------------------- - spi: fix busy bit check in stm32_qspi driver - stm32mp15: configure Buck3 voltage per PMIC NVM on Avenger96 board ---------------------------------------------------------------- Marek Vasut (1): ARM: dts: stm32: Configure Buck3 voltage per PMIC NVM on Avenger96 Patrice Chotard (2): spi: stm32_qspi: Always check SR_TCF flags in stm32_qspi_wait_cmd() spi: stm32_qspi: Remove SR_BUSY bit check before sending command arch/arm/dts/stm32mp15xx-dhcor-io1v8.dtsi | 2 +- board/dhelectronics/dh_stm32mp1/board.c | 109 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--- drivers/spi/stm32_qspi.c | 27 +++++++++++---------------- 3 files changed, 118 insertions(+), 20 deletions(-)

2 1

[RFC PATCH 1/2] board: dhelectronics: stm32mp1: convert to livetree
by Patrick Delaunay 21 May '22

21 May '22

Replace call to fdt_*() functions and access to gd->fdt_blob with call to ofnode_*() functions to support a live tree. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- board/dhelectronics/dh_stm32mp1/board.c | 38 +++++++++++-------------- 1 file changed, 16 insertions(+), 22 deletions(-) diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index d407f0bf59..f5afe97c73 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -9,7 +9,6 @@ #include <net.h> #include <asm/arch/stm32.h> #include <asm/arch/sys_proto.h> -#include <asm/global_data.h> #include <asm/gpio.h> #include <asm/io.h> #include <bootm.h> @@ -78,11 +77,6 @@ #define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21) #define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23) -/* - * Get a global data pointer - */ -DECLARE_GLOBAL_DATA_PTR; - #define KS_CCR 0x08 #define KS_CCR_EEPROM BIT(9) #define KS_BE0 BIT(12) @@ -96,14 +90,15 @@ int setup_mac_address(void) bool skip_eth0 = false; bool skip_eth1 = false; struct udevice *dev; - int off, ret; + int ret; + ofnode node; ret = eth_env_get_enetaddr("ethaddr", enetaddr); if (ret) /* ethaddr is already set */ skip_eth0 = true; - off = fdt_path_offset(gd->fdt_blob, "ethernet1"); - if (off < 0) { + node = ofnode_path("ethernet1"); + if (!ofnode_valid(node)) { /* ethernet1 is not present in the system */ skip_eth1 = true; goto out_set_ethaddr; @@ -116,7 +111,7 @@ int setup_mac_address(void) goto out_set_ethaddr; } - ret = fdt_node_check_compatible(gd->fdt_blob, off, "micrel,ks8851-mll"); + ret = ofnode_device_is_compatible(node, "micrel,ks8851-mll"); if (ret) goto out_set_ethaddr; @@ -127,7 +122,7 @@ int setup_mac_address(void) * MAC address. */ u32 reg, cider, ccr; - reg = fdt_get_base_address(gd->fdt_blob, off); + reg = ofnode_get_addr(node); if (!reg) goto out_set_ethaddr; @@ -149,13 +144,13 @@ out_set_ethaddr: if (skip_eth0 && skip_eth1) return 0; - off = fdt_path_offset(gd->fdt_blob, "eeprom0"); - if (off < 0) { + node = ofnode_path("eeprom0"); + if (!ofnode_valid(node)) { printf("%s: No eeprom0 path offset\n", __func__); - return off; + return -ENOENT; } - ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev); + ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, node, &dev); if (ret) { printf("Cannot find EEPROM!\n"); return ret; @@ -191,8 +186,8 @@ int checkboard(void) mode = "basic"; printf("Board: stm32mp1 in %s mode", mode); - fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", - &fdt_compat_len); + fdt_compat = ofnode_get_property(ofnode_root(), "compatible", + &fdt_compat_len); if (fdt_compat && fdt_compat_len) printf(" (%s)", fdt_compat); puts("\n"); @@ -289,7 +284,7 @@ int board_fit_config_name_match(const char *name) const char *compat; char test[128]; - compat = fdt_getprop(gd->fdt_blob, 0, "compatible", NULL); + compat = ofnode_get_property(ofnode_root(), "compatible", NULL); snprintf(test, sizeof(test), "%s_somrev%d_boardrev%d", compat, somcode, brdcode); @@ -604,14 +599,13 @@ static void board_init_fmc2(void) #define STPMIC_NVM_BUCKS_VOUT_SHR_BUCK_OFFSET(n) ((((n) - 1) & 3) * 2) static int board_get_regulator_buck3_nvm_uv_av96(int *uv) { - const void *fdt = gd->fdt_blob; struct udevice *dev; u8 bucks_vout = 0; const char *prop; int len, ret; /* Check whether this is Avenger96 board. */ - prop = fdt_getprop(fdt, 0, "compatible", &len); + prop = ofnode_get_property(ofnode_root(), "compatible", &len); if (!prop || !len) return -ENODEV; @@ -701,8 +695,8 @@ int board_late_init(void) const void *fdt_compat; int fdt_compat_len; - fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", - &fdt_compat_len); + fdt_compat = ofnode_get_property(ofnode_root(), "compatible", + &fdt_compat_len); if (fdt_compat && fdt_compat_len) { if (strncmp(fdt_compat, "st,", 3) != 0) env_set("board_name", fdt_compat); -- 2.25.1

2 3

i.MX8MP usb status
by Peng Fan 21 May '22

21 May '22

Hi Marek, Since you did some work on i.MX8MP USB, may I know the status? Does host/device mode both supported in upstream? Any plan on PTN5110 support? Thanks, Peng.

9 15

[PATCH] configs: get rid of build warnings due to SPL_USB_DWC3_GENERIC
by Angus Ainslie 20 May '22

20 May '22

Adding the SPL_USB_DWC3_GENERIC symbol broke some ti builds. This should fix the builds but untested on HW. Signed-off-by: Angus Ainslie <angus(a)akkea.ca> --- configs/am43xx_evm_defconfig | 2 ++ configs/am43xx_evm_usbhost_boot_defconfig | 2 ++ configs/am43xx_hs_evm_defconfig | 2 ++ configs/am57xx_hs_evm_usb_defconfig | 2 ++ configs/am65x_evm_r5_usbdfu_defconfig | 2 ++ configs/dra7xx_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_defconfig | 2 ++ configs/dra7xx_hs_evm_usb_defconfig | 2 ++ 8 files changed, 16 insertions(+) diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 7a736b6fe1..13a305a53c 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -59,6 +59,7 @@ CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y CONFIG_MISC=y +CONFIG_SPL_MISC=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y @@ -93,6 +94,7 @@ CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index e844106243..b1f17c6a9e 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -8,6 +8,7 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm" CONFIG_AM43XX=y CONFIG_SPL=y +CONFIG_SPL_MISC=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set @@ -94,6 +95,7 @@ CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index d436b41a0c..206e5cf7bc 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -15,6 +15,7 @@ CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000 CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y +CONFIG_SPL_MISC=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT_IMAGE_POST_PROCESS=y CONFIG_SPL_LOAD_FIT=y @@ -97,6 +98,7 @@ CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index 6514a4f20c..dee35839c4 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -14,6 +14,7 @@ CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000 CONFIG_TARGET_AM57XX_EVM=y CONFIG_SPL=y +CONFIG_SPL_MISC=y CONFIG_ENV_OFFSET_REDUND=0x280000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y @@ -115,6 +116,7 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig index 57cd0f35a5..0430a94a7c 100644 --- a/configs/am65x_evm_r5_usbdfu_defconfig +++ b/configs/am65x_evm_r5_usbdfu_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_K3=y CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x55000 CONFIG_SPL_GPIO=y +CONFIG_SPL_MISC=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 @@ -111,6 +112,7 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 1aee9d742c..db7eb8efe9 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_TEXT_BASE=0x40300000 CONFIG_OMAP54XX=y CONFIG_TARGET_DRA7XX_EVM=y CONFIG_SPL=y +CONFIG_SPL_MISC=y CONFIG_ENV_OFFSET_REDUND=0x280000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y @@ -137,6 +138,7 @@ CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 728515d433..7796419f6b 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -13,6 +13,7 @@ CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000 CONFIG_TARGET_DRA7XX_EVM=y CONFIG_SPL=y +CONFIG_SPL_MISC=y CONFIG_ENV_OFFSET_REDUND=0x280000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y @@ -136,6 +137,7 @@ CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig index 9ebe45463c..bbb7a47d94 100644 --- a/configs/dra7xx_hs_evm_usb_defconfig +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -15,6 +15,7 @@ CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000 CONFIG_TARGET_DRA7XX_EVM=y CONFIG_SPL=y +CONFIG_SPL_MISC=y CONFIG_ENV_OFFSET_REDUND=0x280000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y @@ -124,6 +125,7 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_OMAP=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 -- 2.34.1

1 0

[PATCH] board: gateowrks: venice: add GW7903 PMIC
by Tim Harvey 20 May '22

20 May '22

The GW7903 has a BD71847 PMIC on I2C1. Adjust the model compare strings to add it. Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- board/gateworks/venice/spl.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c index 4c0feb4381c9..914a56a96f52 100644 --- a/board/gateworks/venice/spl.c +++ b/board/gateworks/venice/spl.c @@ -173,11 +173,12 @@ static int power_init_board(void) } else if ((!strncmp(model, "GW7901", 6)) || - (!strncmp(model, "GW7902", 6))) { - if (!strncmp(model, "GW7901", 6)) - ret = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus); - else + (!strncmp(model, "GW7902", 6)) || + (!strncmp(model, "GW7903", 6))) { + if (!strncmp(model, "GW7902", 6)) ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &bus); + else + ret = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus); if (ret) { printf("PMIC : failed I2C2 probe: %d\n", ret); return ret; -- 2.17.1

2 1

[PATCH] crypto/fsl: fsl_hash: Fix dcache issue in caam_hash_finish
by Gaurav Jain 20 May '22

20 May '22

HW accelerated hash operations are giving incorrect hash output. so add flush and invalidate for input/output hash buffers. Fixes: 94e3c8c4fd (crypto/fsl - Add progressive hashing support using hardware acceleration.) Signed-off-by: Gaurav Jain <gaurav.jain(a)nxp.com> --- drivers/crypto/fsl/fsl_hash.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index a52c4ac957..9e6829b7ad 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -149,12 +149,20 @@ static int caam_hash_finish(void *hash_ctx, void *dest_buf, driver_hash[caam_algo].digestsize, 1); + flush_dcache_range((ulong)ctx->sg_tbl, (ulong)(ctx->sg_tbl) + len); + flush_dcache_range((ulong)ctx->sha_desc, + (ulong)(ctx->sha_desc) + (sizeof(uint32_t) * MAX_CAAM_DESCSIZE)); + flush_dcache_range((ulong)ctx->hash, + (ulong)(ctx->hash) + driver_hash[caam_algo].digestsize); + ret = run_descriptor_jr(ctx->sha_desc); if (ret) { debug("Error %x\n", ret); return ret; } else { + invalidate_dcache_range((ulong)ctx->hash, + (ulong)(ctx->hash) + driver_hash[caam_algo].digestsize); memcpy(dest_buf, ctx->hash, sizeof(ctx->hash)); } free(ctx); -- 2.25.1

4 3

[PATCH v3 1/2] imx8mn_ddr4_evk: Add USB Mass Storage support
by Fabio Estevam 20 May '22

20 May '22

From: Fabio Estevam <festevam(a)denx.de> Add USB Mass Storage support, which is a convenient way to flash the eMMC card, for example. Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- Changes since v2: - None configs/imx8mn_ddr4_evk_defconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 917cdb5aa9d9..065f7392b706 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -42,6 +42,8 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y @@ -82,4 +84,14 @@ CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y +CONFIG_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_IMX_WATCHDOG=y -- 2.25.1

5 8

[PATCH V2 00/14] imx8m: convert to DM_SERIAL
by Peng Fan (OSS) 20 May '22

20 May '22

From: Peng Fan <peng.fan(a)nxp.com> V2: Drop patch patch 11 in V1, because it was included in https://patchwork.ozlabs.org/project/uboot/patch/20220503041429.30969-1-pen… phandle->phanbell Add R-b/T-b/A-b tags for the patchset This patchset is to convert some i.MX8M boards to DM SERIAL Note: this is based on my experience on i.MX8M*-EVK from NXP, I not have the following boards. If possible, please test. Peng Fan (14): imx: imx8mp_rsb3720a1: convert to DM_SERIAL imx: imx8m[m/n/p]_venice: Enable SPL_DM_SERIAL imx: imx8mm_mx8menlo: Enable DM_SERIAL imx: imx8m[m/n]_beacon: Enable SPL_DM_SERIAL imx: imx8mm-cl-iot-gate: Enable DM_SERIAL imx: imx8mm_icore: Enable SPL_DM_SERIAL imx: imx8m[m/p]_phycore: Enable DM_SERIAL imx: imx8mn_var_som: enable DM_SERIAL imx: imx8mm_edm_sbc: Enable SPL_DM_SERIAL imx: kontron-sl-mx8mm: enable DM_SERIAL imx: dts: move common changes to imx8mq-u-boot.dtsi imx: imx8mq-cm: enable CONFIG_DM_SERIAL imx: imx8mq-pico: enable CONFIG_DM_SERIAL imx: imx8mq-phanbell: enable CONFIG_DM_SERIAL arch/arm/dts/imx8mq-cm-u-boot.dtsi | 8 +++++++ arch/arm/dts/imx8mq-evk-u-boot.dtsi | 24 ------------------- arch/arm/dts/imx8mq-phanbell-u-boot.dtsi | 8 +++++++ arch/arm/dts/imx8mq-pico-pi-u-boot.dtsi | 9 +++++++ arch/arm/dts/imx8mq-u-boot.dtsi | 24 +++++++++++++++++++ .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 8 ------- board/beacon/imx8mm/spl.c | 12 ++-------- board/beacon/imx8mn/spl.c | 11 ++------- board/compulab/imx8mm-cl-iot-gate/spl.c | 12 ++-------- board/data_modul/imx8mm_edm_sbc/spl.c | 12 ++-------- board/engicam/imx8mm/spl.c | 14 +++-------- board/gateworks/venice/spl.c | 22 ++--------------- board/kontron/sl-mx8mm/spl.c | 12 ++-------- board/menlo/mx8menlo/mx8menlo.c | 9 ------- board/phytec/phycore_imx8mm/spl.c | 12 ++-------- board/phytec/phycore_imx8mp/spl.c | 8 ------- board/variscite/imx8mn_var_som/spl.c | 11 ++------- configs/imx8mm-cl-iot-gate-optee_defconfig | 1 + configs/imx8mm-cl-iot-gate_defconfig | 1 + configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 - configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 - configs/imx8mm-mx8menlo_defconfig | 1 + configs/imx8mm_beacon_defconfig | 1 - configs/imx8mm_data_modul_edm_sbc_defconfig | 1 - configs/imx8mm_venice_defconfig | 1 - configs/imx8mn_beacon_2g_defconfig | 1 - configs/imx8mn_beacon_defconfig | 1 - configs/imx8mn_var_som_defconfig | 1 + configs/imx8mn_venice_defconfig | 1 - configs/imx8mp_rsb3720a1_4G_defconfig | 1 + configs/imx8mp_rsb3720a1_6G_defconfig | 1 + configs/imx8mp_venice_defconfig | 1 - configs/imx8mq_cm_defconfig | 1 + configs/imx8mq_phanbell_defconfig | 1 + configs/kontron-sl-mx8mm_defconfig | 1 + configs/phycore-imx8mm_defconfig | 1 + configs/phycore-imx8mp_defconfig | 1 + configs/pico-imx8mq_defconfig | 1 + include/configs/imx8mm-cl-iot-gate.h | 2 -- include/configs/imx8mm-mx8menlo.h | 3 --- include/configs/imx8mm_beacon.h | 2 -- include/configs/imx8mm_data_modul_edm_sbc.h | 2 -- include/configs/imx8mm_icore_mx8mm.h | 3 --- include/configs/imx8mm_venice.h | 3 --- include/configs/imx8mn_beacon.h | 2 -- include/configs/imx8mn_var_som.h | 2 -- include/configs/imx8mn_venice.h | 3 --- include/configs/imx8mp_rsb3720.h | 2 -- include/configs/imx8mp_venice.h | 3 --- include/configs/kontron-sl-mx8mm.h | 1 - include/configs/phycore_imx8mm.h | 3 --- include/configs/phycore_imx8mp.h | 3 --- 52 files changed, 80 insertions(+), 191 deletions(-) create mode 100644 arch/arm/dts/imx8mq-pico-pi-u-boot.dtsi -- 2.36.0

3 22

[PATCH 1/3] imx8mm-cl-iot-gate: Enable cache in SPL
by Fabio Estevam 20 May '22

20 May '22

From: Fabio Estevam <festevam(a)denx.de> There is no reason for disabling I-cache and D-cache in SPL. Remove the unneeded CONFIG_SPL_SYS_ICACHE_OFF and CONFIG_SPL_SYS_DCACHE_OFF options. Signed-off-by: Fabio Estevam <festevam(a)denx.de> --- configs/imx8mm-cl-iot-gate-optee_defconfig | 2 -- configs/imx8mm-cl-iot-gate_defconfig | 2 -- 2 files changed, 4 deletions(-) diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig index 0bde51a91f53..8b3d1b3ef1a1 100644 --- a/configs/imx8mm-cl-iot-gate-optee_defconfig +++ b/configs/imx8mm-cl-iot-gate-optee_defconfig @@ -1,6 +1,4 @@ CONFIG_ARM=y -CONFIG_SPL_SYS_ICACHE_OFF=y -CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_ARCH_IMX8M=y CONFIG_SYS_TEXT_BASE=0x40200000 CONFIG_SPL_GPIO=y diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index d734586a60cc..b418e86248f9 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -1,6 +1,4 @@ CONFIG_ARM=y -CONFIG_SPL_SYS_ICACHE_OFF=y -CONFIG_SPL_SYS_DCACHE_OFF=y CONFIG_ARCH_IMX8M=y CONFIG_SYS_TEXT_BASE=0x40200000 CONFIG_SYS_MALLOC_LEN=0x2000000 -- 2.25.1

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[PATCH v3 1/2] pmic: pca9450: Add upstream regulators subnode match
by Marek Vasut 20 May '22

20 May '22

The upstream DT regulators node subnodes are named BUCKn and LDOn, the downstream DT regulators node subnodes are named buckn and ldon, add the upstream match. Reviewed-by: Fabio Estevam <festevam(a)denx.de> Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)denx.de> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- V2: Add RB by Fabio V3: No change --- drivers/power/pmic/pca9450.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index 2394b196c56..26c876c9c45 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR; static const struct pmic_child_info pmic_children_info[] = { /* buck */ { .prefix = "b", .driver = PCA9450_REGULATOR_DRIVER}, + { .prefix = "B", .driver = PCA9450_REGULATOR_DRIVER}, /* ldo */ { .prefix = "l", .driver = PCA9450_REGULATOR_DRIVER}, + { .prefix = "L", .driver = PCA9450_REGULATOR_DRIVER}, { }, }; -- 2.35.1

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