May 2022 - U-Boot

[PATCH] rockchip: rk3328: nanopi-r2s: Use the sdcard for the env
by Emmanuel Vadot 26 May '22

26 May '22

The NanoPi-R2S doesn't have eMMC so use the sdcard as the device to save the environment variables Signed-off-by: Emmanuel Vadot <manu(a)FreeBSD.org> --- configs/nanopi-r2s-rk3328_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index 453e54295d..0665368c4d 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -44,6 +44,7 @@ CONFIG_TPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TPL_DM=y -- 2.36.0

2 1

[PATCH v1] arm: dts: rockchip: rk3288: move dma-controller nodes
by Johan Jonker 26 May '22

26 May '22

In order to better compare the Linux rk3288.dtsi version with the u-boot version move the dma-controller nodes to the DT root. Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- arch/arm/dts/rk3288.dtsi | 76 ++++++++++++++++++---------------------- 1 file changed, 35 insertions(+), 41 deletions(-) diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 469df94e..53ee760b 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -86,47 +86,6 @@ }; }; - amba { - compatible = "arm,amba-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - dmac_peri: dma-controller@ff250000 { - compatible = "arm,pl330", "arm,primecell"; - broken-no-flushp; - reg = <0xff250000 0x4000>; - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC2>; - clock-names = "apb_pclk"; - }; - - dmac_bus_ns: dma-controller@ff600000 { - compatible = "arm,pl330", "arm,primecell"; - broken-no-flushp; - reg = <0xff600000 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - status = "disabled"; - }; - - dmac_bus_s: dma-controller@ffb20000 { - compatible = "arm,pl330", "arm,primecell"; - broken-no-flushp; - reg = <0xffb20000 0x4000>; - interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; - #dma-cells = <1>; - clocks = <&cru ACLK_DMAC1>; - clock-names = "apb_pclk"; - }; - }; - xin24m: oscillator { compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -367,6 +326,18 @@ pinctrl-0 = <&uart4_xfer>; status = "disabled"; }; + + dmac_peri: dma-controller@ff250000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xff250000 0x4000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + broken-no-flushp; + clocks = <&cru ACLK_DMAC2>; + clock-names = "apb_pclk"; + }; + thermal: thermal-zones { #include "rk3288-thermal.dtsi" }; @@ -458,6 +429,18 @@ status = "disabled"; }; + dmac_bus_ns: dma-controller@ff600000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xff600000 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + broken-no-flushp; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + i2c0: i2c@ff650000 { compatible = "rockchip,rk3288-i2c"; reg = <0xff650000 0x1000>; @@ -870,6 +853,17 @@ status = "disabled"; }; + dmac_bus_s: dma-controller@ffb20000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffb20000 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + broken-no-flushp; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + }; + efuse: efuse@ffb40000 { compatible = "rockchip,rk3288-efuse"; reg = <0xffb40000 0x10000>; -- 2.20.1

2 1

[PATCH v1] arm: dts: rockchip: rk3288: sort mipi hdmi lvds and dp nodes
by Johan Jonker 26 May '22

26 May '22

In order to better compare the Linux rk3288.dtsi version with the u-boot version sort the mipi,hdmi,lvds and dp nodes. Changed: Rename mipi_dsi label. Rename dp nodename. Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- arch/arm/dts/rk3288-evb.dtsi | 2 +- arch/arm/dts/rk3288.dtsi | 110 +++++++++++++++++------------------ 2 files changed, 56 insertions(+), 56 deletions(-) diff --git a/arch/arm/dts/rk3288-evb.dtsi b/arch/arm/dts/rk3288-evb.dtsi index 04902c0b..72da8847 100644 --- a/arch/arm/dts/rk3288-evb.dtsi +++ b/arch/arm/dts/rk3288-evb.dtsi @@ -448,7 +448,7 @@ status = "okay"; }; -&mipi_dsi0 { +&mipi_dsi { status = "disabled"; rockchip,panel = <&panel>; display-timings { diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 0bfa4c39..469df94e 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -709,54 +709,29 @@ status = "disabled"; }; - edp: edp@ff970000 { - compatible = "rockchip,rk3288-edp"; - reg = <0xff970000 0x4000>; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>; - rockchip,grf = <&grf>; - clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; - resets = <&cru 111>; - reset-names = "edp"; - power-domains = <&power RK3288_PD_VIO>; - status = "disabled"; - ports { - edp_in: port { - #address-cells = <1>; - #size-cells = <0>; - edp_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_edp>; - }; - edp_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_edp>; - }; - }; - }; - }; - - hdmi: hdmi@ff980000 { - compatible = "rockchip,rk3288-dw-hdmi"; - reg = <0xff980000 0x20000>; - reg-io-width = <4>; - ddc-i2c-bus = <&i2c5>; + mipi_dsi: mipi@ff960000 { + compatible = "rockchip,rk3288_mipi_dsi"; + reg = <0xff960000 0x4000>; + clocks = <&cru PCLK_MIPI_DSI0>; + clock-names = "pclk_mipi"; + /*pinctrl-names = "default"; + pinctrl-0 = <&lcdc0_ctl>;*/ rockchip,grf = <&grf>; - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; - clock-names = "iahb", "isfr"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; ports { - hdmi_in: port { + reg = <1>; + mipi_in: port { #address-cells = <1>; #size-cells = <0>; - hdmi_in_vopb: endpoint@0 { + mipi_in_vopb: endpoint@0 { reg = <0>; - remote-endpoint = <&vopb_out_hdmi>; + remote-endpoint = <&vopb_out_mipi>; }; - hdmi_in_vopl: endpoint@1 { + mipi_in_vopl: endpoint@1 { reg = <1>; - remote-endpoint = <&vopl_out_hdmi>; + remote-endpoint = <&vopl_out_mipi>; }; }; }; @@ -790,29 +765,54 @@ }; }; - mipi_dsi0: mipi@ff960000 { - compatible = "rockchip,rk3288_mipi_dsi"; - reg = <0xff960000 0x4000>; - clocks = <&cru PCLK_MIPI_DSI0>; - clock-names = "pclk_mipi"; - /*pinctrl-names = "default"; - pinctrl-0 = <&lcdc0_ctl>;*/ + edp: dp@ff970000 { + compatible = "rockchip,rk3288-edp"; + reg = <0xff970000 0x4000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>; rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; + clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; + resets = <&cru 111>; + reset-names = "edp"; + power-domains = <&power RK3288_PD_VIO>; status = "disabled"; ports { - reg = <1>; - mipi_in: port { + edp_in: port { #address-cells = <1>; #size-cells = <0>; - mipi_in_vopb: endpoint@0 { + edp_in_vopb: endpoint@0 { reg = <0>; - remote-endpoint = <&vopb_out_mipi>; + remote-endpoint = <&vopb_out_edp>; }; - mipi_in_vopl: endpoint@1 { + edp_in_vopl: endpoint@1 { reg = <1>; - remote-endpoint = <&vopl_out_mipi>; + remote-endpoint = <&vopl_out_edp>; + }; + }; + }; + }; + + hdmi: hdmi@ff980000 { + compatible = "rockchip,rk3288-dw-hdmi"; + reg = <0xff980000 0x20000>; + reg-io-width = <4>; + ddc-i2c-bus = <&i2c5>; + rockchip,grf = <&grf>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; + clock-names = "iahb", "isfr"; + status = "disabled"; + ports { + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_hdmi>; + }; + hdmi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_hdmi>; }; }; }; -- 2.20.1

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[PATCH v1] arm: dts: rockchip: rk3288: rename mmc nodenames
by Johan Jonker 26 May '22

26 May '22

The boot_devices constants for rk3288 were changed to match the binding, but the dtsi file was not synced. Fix by renaming the rk3288 mmc node names. Also correct the clock name for "ciu-drive". Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- arch/arm/dts/rk3288.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 5e40e741..0bfa4c39 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -150,48 +150,48 @@ ports = <&vopl_out>, <&vopb_out>; }; - sdmmc: dwmmc@ff0c0000 { + sdmmc: mmc@ff0c0000 { compatible = "rockchip,rk3288-dw-mshc"; max-frequency = <150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; reg = <0xff0c0000 0x4000>; status = "disabled"; }; - sdio0: dwmmc@ff0d0000 { + sdio0: mmc@ff0d0000 { compatible = "rockchip,rk3288-dw-mshc"; max-frequency = <150000000>; clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; reg = <0xff0d0000 0x4000>; status = "disabled"; }; - sdio1: dwmmc@ff0e0000 { + sdio1: mmc@ff0e0000 { compatible = "rockchip,rk3288-dw-mshc"; max-frequency = <150000000>; clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>, <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; reg = <0xff0e0000 0x4000>; status = "disabled"; }; - emmc: dwmmc@ff0f0000 { + emmc: mmc@ff0f0000 { compatible = "rockchip,rk3288-dw-mshc"; max-frequency = <150000000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; fifo-depth = <0x100>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; reg = <0xff0f0000 0x4000>; -- 2.20.1

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[PATCH v1] arm: dts: rockchip: rk3288: bulk convert gpios to their constant counterparts
by Johan Jonker 26 May '22

26 May '22

Bulk convert rk3288 DT gpios to their constant counterparts. Partial Linux sync for the rk3288.dtsi file. ARM: dts: rockchip: bulk convert gpios to their constant counterparts https://lore.kernel.org/all/20190402121852.14442-1-heiko@sntech.de/ sed -i -f script.sed rk3288.dtsi ================================ /rockchip,pins *=/bcheck b # to end of script :append-next-line N :check /^[^;]*$/bappend-next-line s/<RK_GPIO$[0-9]$ /<\1 /g s/<$[^ ][^ ]* *$0 /<\1RK_PA0 /g s/<$[^ ][^ ]* *$1 /<\1RK_PA1 /g s/<$[^ ][^ ]* *$2 /<\1RK_PA2 /g s/<$[^ ][^ ]* *$3 /<\1RK_PA3 /g s/<$[^ ][^ ]* *$4 /<\1RK_PA4 /g s/<$[^ ][^ ]* *$5 /<\1RK_PA5 /g s/<$[^ ][^ ]* *$6 /<\1RK_PA6 /g s/<$[^ ][^ ]* *$7 /<\1RK_PA7 /g s/<$[^ ][^ ]* *$8 /<\1RK_PB0 /g s/<$[^ ][^ ]* *$9 /<\1RK_PB1 /g s/<$[^ ][^ ]* *$10 /<\1RK_PB2 /g s/<$[^ ][^ ]* *$11 /<\1RK_PB3 /g s/<$[^ ][^ ]* *$12 /<\1RK_PB4 /g s/<$[^ ][^ ]* *$13 /<\1RK_PB5 /g s/<$[^ ][^ ]* *$14 /<\1RK_PB6 /g s/<$[^ ][^ ]* *$15 /<\1RK_PB7 /g s/<$[^ ][^ ]* *$16 /<\1RK_PC0 /g s/<$[^ ][^ ]* *$17 /<\1RK_PC1 /g s/<$[^ ][^ ]* *$18 /<\1RK_PC2 /g s/<$[^ ][^ ]* *$19 /<\1RK_PC3 /g s/<$[^ ][^ ]* *$20 /<\1RK_PC4 /g s/<$[^ ][^ ]* *$21 /<\1RK_PC5 /g s/<$[^ ][^ ]* *$22 /<\1RK_PC6 /g s/<$[^ ][^ ]* *$23 /<\1RK_PC7 /g s/<$[^ ][^ ]* *$24 /<\1RK_PD0 /g s/<$[^ ][^ ]* *$25 /<\1RK_PD1 /g s/<$[^ ][^ ]* *$26 /<\1RK_PD2 /g s/<$[^ ][^ ]* *$27 /<\1RK_PD3 /g s/<$[^ ][^ ]* *$28 /<\1RK_PD4 /g s/<$[^ ][^ ]* *$29 /<\1RK_PD5 /g s/<$[^ ][^ ]* *$30 /<\1RK_PD6 /g s/<$[^ ][^ ]* *$31 /<\1RK_PD7 /g s/<$[^ ][^ ]* *[^ ][^ ]* *$0 /<\1RK_FUNC_GPIO /g s/<$[^ ][^ ]* *[^ ][^ ]* *$RK_FUNC_$[1-9]$ /<\1\2 /g Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- arch/arm/dts/rk3288.dtsi | 274 +++++++++++++++++++-------------------- 1 file changed, 137 insertions(+), 137 deletions(-) diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index c4abfa37..5e40e741 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -1072,411 +1072,411 @@ sleep { global_pwroff: global-pwroff { - rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>; }; ddrio_pwroff: ddrio-pwroff { - rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; }; ddr0_retention: ddr0-retention { - rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_up>; }; ddr1_retention: ddr1-retention { - rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; }; }; i2c0 { i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, - <0 16 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>, + <0 RK_PC0 1 &pcfg_pull_none>; }; }; i2c1 { i2c1_xfer: i2c1-xfer { - rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>, - <8 5 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <8 RK_PA4 1 &pcfg_pull_none>, + <8 RK_PA5 1 &pcfg_pull_none>; }; }; i2c2 { i2c2_xfer: i2c2-xfer { - rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>, - <6 10 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <6 RK_PB1 1 &pcfg_pull_none>, + <6 RK_PB2 1 &pcfg_pull_none>; }; }; i2c3 { i2c3_xfer: i2c3-xfer { - rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>, - <2 17 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>, + <2 RK_PC1 1 &pcfg_pull_none>; }; }; i2c4 { i2c4_xfer: i2c4-xfer { - rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>, - <7 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <7 RK_PC1 1 &pcfg_pull_none>, + <7 RK_PC2 1 &pcfg_pull_none>; }; }; i2c5 { i2c5_xfer: i2c5-xfer { - rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>, - <7 20 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <7 RK_PC3 1 &pcfg_pull_none>, + <7 RK_PC4 1 &pcfg_pull_none>; }; }; i2s0 { i2s0_bus: i2s0-bus { - rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>, - <6 1 RK_FUNC_1 &pcfg_pull_none>, - <6 2 RK_FUNC_1 &pcfg_pull_none>, - <6 3 RK_FUNC_1 &pcfg_pull_none>, - <6 4 RK_FUNC_1 &pcfg_pull_none>, - <6 8 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <6 RK_PA0 1 &pcfg_pull_none>, + <6 RK_PA1 1 &pcfg_pull_none>, + <6 RK_PA2 1 &pcfg_pull_none>, + <6 RK_PA3 1 &pcfg_pull_none>, + <6 RK_PA4 1 &pcfg_pull_none>, + <6 RK_PB0 1 &pcfg_pull_none>; }; }; lcdc0 { lcdc0_ctl: lcdc0-ctl { - rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>, - <1 25 RK_FUNC_1 &pcfg_pull_none>, - <1 26 RK_FUNC_1 &pcfg_pull_none>, - <1 27 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, + <1 RK_PD1 1 &pcfg_pull_none>, + <1 RK_PD2 1 &pcfg_pull_none>, + <1 RK_PD3 1 &pcfg_pull_none>; }; }; sdmmc { sdmmc_clk: sdmmc-clk { - rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none>; }; sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <6 RK_PC5 1 &pcfg_pull_up>; }; sdmmc_cd: sdmcc-cd { - rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <6 RK_PC6 1 &pcfg_pull_up>; }; sdmmc_bus1: sdmmc-bus1 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>; }; sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>, - <6 17 RK_FUNC_1 &pcfg_pull_up>, - <6 18 RK_FUNC_1 &pcfg_pull_up>, - <6 19 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <6 RK_PC0 1 &pcfg_pull_up>, + <6 RK_PC1 1 &pcfg_pull_up>, + <6 RK_PC2 1 &pcfg_pull_up>, + <6 RK_PC3 1 &pcfg_pull_up>; }; }; sdio0 { sdio0_bus1: sdio0-bus1 { - rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>; }; sdio0_bus4: sdio0-bus4 { - rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, - <4 21 RK_FUNC_1 &pcfg_pull_up>, - <4 22 RK_FUNC_1 &pcfg_pull_up>, - <4 23 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <4 RK_PC4 1 &pcfg_pull_up>, + <4 RK_PC5 1 &pcfg_pull_up>, + <4 RK_PC6 1 &pcfg_pull_up>, + <4 RK_PC7 1 &pcfg_pull_up>; }; sdio0_cmd: sdio0-cmd { - rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <4 RK_PD0 1 &pcfg_pull_up>; }; sdio0_clk: sdio0-clk { - rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none>; }; sdio0_cd: sdio0-cd { - rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <4 RK_PD2 1 &pcfg_pull_up>; }; sdio0_wp: sdio0-wp { - rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <4 RK_PD3 1 &pcfg_pull_up>; }; sdio0_pwr: sdio0-pwr { - rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <4 RK_PD4 1 &pcfg_pull_up>; }; sdio0_bkpwr: sdio0-bkpwr { - rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <4 RK_PD5 1 &pcfg_pull_up>; }; sdio0_int: sdio0-int { - rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <4 RK_PD6 1 &pcfg_pull_up>; }; }; sdio1 { sdio1_bus1: sdio1-bus1 { - rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>; }; sdio1_bus4: sdio1-bus4 { - rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>, - <3 25 RK_FUNC_4 &pcfg_pull_up>, - <3 26 RK_FUNC_4 &pcfg_pull_up>, - <3 27 RK_FUNC_4 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD0 4 &pcfg_pull_up>, + <3 RK_PD1 4 &pcfg_pull_up>, + <3 RK_PD2 4 &pcfg_pull_up>, + <3 RK_PD3 4 &pcfg_pull_up>; }; sdio1_cd: sdio1-cd { - rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD4 4 &pcfg_pull_up>; }; sdio1_wp: sdio1-wp { - rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD5 4 &pcfg_pull_up>; }; sdio1_bkpwr: sdio1-bkpwr { - rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD6 4 &pcfg_pull_up>; }; sdio1_int: sdio1-int { - rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>; + rockchip,pins = <3 RK_PD7 4 &pcfg_pull_up>; }; sdio1_cmd: sdio1-cmd { - rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>; + rockchip,pins = <4 RK_PA6 4 &pcfg_pull_up>; }; sdio1_clk: sdio1-clk { - rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>; + rockchip,pins = <4 RK_PA7 4 &pcfg_pull_none>; }; sdio1_pwr: sdio1-pwr { - rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>; + rockchip,pins = <4 RK_PB1 4 &pcfg_pull_up>; }; }; emmc { emmc_clk: emmc-clk { - rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; + rockchip,pins = <3 RK_PC2 2 &pcfg_pull_none>; }; emmc_cmd: emmc-cmd { - rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PC0 2 &pcfg_pull_up>; }; emmc_pwr: emmc-pwr { - rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PB1 2 &pcfg_pull_up>; }; emmc_bus1: emmc-bus1 { - rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>; }; emmc_bus4: emmc-bus4 { - rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, - <3 1 RK_FUNC_2 &pcfg_pull_up>, - <3 2 RK_FUNC_2 &pcfg_pull_up>, - <3 3 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, + <3 RK_PA1 2 &pcfg_pull_up>, + <3 RK_PA2 2 &pcfg_pull_up>, + <3 RK_PA3 2 &pcfg_pull_up>; }; emmc_bus8: emmc-bus8 { - rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>, - <3 1 RK_FUNC_2 &pcfg_pull_up>, - <3 2 RK_FUNC_2 &pcfg_pull_up>, - <3 3 RK_FUNC_2 &pcfg_pull_up>, - <3 4 RK_FUNC_2 &pcfg_pull_up>, - <3 5 RK_FUNC_2 &pcfg_pull_up>, - <3 6 RK_FUNC_2 &pcfg_pull_up>, - <3 7 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <3 RK_PA0 2 &pcfg_pull_up>, + <3 RK_PA1 2 &pcfg_pull_up>, + <3 RK_PA2 2 &pcfg_pull_up>, + <3 RK_PA3 2 &pcfg_pull_up>, + <3 RK_PA4 2 &pcfg_pull_up>, + <3 RK_PA5 2 &pcfg_pull_up>, + <3 RK_PA6 2 &pcfg_pull_up>, + <3 RK_PA7 2 &pcfg_pull_up>; }; }; spi0 { spi0_clk: spi0-clk { - rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <5 RK_PB4 1 &pcfg_pull_up>; }; spi0_cs0: spi0-cs0 { - rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <5 RK_PB5 1 &pcfg_pull_up>; }; spi0_tx: spi0-tx { - rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <5 RK_PB6 1 &pcfg_pull_up>; }; spi0_rx: spi0-rx { - rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <5 RK_PB7 1 &pcfg_pull_up>; }; spi0_cs1: spi0-cs1 { - rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <5 RK_PC0 1 &pcfg_pull_up>; }; }; spi1 { spi1_clk: spi1-clk { - rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <7 RK_PB4 2 &pcfg_pull_up>; }; spi1_cs0: spi1-cs0 { - rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <7 RK_PB5 2 &pcfg_pull_up>; }; spi1_rx: spi1-rx { - rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <7 RK_PB6 2 &pcfg_pull_up>; }; spi1_tx: spi1-tx { - rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>; + rockchip,pins = <7 RK_PB7 2 &pcfg_pull_up>; }; }; spi2 { spi2_cs1: spi2-cs1 { - rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <8 RK_PA3 1 &pcfg_pull_up>; }; spi2_clk: spi2-clk { - rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <8 RK_PA6 1 &pcfg_pull_up>; }; spi2_cs0: spi2-cs0 { - rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <8 RK_PA7 1 &pcfg_pull_up>; }; spi2_rx: spi2-rx { - rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <8 RK_PB0 1 &pcfg_pull_up>; }; spi2_tx: spi2-tx { - rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>; + rockchip,pins = <8 RK_PB1 1 &pcfg_pull_up>; }; }; uart0 { uart0_xfer: uart0-xfer { - rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, - <4 17 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <4 RK_PC0 1 &pcfg_pull_up>, + <4 RK_PC1 1 &pcfg_pull_none>; }; uart0_cts: uart0-cts { - rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <4 RK_PC2 1 &pcfg_pull_none>; }; uart0_rts: uart0-rts { - rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <4 RK_PC3 1 &pcfg_pull_none>; }; }; uart1 { uart1_xfer: uart1-xfer { - rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>, - <5 9 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <5 RK_PB0 1 &pcfg_pull_up>, + <5 RK_PB1 1 &pcfg_pull_none>; }; uart1_cts: uart1-cts { - rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <5 RK_PB2 1 &pcfg_pull_none>; }; uart1_rts: uart1-rts { - rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <5 RK_PB3 1 &pcfg_pull_none>; }; }; uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>, - <7 23 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <7 RK_PC6 1 &pcfg_pull_up>, + <7 RK_PC7 1 &pcfg_pull_none>; }; /* no rts / cts for uart2 */ }; uart3 { uart3_xfer: uart3-xfer { - rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>, - <7 8 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <7 RK_PA7 1 &pcfg_pull_up>, + <7 RK_PB0 1 &pcfg_pull_none>; }; uart3_cts: uart3-cts { - rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <7 RK_PB1 1 &pcfg_pull_none>; }; uart3_rts: uart3-rts { - rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <7 RK_PB2 1 &pcfg_pull_none>; }; }; uart4 { uart4_xfer: uart4-xfer { - rockchip,pins = <5 12 3 &pcfg_pull_up>, - <5 13 3 &pcfg_pull_none>; + rockchip,pins = <5 RK_PB4 3 &pcfg_pull_up>, + <5 RK_PB5 3 &pcfg_pull_none>; }; uart4_cts: uart4-cts { - rockchip,pins = <5 14 3 &pcfg_pull_none>; + rockchip,pins = <5 RK_PB6 3 &pcfg_pull_none>; }; uart4_rts: uart4-rts { - rockchip,pins = <5 15 3 &pcfg_pull_none>; + rockchip,pins = <5 RK_PB7 3 &pcfg_pull_none>; }; }; tsadc { otp_out: otp-out { - rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <0 RK_PB2 1 &pcfg_pull_none>; }; }; pwm0 { pwm0_pin: pwm0-pin { - rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <7 RK_PA0 1 &pcfg_pull_none>; }; }; pwm1 { pwm1_pin: pwm1-pin { - rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <7 RK_PA1 1 &pcfg_pull_none>; }; }; pwm2 { pwm2_pin: pwm2-pin { - rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>; + rockchip,pins = <7 RK_PC6 3 &pcfg_pull_none>; }; }; pwm3 { pwm3_pin: pwm3-pin { - rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>; + rockchip,pins = <7 RK_PC7 3 &pcfg_pull_none>; }; }; gmac { rgmii_pins: rgmii-pins { - rockchip,pins = <3 30 3 &pcfg_pull_none>, - <3 31 3 &pcfg_pull_none>, - <3 26 3 &pcfg_pull_none>, - <3 27 3 &pcfg_pull_none>, - <3 28 3 &pcfg_pull_none_12ma>, - <3 29 3 &pcfg_pull_none_12ma>, - <3 24 3 &pcfg_pull_none_12ma>, - <3 25 3 &pcfg_pull_none_12ma>, - <4 0 3 &pcfg_pull_none>, - <4 5 3 &pcfg_pull_none>, - <4 6 3 &pcfg_pull_none>, - <4 9 3 &pcfg_pull_none_12ma>, - <4 4 3 &pcfg_pull_none_12ma>, - <4 1 3 &pcfg_pull_none>, - <4 3 3 &pcfg_pull_none>; + rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, + <3 RK_PD7 3 &pcfg_pull_none>, + <3 RK_PD2 3 &pcfg_pull_none>, + <3 RK_PD3 3 &pcfg_pull_none>, + <3 RK_PD4 3 &pcfg_pull_none_12ma>, + <3 RK_PD5 3 &pcfg_pull_none_12ma>, + <3 RK_PD0 3 &pcfg_pull_none_12ma>, + <3 RK_PD1 3 &pcfg_pull_none_12ma>, + <4 RK_PA0 3 &pcfg_pull_none>, + <4 RK_PA5 3 &pcfg_pull_none>, + <4 RK_PA6 3 &pcfg_pull_none>, + <4 RK_PB1 3 &pcfg_pull_none_12ma>, + <4 RK_PA4 3 &pcfg_pull_none_12ma>, + <4 RK_PA1 3 &pcfg_pull_none>, + <4 RK_PA3 3 &pcfg_pull_none>; }; rmii_pins: rmii-pins { - rockchip,pins = <3 30 3 &pcfg_pull_none>, - <3 31 3 &pcfg_pull_none>, - <3 28 3 &pcfg_pull_none>, - <3 29 3 &pcfg_pull_none>, - <4 0 3 &pcfg_pull_none>, - <4 5 3 &pcfg_pull_none>, - <4 4 3 &pcfg_pull_none>, - <4 1 3 &pcfg_pull_none>, - <4 2 3 &pcfg_pull_none>, - <4 3 3 &pcfg_pull_none>; + rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>, + <3 RK_PD7 3 &pcfg_pull_none>, + <3 RK_PD4 3 &pcfg_pull_none>, + <3 RK_PD5 3 &pcfg_pull_none>, + <4 RK_PA0 3 &pcfg_pull_none>, + <4 RK_PA5 3 &pcfg_pull_none>, + <4 RK_PA4 3 &pcfg_pull_none>, + <4 RK_PA1 3 &pcfg_pull_none>, + <4 RK_PA2 3 &pcfg_pull_none>, + <4 RK_PA3 3 &pcfg_pull_none>; }; }; spdif { spdif_tx: spdif-tx { - rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>; + rockchip,pins = <6 RK_PB3 1 &pcfg_pull_none>; }; }; }; -- 2.20.1

2 1

[PATCH v1 1/4] rockchip: usb: gadget: add rk3066 product id
by Johan Jonker 26 May '22

26 May '22

From: Paweł Jarosz <paweljarosz3691(a)gmail.com> Product id of rk3066 usb otg is 0x300a. Signed-off-by: Paweł Jarosz <paweljarosz3691(a)gmail.com> Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- drivers/usb/gadget/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index d81a9c5a..8c6cf474 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -61,6 +61,7 @@ config USB_GADGET_PRODUCT_NUM hex "Product ID of the USB device" default 0x1010 if ARCH_SUNXI default 0x310a if ROCKCHIP_RK3036 + default 0x300a if ROCKCHIP_RK3066 default 0x310c if ROCKCHIP_RK3128 default 0x320a if ROCKCHIP_RK3229 || ROCKCHIP_RK3288 default 0x330a if ROCKCHIP_RK3328 -- 2.20.1

2 7

[PATCH 0/2] Rockchip: Add option to prevent boot on plug-in
by Chris Morgan 26 May '22

26 May '22

From: Chris Morgan <macromorgan(a)hotmail.com> Sometimes it is desirable to prevent a board from automatically booting as soon as the power cable is plugged in. For boards with an rk8xx PMIC, (excluding the rk808) we can actually query the power up source. Chris Morgan (2): power: pmic: rk8xx: Support sysreset shutdown method rockchip: Add option to prevent booting on power plug-in arch/arm/mach-rockchip/Kconfig | 10 ++++ drivers/power/pmic/rk8xx.c | 92 +++++++++++++++++++++++++++++++++- include/power/rk8xx_pmic.h | 3 ++ 3 files changed, 104 insertions(+), 1 deletion(-) -- 2.25.1

3 5

[PATCH 0/2] fix issues in bootmenu after adding efi entries
by Masahisa Kojima 26 May '22

26 May '22

This series fixes the issue in bootmenu after adding efi entries. Masahisa Kojima (2): bootmenu: use utf-8 for menu title bootmenu: U-Boot console is enabled as default boot/Kconfig | 9 +++++++++ cmd/Kconfig | 10 ---------- cmd/bootmenu.c | 40 +++++++++++++++++++++++----------------- 3 files changed, 32 insertions(+), 27 deletions(-) -- 2.17.1

3 6

Raspberry Pi won’t boot from compressed subvolume (BTRFS)
by Nathan Henrie 25 May '22

25 May '22

Hello u-boot team, I’ve been experimenting for about a year with a NixOS-based Raspberry Pi image, with the end goal of a zstd-compressed image that uses BTRFS subvolumes, having the root filesystem at @ and boot at @boot (with several other subvolumes). The NixOS Raspberry Pi images use u-boot by default. I’ve started a few discussions in the NixOS community as I learn and iterate: https://discourse.nixos.org/t/raspberry-pi-nixos-on-btrfs-root/14081 and I’ve made my code available at: https://github.com/n8henrie/nixos-btrfs-pi . I’m sure it’s obvious (or will be soon) that I’m a hobbyist, a novice with NixOS, and that I understand very little about u-boot and bootloaders in general, so I hope you can be patient as I humbly ask for someone to point me in the right direction. For reference, the official NixOS code for generating u-boot images is here: https://github.com/NixOS/nixpkgs/blob/3d4e586313d292c9e764a8e88a1fdccb16ffb… I’ve made a lot of progress, including an image that reliably boots from @boot to the @ root subvolume with the u-boot configuration: CONFIG_CMD_BTRFS=y CONFIG_ZSTD=y CONFIG_BOOTCOMMAND="setenv boot_prefixes / /boot/ /@/ /@boot/; run distro_bootcmd;" with kernel params: "root=LABEL=NIXOS_SD" "rootfstype=btrfs" "rootflags=subvol=@" Unfortunately, after the initial boot and going through the initial OS installation steps, if I have compression enabled, it reboots into a boot loop with the following error messages: Scanning mmc 0:2... Found /(a)boot/extlinux/extlinux.conf Retrieving file: /(a)boot/extlinux/extlinux.conf 2938 bytes read in 27 ms (105.5 KiB/s) 1 NixOS Default 2 NixOS Configuration 4 (2022-02-24 21:34 22.05pre356135.7f9b6c2babf) 3 NixOS Configuration 3 (2022-02-25 03:59 22.05pre356435.7/9b6eZbabf) 4: NixOS Configuration 2 (2022-02-24 21:34 22.05pre356435.7/9b6c2babr) 5: NixOS Enter choice: 1: NixOS - Default Retrieving file: /@boot/extlinux/..nixos/zhbharzhzqga617uc37uk0g6q1bx891u-initrd-linux-5.10.101-initrd 20588420 bytes read in 1910 ms (10.3 MiB/s) Retrieving file: /@boot/extlinux/..nixos/6c1m6j0k1gmjrmikOyyizariiry?Zlqr-linux-5.10.101-Image 50629120 bytes read in 6863 ms (7 MiB/s) append: init-mix/store/pikl8ju4077iaix36n8mifzu6l6rcajz-nixos-system-nixpi-22.05p re356435-7/9b6eZbabf/init console=tty1 console=ttyAMAO console=ttyS0, 1115200 root= LABEL=-NIXOS_SD rootfstype=btrfs rootflags=subvol=@ loglevel=4 Retrieving file: /@boot/extlinux/../nixos/6c16j0k1gmjrmikOyyizari1ry72lqr-linux-5.10.101-dtbs/broadcon/bcn2837-rpi-3-b.dtb 14310 bytes read in 66 ms (210.9 KiB/s) Moving Image from 0x80000 to 0x200000, end=32f0000 ## Flattened Device Tree blob at 03700000 Booting using the fdt blob at 0x3700000 Using Device Tree in place at 0000000003700000 end 00000000037067e5 fdt_find_or_add_subnode: memory: FDT_ERR_BADSTRUCTURE ERROR: arch-specific fdt fixup failed - must RESET the board to recover. FDT creation failed! resetting ... This happens even though I have CONFIG_ZSTD=y. If I do *not* enable compression (in my BTRFS mount options), it reboots normally and everything works! I may have made some OCR / C&P errors above; I’ve posted some pictures of the error messages (and similar discussion to this email, with no responses) here: https://discourse.nixos.org/t/btrfs-pi-wont-boot-from-compressed-subvolume/… I’m not currently using BTRFS RAID, just a single device. One of my other (x86_64) machines uses a similar setup with @, @boot, and zstd-compression with grub and works well, so I’m hoping this is also possible with u-boot. Seeing that the errors mention the FDT and fixup, I tried CONFIG_ARCH_FIXUP_FDT_MEMORY with both =y and =n without interesting changes to the error messages. What I’m assuming, based on the above, is that re-writing the @boot subvolume with compression is moving the location of the device tree files and that u-boot is no longer able to find the necessary files (some of which I think may also be in the nix store in the @nix subvolume). Does that sound like a reasonable guess as to what is going on? If so, are there config options or settings that I might be able to use to help u-boot find the necessary files after things are re-written with compression? Many thanks in advance for your time and attention, and thanks for your hard work on u-boot!

2 2

[PATCH] arm: socfpga: Add the terasic de10-standard board
by Humberto Naves 25 May '22

25 May '22

Used the de10-nano files as templates for the de10-standard board. Changed the iocsr_config.h and pinmux_config.h based on the handoff files generated by quartus. Finally, the pll_config.h was copied from the altera cyclone5-socdk board. Signed-off-by: Humberto Naves <hsnaves(a)gmail.com> Cc: Marek Vasut <marex(a)denx.de> --- .../dts/socfpga_cyclone5_de10_standard.dts | 86 +++ arch/arm/mach-socfpga/Kconfig | 7 + board/terasic/de10-standard/MAINTAINERS | 5 + board/terasic/de10-standard/Makefile | 6 + .../terasic/de10-standard/qts/iocsr_config.h | 659 ++++++++++++++++++ .../terasic/de10-standard/qts/pinmux_config.h | 218 ++++++ board/terasic/de10-standard/qts/pll_config.h | 84 +++ .../terasic/de10-standard/qts/sdram_config.h | 343 +++++++++ board/terasic/de10-standard/socfpga.c | 5 + configs/socfpga_de10_standard_defconfig | 66 ++ include/configs/socfpga_de10_standard.h | 16 + 11 files changed, 1495 insertions(+) create mode 100644 arch/arm/dts/socfpga_cyclone5_de10_standard.dts create mode 100644 board/terasic/de10-standard/MAINTAINERS create mode 100644 board/terasic/de10-standard/Makefile create mode 100644 board/terasic/de10-standard/qts/iocsr_config.h create mode 100644 board/terasic/de10-standard/qts/pinmux_config.h create mode 100644 board/terasic/de10-standard/qts/pll_config.h create mode 100644 board/terasic/de10-standard/qts/sdram_config.h create mode 100644 board/terasic/de10-standard/socfpga.c create mode 100644 configs/socfpga_de10_standard_defconfig create mode 100644 include/configs/socfpga_de10_standard.h diff --git a/arch/arm/dts/socfpga_cyclone5_de10_standard.dts b/arch/arm/dts/socfpga_cyclone5_de10_standard.dts new file mode 100644 index 0000000000..ccd1413184 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_de10_standard.dts @@ -0,0 +1,86 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017, Intel Corporation + * + * based on socfpga_cyclone5_de10_nano.dts + */ + +#include "socfpga_cyclone5.dtsi" +#include "socfpga-common-u-boot.dtsi" + +/ { + model = "Terasic DE10-Standard"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = &gmac1; + udc0 = &usb1; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + txen-skew-ps = <0>; + txc-skew-ps = <1860>; + rxdv-skew-ps = <420>; + rxc-skew-ps = <1680>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; + +&mmc0 { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&usb1 { + status = "okay"; +}; + +&uart0 { + clock-frequency = <100000000>; + u-boot,dm-pre-reloc; +}; + +&watchdog0 { + status = "disabled"; +}; diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 78a7549a41..547e47ed9d 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -180,6 +180,10 @@ config TARGET_SOCFPGA_TERASIC_DE10_NANO bool "Terasic DE10-Nano (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_TERASIC_DE10_STANDARD + bool "Terasic DE10-Standard (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + config TARGET_SOCFPGA_TERASIC_DE1_SOC bool "Terasic DE1-SoC (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -199,6 +203,7 @@ config SYS_BOARD default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO + default "de10-standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD default "is1" if TARGET_SOCFPGA_IS1 default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK @@ -224,6 +229,7 @@ config SYS_VENDOR default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO + default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT config SYS_SOC @@ -239,6 +245,7 @@ config SYS_CONFIG_NAME default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO + default "socfpga_de10_standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD default "socfpga_is1" if TARGET_SOCFPGA_IS1 default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK diff --git a/board/terasic/de10-standard/MAINTAINERS b/board/terasic/de10-standard/MAINTAINERS new file mode 100644 index 0000000000..94bf1e03ee --- /dev/null +++ b/board/terasic/de10-standard/MAINTAINERS @@ -0,0 +1,5 @@ +DE10-STANDARD BOARD +M: Humberto Naves <hsnaves(a)gmail.com> +S: Maintained +F: include/configs/socfpga_de10_standard.h +F: configs/socfpga_de10_standard_defconfig diff --git a/board/terasic/de10-standard/Makefile b/board/terasic/de10-standard/Makefile new file mode 100644 index 0000000000..2cf9240846 --- /dev/null +++ b/board/terasic/de10-standard/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2017, Intel Corporation +# +# + +obj-y := socfpga.o diff --git a/board/terasic/de10-standard/qts/iocsr_config.h b/board/terasic/de10-standard/qts/iocsr_config.h new file mode 100644 index 0000000000..aad2715d52 --- /dev/null +++ b/board/terasic/de10-standard/qts/iocsr_config.h @@ -0,0 +1,659 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Altera SoCFPGA IOCSR configuration + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00000000, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00020000, + 0x06018000, + 0x06000000, + 0x00000018, + 0x00006018, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x000C0300, + 0x300C0000, + 0x300000C0, + 0x000000C0, + 0x000300C0, + 0x00008000, + 0x00060180, + 0x18060000, + 0x00000000, + 0x00000080, + 0x00020000, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x06018060, + 0x06018000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x0000C030, + 0x0300C000, + 0x03000000, + 0x0000300C, + 0x0000300C, + 0x00000800, + 0x00000000, + 0x00000000, + 0x01800000, + 0x00000006, + 0x00002000, + 0x00000400, + 0x00000000, + 0x00C03000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00601806, + 0x00000000, + 0x80600000, + 0x80000601, + 0x00000601, + 0x00000100, + 0x00300C03, + 0xC0300C00, + 0xC0300000, + 0xC0000300, + 0x000C0300, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x300C0300, + 0x00000000, + 0x0FF00000, + 0x00000000, + 0x0C0300C0, + 0x00008000, + 0x18060180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00020000, + 0x00004000, + 0x200300C0, + 0x0C030000, + 0x00000030, + 0x00000000, + 0x0300C030, + 0x00002000, + 0x10018060, + 0x06018000, + 0x06000000, + 0x00010018, + 0x00006018, + 0x00001000, + 0x0000C030, + 0x00000000, + 0x03000000, + 0x0000800C, + 0x00C0300C, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x0C420D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x40680208, + 0x41034051, + 0x02081A00, + 0x802080D0, + 0x34010406, + 0x01A02490, + 0x080D0000, + 0x51406802, + 0x00410340, + 0xD000001A, + 0x06802080, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x40680C30, + 0x49034010, + 0x12481A02, + 0x802080D0, + 0x34051406, + 0x01A00040, + 0x080D0002, + 0x51406802, + 0x02490340, + 0xD012481A, + 0x06802080, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x18864000, + 0x49247A06, + 0xE3CF23DA, + 0xF796591E, + 0x0344E388, + 0x821A0000, + 0x0000D000, + 0x01040680, + 0xD271C47A, + 0x1EE3CF23, + 0x88F79659, + 0x000344E3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x18864000, + 0x49247A06, + 0xA3CF23DA, + 0xF796591E, + 0x0344E388, + 0x821A028A, + 0x0000D000, + 0x00000680, + 0xD271C47A, + 0x1EA2CB23, + 0x88F79A69, + 0x000344E3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x04864000, + 0x69A47A01, + 0x9228A3D6, + 0xF456591E, + 0x03549248, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD669A47A, + 0x1EE3CF23, + 0x48F45659, + 0x00035492, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x08864000, + 0x71C47A02, + 0xA2CB23D2, + 0xF796591E, + 0x0344A288, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xDA49247A, + 0x1EE3CF23, + 0x88F79659, + 0x000344E3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x08000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; + + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/terasic/de10-standard/qts/pinmux_config.h b/board/terasic/de10-standard/qts/pinmux_config.h new file mode 100644 index 0000000000..f4399c654a --- /dev/null +++ b/board/terasic/de10-standard/qts/pinmux_config.h @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Altera SoCFPGA PinMux configuration + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 0, /* EMACIO0 - Unused */ + 2, /* EMACIO1 - USB */ + 2, /* EMACIO2 - USB */ + 2, /* EMACIO3 - USB */ + 2, /* EMACIO4 - USB */ + 2, /* EMACIO5 - USB */ + 2, /* EMACIO6 - USB */ + 2, /* EMACIO7 - USB */ + 2, /* EMACIO8 - USB */ + 0, /* EMACIO9 - Unused */ + 2, /* EMACIO10 - USB */ + 2, /* EMACIO11 - USB */ + 2, /* EMACIO12 - USB */ + 2, /* EMACIO13 - USB */ + 0, /* EMACIO14 - N/A */ + 0, /* EMACIO15 - N/A */ + 0, /* EMACIO16 - N/A */ + 0, /* EMACIO17 - N/A */ + 0, /* EMACIO18 - N/A */ + 0, /* EMACIO19 - N/A */ + 3, /* FLASHIO0 - SDMMC */ + 0, /* FLASHIO1 - SDMMC */ + 3, /* FLASHIO2 - SDMMC */ + 3, /* FLASHIO3 - SDMMC */ + 0, /* FLASHIO4 - SDMMC */ + 0, /* FLASHIO5 - SDMMC */ + 0, /* FLASHIO6 - SDMMC */ + 0, /* FLASHIO7 - SDMMC */ + 0, /* FLASHIO8 - SDMMC */ + 3, /* FLASHIO9 - SDMMC */ + 3, /* FLASHIO10 - SDMMC */ + 3, /* FLASHIO11 - SDMMC */ + 0, /* GENERALIO0 - TRACE */ + 1, /* GENERALIO1 - TRACE */ + 1, /* GENERALIO2 - TRACE */ + 1, /* GENERALIO3 - TRACE */ + 1, /* GENERALIO4 - TRACE */ + 0, /* GENERALIO5 - TRACE */ + 0, /* GENERALIO6 - TRACE */ + 1, /* GENERALIO7 - TRACE */ + 1, /* GENERALIO8 - TRACE */ + 3, /* GENERALIO9 - SPIM0 */ + 3, /* GENERALIO10 - SPIM0 */ + 3, /* GENERALIO11 - SPIM0 */ + 3, /* GENERALIO12 - SPIM0 */ + 0, /* GENERALIO13 - CAN0 */ + 0, /* GENERALIO14 - CAN0 */ + 1, /* GENERALIO15 - I2C0 */ + 1, /* GENERALIO16 - I2C0 */ + 1, /* GENERALIO17 - UART0 */ + 1, /* GENERALIO18 - UART0 */ + 0, /* GENERALIO19 - N/A */ + 0, /* GENERALIO20 - N/A */ + 0, /* GENERALIO21 - N/A */ + 0, /* GENERALIO22 - N/A */ + 0, /* GENERALIO23 - N/A */ + 0, /* GENERALIO24 - N/A */ + 0, /* GENERALIO25 - N/A */ + 0, /* GENERALIO26 - N/A */ + 0, /* GENERALIO27 - N/A */ + 0, /* GENERALIO28 - N/A */ + 0, /* GENERALIO29 - N/A */ + 0, /* GENERALIO30 - N/A */ + 0, /* GENERALIO31 - N/A */ + 2, /* MIXED1IO0 - EMAC */ + 2, /* MIXED1IO1 - EMAC */ + 2, /* MIXED1IO2 - EMAC */ + 2, /* MIXED1IO3 - EMAC */ + 2, /* MIXED1IO4 - EMAC */ + 2, /* MIXED1IO5 - EMAC */ + 2, /* MIXED1IO6 - EMAC */ + 2, /* MIXED1IO7 - EMAC */ + 2, /* MIXED1IO8 - EMAC */ + 2, /* MIXED1IO9 - EMAC */ + 2, /* MIXED1IO10 - EMAC */ + 2, /* MIXED1IO11 - EMAC */ + 2, /* MIXED1IO12 - EMAC */ + 2, /* MIXED1IO13 - EMAC */ + 0, /* MIXED1IO14 - Unused */ + 3, /* MIXED1IO15 - QSPI */ + 3, /* MIXED1IO16 - QSPI */ + 3, /* MIXED1IO17 - QSPI */ + 3, /* MIXED1IO18 - QSPI */ + 3, /* MIXED1IO19 - QSPI */ + 3, /* MIXED1IO20 - QSPI */ + 0, /* MIXED1IO21 - GPIO */ + 0, /* MIXED2IO0 - N/A */ + 0, /* MIXED2IO1 - N/A */ + 0, /* MIXED2IO2 - N/A */ + 0, /* MIXED2IO3 - N/A */ + 0, /* MIXED2IO4 - N/A */ + 0, /* MIXED2IO5 - N/A */ + 0, /* MIXED2IO6 - N/A */ + 0, /* MIXED2IO7 - N/A */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/terasic/de10-standard/qts/pll_config.h b/board/terasic/de10-standard/qts/pll_config.h new file mode 100644 index 0000000000..ae5cfab0cf --- /dev/null +++ b/board/terasic/de10-standard/qts/pll_config.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Altera SoCFPGA Clock and PLL configuration + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 1 + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73 +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CONFIG_HPS_CLK_OSC1_HZ 25000000 +#define CONFIG_HPS_CLK_OSC2_HZ 25000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 +#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 +#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 +#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 +#define CONFIG_HPS_CLK_NAND_HZ 50000000 +#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 +#define CONFIG_HPS_CLK_QSPI_HZ 370000000 +#define CONFIG_HPS_CLK_SPIM_HZ 200000000 +#define CONFIG_HPS_CLK_CAN0_HZ 100000000 +#define CONFIG_HPS_CLK_CAN1_HZ 12500000 +#define CONFIG_HPS_CLK_GPIODB_HZ 32000 +#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 +#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 + +#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 4 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4 + + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/terasic/de10-standard/qts/sdram_config.h b/board/terasic/de10-standard/qts/sdram_config.h new file mode 100644 index 0000000000..26910ef348 --- /dev/null +++ b/board/terasic/de10-standard/qts/sdram_config.h @@ -0,0 +1,343 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Altera SoCFPGA SDRAM configuration + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define RW_MGR_GUARANTEED_READ 0x4C +#define RW_MGR_GUARANTEED_READ_CONT 0x54 +#define RW_MGR_GUARANTEED_WRITE 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7B +#define RW_MGR_IDLE_LOOP2 0x7A +#define RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x59 +#define RW_MGR_READ_B2B_WAIT1 0x61 +#define RW_MGR_READ_B2B_WAIT2 0x6B +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7D +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 8 +#define CALIB_VFIFO_OFFSET 6 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 312 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504a1 +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 99 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 99 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x20700000, + 0x20780000, + 0x10080431, + 0x10080530, + 0x10090044, + 0x100a0010, + 0x100b0000, + 0x10380400, + 0x10080449, + 0x100804c8, + 0x100a0024, + 0x10090008, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/terasic/de10-standard/socfpga.c b/board/terasic/de10-standard/socfpga.c new file mode 100644 index 0000000000..f9173f1921 --- /dev/null +++ b/board/terasic/de10-standard/socfpga.c @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017, Intel Corporation + */ +#include <common.h> diff --git a/configs/socfpga_de10_standard_defconfig b/configs/socfpga_de10_standard_defconfig new file mode 100644 index 0000000000..91bd49840d --- /dev/null +++ b/configs/socfpga_de10_standard_defconfig @@ -0,0 +1,66 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_MALLOC_LEN=0x4000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x4400 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de10_standard" +CONFIG_SPL_TEXT_BASE=0xFFFF0000 +CONFIG_TARGET_SOCFPGA_TERASIC_DE10_STANDARD=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_TIMESTAMP=y +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de10_standard.dtb" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CLOCKS=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_VERSION_VARIABLE=y +CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_MMC_DW=y +CONFIG_MTD=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="terasic" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +# CONFIG_SPL_WDT is not set diff --git a/include/configs/socfpga_de10_standard.h b/include/configs/socfpga_de10_standard.h new file mode 100644 index 0000000000..4d6719eb52 --- /dev/null +++ b/include/configs/socfpga_de10_standard.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2017, Intel Corporation + */ +#ifndef __CONFIG_TERASIC_DE10_STANDARD_H__ +#define __CONFIG_TERASIC_DE10_STANDARD_H__ + +#include <asm/arch/base_addr_ac5.h> + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ + +/* The rest of the configuration is shared */ +#include <configs/socfpga_common.h> + +#endif /* __CONFIG_TERASIC_DE10_STANDARD_H__ */ -- 2.36.1

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