May 2022 - U-Boot

[PATCH] net: e1000: Depend on CONFIG_PCI
by Sean Anderson 27 May '22

27 May '22

This driver depends on PCI. Update the Kconfig accordingly. Signed-off-by: Sean Anderson <sean.anderson(a)seco.com> --- drivers/net/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 347fe8aa42..339ccdae15 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -231,6 +231,7 @@ config DWC_ETH_QOS_TEGRA186 config E1000 bool "Intel PRO/1000 Gigabit Ethernet support" + depends on PCI help This driver supports Intel(R) PRO/1000 gigabit ethernet family of adapters. For more information on how to identify your adapter, go -- 2.35.1.1320.gc452695387.dirty

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[PATCH v2] imx8m: fixup thermal trips
by Andrejs Cainikovs 27 May '22

27 May '22

Fixup thermal trips in Linux device tree according to SoC thermal grade. Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs(a)toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini(a)toradex.com> Tested-by: Adam Ford <aford173(a)gmail.com> --- arch/arm/mach-imx/imx8m/soc.c | 49 +++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 59335356b5..e4e56079cf 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -1203,6 +1203,48 @@ static int cleanup_nodes_for_efi(void *blob) return 0; } +static int fixup_thermal_trips(void *blob, const char *name) +{ + int minc, maxc; + int node, trip; + + node = fdt_path_offset(blob, "/thermal-zones"); + if (node < 0) + return node; + + node = fdt_subnode_offset(blob, node, name); + if (node < 0) + return node; + + node = fdt_subnode_offset(blob, node, "trips"); + if (node < 0) + return node; + + get_cpu_temp_grade(&minc, &maxc); + + fdt_for_each_subnode(trip, blob, node) { + const char *type; + int temp, ret; + + type = fdt_getprop(blob, trip, "type", NULL); + if (!type) + continue; + + temp = 0; + if (!strcmp(type, "critical")) + temp = 1000 * maxc; + else if (!strcmp(type, "passive")) + temp = 1000 * (maxc - 10); + if (temp) { + ret = fdt_setprop_u32(blob, trip, "temperature", temp); + if (ret) + return ret; + } + } + + return 0; +} + int ft_system_setup(void *blob, struct bd_info *bd) { #ifdef CONFIG_IMX8MQ @@ -1345,6 +1387,13 @@ usb_modify_speed: #endif cleanup_nodes_for_efi(blob); + + if (fixup_thermal_trips(blob, "cpu-thermal")) + printf("Failed to update cpu-thermal trip(s)"); + if (IS_ENABLED(CONFIG_IMX8MP) && + fixup_thermal_trips(blob, "soc-thermal")) + printf("Failed to update soc-thermal trip(s)"); + return 0; } #endif -- 2.34.1

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Re: Fwd: dlmalloc hanging
by Heinrich Schuchardt 27 May '22

27 May '22

Am 27. Mai 2022 09:52:04 MESZ schrieb Oleksii Kurochko <oleksii.kurochko(a)gmail.com>: >Hello Heinrich, > >get_maintainer.pl script told me that you are a maintainer of dlmalloc.c Hello Oleksii, I am not the maintainer of dlmalloc.c but only a contributor. >so if you don't mind I would like to ask you for advice about >how could debugging of dlmalloc allocation be done? > >I faced the issue that hanging happens during the freeing of >resources [ >https://elixir.bootlin.com/u-boot/latest/source/arch/arm/lib/bootm.c#L77] >before U-boot finally will transfer control to Linux Kernel. >I did a little investigation and found out that hanging >happens here [ >https://elixir.bootlin.com/u-boot/latest/source/common/dlmalloc.c#L940] >and it happens because FD->fd points to itself so a cycle occurs. Does the problem exist in mainline U-Boot? How can it be reproduced in mainline U-Boot? If it is a Bootlin specific problem, please, consider contacting that company. Possible reasons for running into problems in dlmalloc.c are double frees and out of bound writing to memory. Best regards Heinrich > >Should be a check added here which will check that FD->fd does not point to >itself or >does a guarantee exist that the cycle can't be at all? > >Also, I tried to do "#define DEBUG" at the top of dlmalloc.c >and I started to be asserted here: >https://elixir.bootlin.com/u-boot/latest/source/common/dlmalloc.c#L842 >during the mentioned transfer from U-boot to kernel. > >I also tried to understand why it is in the used state and I couldn't find >where it is actually switched to the unused state. At least clear_inuse() >macros aren't used elsewhere in file dlmalloc.c. > >Interesting behavior has been obtained. It looks like that for >the number of lines in CONFIG_EXTRA_ENV_SETTINGS there is no >hanging at all during mentioned above transfer. So I can assume that >it might be allocated a buffer or pointer to its buffer is overwritten >because of the memory alignment of an array that uses >CONFIG_EXTRA_ENV_SETTINGS. > >Could you please give me some advice on how such behavior >could be debugged? > >Thanks in advance. > >Best regards, > > Oleksii

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[PATCH 0/2] tpm: Add support for TPMv2.x I2C chips
by Eddie James 27 May '22

27 May '22

Add a tpm driver that should support any TPMv2 compliant I2C chips, such as the NPCT75X chip. In my testing I also noticed that the timeouts weren't set before requesting the locality so I have included a fix. Eddie James (2): tpm: core: Set timeouts before requesting locality tpm: add support for TPMv2.x I2C chips drivers/tpm/Kconfig | 9 ++ drivers/tpm/Makefile | 1 + drivers/tpm/tpm2_tis_core.c | 7 +- drivers/tpm/tpm2_tis_i2c.c | 171 ++++++++++++++++++++++++++++++++++++ 4 files changed, 185 insertions(+), 3 deletions(-) create mode 100644 drivers/tpm/tpm2_tis_i2c.c -- 2.27.0

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[PATCH 00/14] SCMI multi-channel and optee shm
by Etienne Carriere 27 May '22

27 May '22

Dear all, This series implements 2 features in driver/firmware/scmi. First, a single change adds support for SCMI OP-TEE transport to use OP-TEE native shared memory. See the 1st patch in this series: "firmware: scmi: optee: use TEE shared memory for SCMI messages". Then come changes for supporting multi-channel in the SCMI drivers. I've split the implementation in 11 several small incremental changes in the hope it helps the review. Few minor fixup commits are also inserted in the series. Regards, Etienne Etienne Carriere (14): firmware: scmi: optee: use TEE shared memory for SCMI messages firmware: scmi: optee: fix inline description of PTA_SCMI_CMD_GET_CHANNEL firmware: scmi: prepare scmi uclass API to multi-channel firmware: scmi: prepare uclass to pass channel reference firmware: scmi: factorize scmi transport look up firmware: scmi: add multi-channel support firmware: scmi: mailbox transport: implement multi-channel firmware: scmi: smccc transport: implement multi-channel firmware: scmi: optee transport: implement multi-channel clk: scmi: support SCMI multi-channel reset: scmi: support SCMI multi-channel power: regulator: scmi: support SCMI multi-channel power: regulator: scmi: simplify scmi_voltd_set_enable() firmware: scmi: use multi channel in mailbox, optee and smccc agents drivers/clk/clk_scmi.c | 23 +++- drivers/firmware/scmi/mailbox_agent.c | 65 +++++++-- drivers/firmware/scmi/optee_agent.c | 147 ++++++++++++++++----- drivers/firmware/scmi/sandbox-scmi_agent.c | 1 + drivers/firmware/scmi/scmi_agent-uclass.c | 48 +++++-- drivers/firmware/scmi/smccc_agent.c | 56 +++++++- drivers/firmware/scmi/smt.c | 53 +++++++- drivers/firmware/scmi/smt.h | 45 ++++++- drivers/power/regulator/scmi_regulator.c | 26 ++-- drivers/reset/reset-scmi.c | 15 ++- include/scmi_agent-uclass.h | 15 ++- include/scmi_agent.h | 14 +- 12 files changed, 431 insertions(+), 77 deletions(-) -- 2.25.1

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imx8mm eLCDIF clock
by Tommaso Merciai 27 May '22

27 May '22

Hi, I'm working on drivers/clk/imx/clk-imx8mm.c to port and bring up eLCDIF clocks. After port all necessary clocks needed by eLCDIF I found that IMX8MM_VIDEO_PLL1 clock is not enabled and need the following code to enable it at the end of the clk-imx8mm probe: struct clk *clkp; clk_get_by_id(IMX8MM_VIDEO_PLL1, &clkp); clk_set_rate(clkp, 594000000UL); clk_enable(clkp); What do you think about this solution? There is a more standard way to do this? Thanks, Tommmaso -- Tommaso Merciai Embedded Linux Engineer tommaso.merciai(a)amarulasolutions.com __________________________________ Amarula Solutions SRL Via Le Canevare 30, 31100 Treviso, Veneto, IT T. +39 042 243 5310 info(a)amarulasolutions.com www.amarulasolutions.com

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[PATCH 1/2] mmc: Add support for wait_dat0 callback
by Loic Poulain 27 May '22

27 May '22

There is no wait_dat0 mmc ops, causing operations waiting for data line state change (e.g mmc_switch_voltage) to fallback to a 250ms active delay. mmc_ops still used when DM_MMC is not enabled, which is often the case for SPL. The result can be unexpectly long SPL boot time. This change adds support for wait_dat0() mmc operation. Signed-off-by: Loic Poulain <loic.poulain(a)linaro.org> --- drivers/mmc/mmc.c | 3 +++ include/mmc.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index f6ccd83..109f340 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -34,6 +34,9 @@ static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage); static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us) { + if (mmc->cfg->ops->wait_dat0) + return mmc->cfg->ops->wait_dat0(mmc, state, timeout_us); + return -ENOSYS; } diff --git a/include/mmc.h b/include/mmc.h index 6bdcce8..b7e94e8 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -561,6 +561,7 @@ struct mmc_ops { int (*getwp)(struct mmc *mmc); int (*host_power_cycle)(struct mmc *mmc); int (*get_b_max)(struct mmc *mmc, void *dst, lbaint_t blkcnt); + int (*wait_dat0)(struct mmc *mmc, int state, int timeout_us); }; static inline int mmc_hs400_prepare_ddr(struct mmc *mmc) -- 2.7.4

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[PATCH] usb: xhci-mtk: disable all ports when disable host controller
by Chunfeng Yun 27 May '22

27 May '22

This is used to avoid the ports status of IPPC being brought in kernel stage, it may cause ports error especially when the xhci controller is a component of dual-role controller. Reported-by: Yun-Chien Yu <yun-chien.yu(a)mediatek.com> Signed-off-by: Chunfeng Yun <chunfeng.yun(a)mediatek.com> --- drivers/usb/host/xhci-mtk.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c index 18b4f55d89..3838a990ec 100644 --- a/drivers/usb/host/xhci-mtk.c +++ b/drivers/usb/host/xhci-mtk.c @@ -122,11 +122,13 @@ static int xhci_mtk_host_disable(struct mtk_xhci *mtk) /* power down all u3 ports */ for (i = 0; i < mtk->num_u3ports; i++) - setbits_le32(mtk->ippc + IPPC_U3_CTRL(i), CTRL_U3_PORT_PDN); + setbits_le32(mtk->ippc + IPPC_U3_CTRL(i), + CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS); /* power down all u2 ports */ for (i = 0; i < mtk->num_u2ports; i++) - setbits_le32(mtk->ippc + IPPC_U2_CTRL(i), CTRL_U2_PORT_PDN); + setbits_le32(mtk->ippc + IPPC_U2_CTRL(i), + CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS); /* power down host ip */ setbits_le32(mtk->ippc + IPPC_IP_PW_CTRL1, CTRL1_IP_HOST_PDN); -- 2.18.0

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[PATCH v1 0/9] Introduce HPE GXP Architecture
by nick.hawkins＠hpe.com 26 May '22

26 May '22

From: Nick Hawkins <nick.hawkins(a)hpe.com> The GXP is the HPE BMC SoC that is used in the majority of HPE current generation servers. Traditionally the asic will last multiple generations of server before being replaced. Info about SoC: HPE GXP is the name of the HPE SoC. This SoC is used to implement many BMC features at HPE. It supports ARMv7 architecture based on the Cortex A9 core. It is capable of using an AXI bus to which a memory controller is attached. It has multiple SPI interfaces to connect boot flash and BIOS flash. It uses a 10/100/1000 MAC for network connectivity. It has multiple i2c engines to drive connectivity with a host infrastructure. The initial patches enable the timer enabling U-Boot prompt to work. Nick Hawkins (9): ARM: hpe: gxp: add core support timer: gxp: Add HPE GXP timer support board: hpe: gxp: add HPE GXP soc support dt-bindings: arm: hpe: add GXP Support dt-bindings: timer: Add hpe gxp timer ARM: dts: Add device tree files for hpe gxp soc configs: gxp: add core support configs: gxp: add gxp_defconfig MAINTAINERS: Introduce HPE GXP Architecture MAINTAINERS | 12 +++ arch/arm/Kconfig | 8 ++ arch/arm/Makefile | 1 + arch/arm/dts/Makefile | 2 + arch/arm/dts/hpe-bmc-dl360gen10.dts | 26 +++++ arch/arm/dts/hpe-gxp.dtsi | 95 ++++++++++++++++++ arch/arm/mach-hpe/Makefile | 1 + arch/arm/mach-hpe/gxp/Kconfig | 9 ++ arch/arm/mach-hpe/gxp/Makefile | 1 + arch/arm/mach-hpe/gxp/reset.c | 26 +++++ board/hpe/gxp/Kconfig | 47 +++++++++ board/hpe/gxp/Makefile | 1 + board/hpe/gxp/gxp_board.c | 33 +++++++ configs/gxp_defconfig | 48 ++++++++++ doc/device-tree-bindings/arm/hpe,gxp.yaml | 27 ++++++ .../timer/hpe,gxp-timer.yaml | 47 +++++++++ drivers/timer/Kconfig | 7 ++ drivers/timer/Makefile | 1 + drivers/timer/gxp-timer.c | 65 +++++++++++++ include/configs/gxp.h | 96 +++++++++++++++++++ 20 files changed, 553 insertions(+) create mode 100644 arch/arm/dts/hpe-bmc-dl360gen10.dts create mode 100644 arch/arm/dts/hpe-gxp.dtsi create mode 100644 arch/arm/mach-hpe/Makefile create mode 100644 arch/arm/mach-hpe/gxp/Kconfig create mode 100644 arch/arm/mach-hpe/gxp/Makefile create mode 100644 arch/arm/mach-hpe/gxp/reset.c create mode 100644 board/hpe/gxp/Kconfig create mode 100644 board/hpe/gxp/Makefile create mode 100644 board/hpe/gxp/gxp_board.c create mode 100644 configs/gxp_defconfig create mode 100644 doc/device-tree-bindings/arm/hpe,gxp.yaml create mode 100644 doc/device-tree-bindings/timer/hpe,gxp-timer.yaml create mode 100644 drivers/timer/gxp-timer.c create mode 100644 include/configs/gxp.h -- 2.17.1

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[PATCH v1 1/8] timer: gxp: Add HPE GXP timer support
by nick.hawkins＠hpe.com 26 May '22

26 May '22

From: Nick Hawkins <nick.hawkins(a)hpe.com> Add support for the HPE GXP SOC timer. The GXP supports several different kinds of timers but for the purpose of this driver there is only support for the General Timer. The timer has a 1us resolution and is 56 bits. Signed-off-by: Nick Hawkins <nick.hawkins(a)hpe.com> --- drivers/timer/Kconfig | 7 +++++ drivers/timer/Makefile | 1 + drivers/timer/gxp-timer.c | 65 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 73 insertions(+) create mode 100644 drivers/timer/gxp-timer.c diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 7b8ab56ed3..d592dba285 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -139,6 +139,13 @@ config DESIGNWARE_APB_TIMER Enables support for the Designware APB Timer driver. This timer is present on Altera SoCFPGA SoCs. +config GXP_TIMER + bool "HPE GXP Timer" + depends on TIMER + help + Enables support for the GXP Timer driver. This timer is + present on HPE GXP SoCs. + config MPC83XX_TIMER bool "MPC83xx timer support" depends on TIMER diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index b2f002d597..cc2b8516b5 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_$(SPL_)ATMEL_PIT_TIMER) += atmel_pit_timer.o obj-$(CONFIG_$(SPL_)ATMEL_TCB_TIMER) += atmel_tcb_timer.o obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o +obj-$(CONFIG_GXP_TIMER) += gxp-timer.o obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o obj-$(CONFIG_NOMADIK_MTU_TIMER) += nomadik-mtu-timer.o obj-$(CONFIG_NPCM_TIMER) += npcm-timer.o diff --git a/drivers/timer/gxp-timer.c b/drivers/timer/gxp-timer.c new file mode 100644 index 0000000000..db11eddf74 --- /dev/null +++ b/drivers/timer/gxp-timer.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * GXP timer driver + * + * (C) Copyright 2022 Hewlett Packard Enterprise Development LP. + * Author: Nick Hawkins <nick.hawkins(a)hpe.com> + * Author: Jean-Marie Verdun <verdun(a)hpe.com> + */ + +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <timer.h> +#include <asm/io.h> + +#define USTIMELO 0x18 +#define USTIMEHI 0x1C + +struct gxp_timer_priv { + void __iomem *base; +}; + +static u64 gxp_timer_get_count(struct udevice *dev) +{ + struct gxp_timer_priv *priv = dev_get_priv(dev); + u64 val; + + val = readl(priv->base + USTIMEHI); + val = (val << 32) | readl(priv->base + USTIMELO); + + return val; +} + +static int gxp_timer_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct gxp_timer_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -ENOENT; + + uc_priv->clock_rate = 1000000; + + return 0; +} + +static const struct timer_ops gxp_timer_ops = { + .get_count = gxp_timer_get_count, +}; + +static const struct udevice_id gxp_timer_ids[] = { + { .compatible = "hpe,gxp-timer" }, + {} +}; + +U_BOOT_DRIVER(gxp_timer) = { + .name = "gxp-timer", + .id = UCLASS_TIMER, + .of_match = gxp_timer_ids, + .priv_auto = sizeof(struct gxp_timer_priv), + .probe = gxp_timer_probe, + .ops = &gxp_timer_ops, + .flags = DM_FLAG_PRE_RELOC, +}; -- 2.17.1

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