May 2022 - U-Boot

[PATCH 1/2] board: stm32mp1: convert to livetree
by Patrick Delaunay 17 Jun '22

17 Jun '22

Replace gd->fdt_blob access with fdt_getprop() function to the function ofnode_get_property() to support a live tree. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- board/st/stm32mp1/stm32mp1.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 07b1a63db7..700ff9ca07 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -82,11 +82,6 @@ #define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21) #define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23) -/* - * Get a global data pointer - */ -DECLARE_GLOBAL_DATA_PTR; - #define USB_LOW_THRESHOLD_UV 200000 #define USB_WARNING_LOW_THRESHOLD_UV 660000 #define USB_START_LOW_THRESHOLD_UV 1230000 @@ -116,8 +111,8 @@ int checkboard(void) mode = "basic"; } - fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", - &fdt_compat_len); + fdt_compat = ofnode_get_property(ofnode_root(), "compatible", + &fdt_compat_len); log_info("Board: stm32mp1 in %s mode (%s)\n", mode, fdt_compat && fdt_compat_len ? fdt_compat : ""); @@ -690,8 +685,8 @@ int board_late_init(void) int buf_len; if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { - fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", - &fdt_compat_len); + fdt_compat = ofnode_get_property(ofnode_root(), "compatible", + &fdt_compat_len); if (fdt_compat && fdt_compat_len) { if (strncmp(fdt_compat, "st,", 3) != 0) { env_set("board_name", fdt_compat); -- 2.25.1

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[PATCH 1/2] stm32mp: fdt: update etzpc for STM32MP15x
by Patrick Delaunay 17 Jun '22

17 Jun '22

Introduce STM32MP15 function and defines to prepare the STM32MP13 introduction. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- arch/arm/mach-stm32mp/fdt.c | 123 ++++++++++++++++++++---------------- 1 file changed, 67 insertions(+), 56 deletions(-) diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c index ad45728949..5d37a44d97 100644 --- a/arch/arm/mach-stm32mp/fdt.c +++ b/arch/arm/mach-stm32mp/fdt.c @@ -28,13 +28,13 @@ #define ETZPC_RESERVED 0xffffffff -#define STM32_FDCAN_BASE 0x4400e000 -#define STM32_CRYP2_BASE 0x4c005000 -#define STM32_CRYP1_BASE 0x54001000 -#define STM32_GPU_BASE 0x59000000 -#define STM32_DSI_BASE 0x5a000000 +#define STM32MP15_FDCAN_BASE 0x4400e000 +#define STM32MP15_CRYP2_BASE 0x4c005000 +#define STM32MP15_CRYP1_BASE 0x54001000 +#define STM32MP15_GPU_BASE 0x59000000 +#define STM32MP15_DSI_BASE 0x5a000000 -static const u32 stm32mp1_ip_addr[] = { +static const u32 stm32mp15_ip_addr[] = { 0x5c008000, /* 00 stgenc */ 0x54000000, /* 01 bkpsram */ 0x5c003000, /* 02 iwdg1 */ @@ -44,7 +44,7 @@ static const u32 stm32mp1_ip_addr[] = { ETZPC_RESERVED, /* 06 reserved */ 0x54003000, /* 07 rng1 */ 0x54002000, /* 08 hash1 */ - STM32_CRYP1_BASE, /* 09 cryp1 */ + STM32MP15_CRYP1_BASE, /* 09 cryp1 */ 0x5a003000, /* 0A ddrctrl */ 0x5a004000, /* 0B ddrphyc */ 0x5c009000, /* 0C i2c6 */ @@ -97,7 +97,7 @@ static const u32 stm32mp1_ip_addr[] = { 0x4400b000, /* 3B sai2 */ 0x4400c000, /* 3C sai3 */ 0x4400d000, /* 3D dfsdm */ - STM32_FDCAN_BASE, /* 3E tt_fdcan */ + STM32MP15_FDCAN_BASE, /* 3E tt_fdcan */ ETZPC_RESERVED, /* 3F reserved */ 0x50021000, /* 40 lptim2 */ 0x50022000, /* 41 lptim3 */ @@ -110,7 +110,7 @@ static const u32 stm32mp1_ip_addr[] = { 0x48003000, /* 48 adc */ 0x4c002000, /* 49 hash2 */ 0x4c003000, /* 4A rng2 */ - STM32_CRYP2_BASE, /* 4B cryp2 */ + STM32MP15_CRYP2_BASE, /* 4B cryp2 */ ETZPC_RESERVED, /* 4C reserved */ ETZPC_RESERVED, /* 4D reserved */ ETZPC_RESERVED, /* 4E reserved */ @@ -163,8 +163,13 @@ static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node) int offset, shift; u32 addr, status, decprot[ETZPC_DECPROT_NB]; - array = stm32mp1_ip_addr; - array_size = ARRAY_SIZE(stm32mp1_ip_addr); + if (IS_ENABLED(CONFIG_STM32MP13x)) + return 0; + + if (IS_ENABLED(CONFIG_STM32MP15x)) { + array = stm32mp15_ip_addr; + array_size = ARRAY_SIZE(stm32mp15_ip_addr); + } for (i = 0; i < ETZPC_DECPROT_NB; i++) decprot[i] = readl(ETZPC_DECPROT(i)); @@ -248,33 +253,9 @@ static void stm32_fdt_disable_optee(void *blob) } } -/* - * This function is called right before the kernel is booted. "blob" is the - * device tree that will be passed to the kernel. - */ -int ft_system_setup(void *blob, struct bd_info *bd) +static void stm32mp15_fdt_fixup(void *blob, int soc, u32 cpu, char *name) { - int ret = 0; - int soc; - u32 pkg, cpu; - char name[SOC_NAME_SIZE]; - - if (IS_ENABLED(CONFIG_STM32MP13x)) - return 0; - - soc = fdt_path_offset(blob, "/soc"); - if (soc < 0) - return soc; - - if (CONFIG_IS_ENABLED(STM32_ETZPC)) { - ret = stm32_fdt_fixup_etzpc(blob, soc); - if (ret) - return ret; - } - - /* MPUs Part Numbers and name*/ - cpu = get_cpu_type(); - get_soc_name(name); + u32 pkg; switch (cpu) { case CPU_STM32MP151Fxx: @@ -284,19 +265,18 @@ int ft_system_setup(void *blob, struct bd_info *bd) stm32_fdt_fixup_cpu(blob, name); /* after cpu delete we can't trust the soc offsets anymore */ soc = fdt_path_offset(blob, "/soc"); - stm32_fdt_disable(blob, soc, STM32_FDCAN_BASE, "can", name); - /* fall through */ + stm32_fdt_disable(blob, soc, STM32MP15_FDCAN_BASE, "can", name); + fallthrough; case CPU_STM32MP153Fxx: case CPU_STM32MP153Dxx: case CPU_STM32MP153Cxx: case CPU_STM32MP153Axx: - stm32_fdt_disable(blob, soc, STM32_GPU_BASE, "gpu", name); - stm32_fdt_disable(blob, soc, STM32_DSI_BASE, "dsi", name); + stm32_fdt_disable(blob, soc, STM32MP15_GPU_BASE, "gpu", name); + stm32_fdt_disable(blob, soc, STM32MP15_DSI_BASE, "dsi", name); break; default: break; } - switch (cpu) { case CPU_STM32MP157Dxx: case CPU_STM32MP157Axx: @@ -304,13 +284,14 @@ int ft_system_setup(void *blob, struct bd_info *bd) case CPU_STM32MP153Axx: case CPU_STM32MP151Dxx: case CPU_STM32MP151Axx: - stm32_fdt_disable(blob, soc, STM32_CRYP1_BASE, "cryp", name); - stm32_fdt_disable(blob, soc, STM32_CRYP2_BASE, "cryp", name); + stm32_fdt_disable(blob, soc, STM32MP15_CRYP1_BASE, "cryp", + name); + stm32_fdt_disable(blob, soc, STM32MP15_CRYP2_BASE, "cryp", + name); break; default: break; } - switch (get_cpu_package()) { case STM32MP15_PKG_AA_LBGA448: pkg = STM32MP_PKG_AA; @@ -334,18 +315,48 @@ int ft_system_setup(void *blob, struct bd_info *bd) do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl", "st,package", pkg, false); } +} + +/* + * This function is called right before the kernel is booted. "blob" is the + * device tree that will be passed to the kernel. + */ +int ft_system_setup(void *blob, struct bd_info *bd) +{ + int ret = 0; + int soc; + u32 cpu; + char name[SOC_NAME_SIZE]; + + soc = fdt_path_offset(blob, "/soc"); + if (soc < 0) + return soc; + + if (CONFIG_IS_ENABLED(STM32_ETZPC)) { + ret = stm32_fdt_fixup_etzpc(blob, soc); + if (ret) + return ret; + } - /* - * TEMP: remove OP-TEE nodes in kernel device tree - * copied from U-Boot device tree by optee_copy_fdt_nodes - * when OP-TEE is not detected (probe failed) - * these OP-TEE nodes are present in <board>-u-boot.dtsi - * under CONFIG_STM32MP15x_STM32IMAGE only for compatibility - * when FIP is not used by TF-A - */ - if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) && - !tee_find_device(NULL, NULL, NULL, NULL)) - stm32_fdt_disable_optee(blob); + /* MPUs Part Numbers and name*/ + cpu = get_cpu_type(); + get_soc_name(name); + + if (IS_ENABLED(CONFIG_STM32MP15x)) { + stm32mp15_fdt_fixup(blob, soc, cpu, name); + + /* + * TEMP: remove OP-TEE nodes in kernel device tree + * copied from U-Boot device tree by optee_copy_fdt_nodes + * when OP-TEE is not detected (probe failed) + * these OP-TEE nodes are present in <board>-u-boot.dtsi + * under CONFIG_STM32MP15x_STM32IMAGE only for compatibility + * when FIP is not used by TF-A + */ + if (CONFIG_IS_ENABLED(STM32MP15x_STM32IMAGE) && + !tee_find_device(NULL, NULL, NULL, NULL)) + stm32_fdt_disable_optee(blob); + } return ret; } -- 2.25.1

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[PATCH 00/16] stm32mp: add STM32MP13x support
by Patrick Delaunay 17 Jun '22

17 Jun '22

Add the minimal support of the new STM32MP13x in mach-stm32mp to allow boot from SD Card. STM32MP13x is a single Cortex-A7 MPU aimed at various applications. The discovery board is supported with stm32mp13_defconfig and the device tree stm32mp135f-dk.dts. The supported boot sequence is: - TF-A BL2 - OP-TEE - U-Boot - Linux Kernel The console over UART and boot from SD Card is functional with this serie. The RCC driver, with support of reset and clock, is not yet provided today and the SCMI is not yet activated in device tree as in Linux kernel. Patrick Delaunay (16): ARM: dts: stm32: add STM32MP13 SoCs support configs: stm32mp1: move SUPPORT_SPL in STM32MP15x arm: stm32mp: move the get_otp helper function in bsec arm: stm32mp: move code for STM32MP15x arm: stm32mp: add choice for STM32MP SOC family arm: stm32mp: add sub config Kconfig.15x arm: stm32mp: add CONFIG_STM32MP15_PWR arm: stm32mp: add support of STM32MP13x arm: stm32mp: support 2 MAC address for STM32MP13 pinctrl: stm32: add support of STM32MP135 board: stm32pm1: add stm32mp13 board support ram: stm32mp1: add support of STM32MP13x mmc: stm32_sdmmc2: make reset property optional arm: dts: stm32mp: add stm32mp13 device tree for U-Boot configs: add stm32mp13 defconfig doc: st: stm32mp1: add STM32MP13x support arch/arm/Kconfig | 1 - arch/arm/dts/Makefile | 3 + arch/arm/dts/stm32mp13-pinctrl.dtsi | 123 ++++++ arch/arm/dts/stm32mp13-u-boot.dtsi | 91 ++++ arch/arm/dts/stm32mp131.dtsi | 358 ++++++++++++++++ arch/arm/dts/stm32mp133.dtsi | 37 ++ arch/arm/dts/stm32mp135.dtsi | 12 + arch/arm/dts/stm32mp135f-dk-u-boot.dtsi | 30 ++ arch/arm/dts/stm32mp135f-dk.dts | 57 +++ arch/arm/dts/stm32mp13xc.dtsi | 17 + arch/arm/dts/stm32mp13xf.dtsi | 17 + arch/arm/mach-stm32mp/Kconfig | 146 ++----- arch/arm/mach-stm32mp/Kconfig.13x | 57 +++ arch/arm/mach-stm32mp/Kconfig.15x | 135 ++++++ arch/arm/mach-stm32mp/Makefile | 5 +- arch/arm/mach-stm32mp/bsec.c | 17 + arch/arm/mach-stm32mp/cpu.c | 392 ++---------------- arch/arm/mach-stm32mp/fdt.c | 11 +- arch/arm/mach-stm32mp/include/mach/stm32.h | 26 ++ .../arm/mach-stm32mp/include/mach/sys_proto.h | 34 +- arch/arm/mach-stm32mp/spl.c | 1 + arch/arm/mach-stm32mp/stm32mp13x.c | 135 ++++++ arch/arm/mach-stm32mp/stm32mp15x.c | 350 ++++++++++++++++ board/st/stm32mp1/Kconfig | 15 + board/st/stm32mp1/MAINTAINERS | 4 + board/st/stm32mp1/stm32mp1.c | 27 +- configs/stm32mp13_defconfig | 54 +++ configs/stm32mp15_basic_defconfig | 6 +- configs/stm32mp15_defconfig | 6 +- configs/stm32mp15_trusted_defconfig | 8 +- doc/board/st/stm32mp1.rst | 181 +++++--- .../memory-controllers/st,stm32mp1-ddr.txt | 49 ++- drivers/mmc/stm32_sdmmc2.c | 14 +- drivers/pinctrl/pinctrl_stm32.c | 1 + drivers/ram/stm32mp1/stm32mp1_ram.c | 28 +- include/configs/stm32mp13_common.h | 106 +++++ include/configs/stm32mp13_st_common.h | 17 + include/configs/stm32mp15_common.h | 4 +- 38 files changed, 1992 insertions(+), 583 deletions(-) create mode 100644 arch/arm/dts/stm32mp13-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp13-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp131.dtsi create mode 100644 arch/arm/dts/stm32mp133.dtsi create mode 100644 arch/arm/dts/stm32mp135.dtsi create mode 100644 arch/arm/dts/stm32mp135f-dk-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp135f-dk.dts create mode 100644 arch/arm/dts/stm32mp13xc.dtsi create mode 100644 arch/arm/dts/stm32mp13xf.dtsi create mode 100644 arch/arm/mach-stm32mp/Kconfig.13x create mode 100644 arch/arm/mach-stm32mp/Kconfig.15x create mode 100644 arch/arm/mach-stm32mp/stm32mp13x.c create mode 100644 arch/arm/mach-stm32mp/stm32mp15x.c create mode 100644 configs/stm32mp13_defconfig create mode 100644 include/configs/stm32mp13_common.h create mode 100644 include/configs/stm32mp13_st_common.h -- 2.25.1

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[PATCH 0/4] mmc: add support for bcm63158
by Philippe Reynes 17 Jun '22

17 Jun '22

This serie adds the support of mmc for bcm63158. The first commit adds a driver that support sdhci on bcm63158. The two next commits add support of mmc in the device tree, and the last one enables the support of mmc and gpt for the reference board bcm963158. Philippe Reynes (4): drivers: mmc: bcm63158_sdhci: initial support arch: arm: dts: bcm63158.dtsi: add mmc support arch: arm: dts: bcm963158.dts: enable sdhci support configs: bcm963158_ram_defconfig: enable mmc and gpt support arch/arm/dts/bcm63158.dtsi | 9 ++ arch/arm/dts/bcm963158.dts | 4 + configs/bcm963158_ram_defconfig | 8 +- drivers/mmc/Kconfig | 12 +++ drivers/mmc/Makefile | 1 + drivers/mmc/bcm63158_sdhci.c | 153 ++++++++++++++++++++++++++++++++ 6 files changed, 184 insertions(+), 3 deletions(-) create mode 100644 drivers/mmc/bcm63158_sdhci.c -- 2.25.1

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[PATCH v3 0/9] spl: Use common function for loading/parsing images
by Sean Anderson 16 Jun '22

16 Jun '22

This series adds support for loading all image types (Legacy, FIT (with and without LOAD_FIT_FULL), and i.MX) to the MMC, SPI, NOR, NET, FAT, and EXT load methods. It does this by introducing a helper function which handles the minutiae of invoking the proper parsing function, and reading the rest of the image. Hopefully, this will make it easier for load methods to support all image types that U-Boot supports, without having undocumented unsupported image types. I applied this to several loaders which were invoking spl_load_simple_fit and/or spl_parse_image_header, but I did not use it with others (e.g. DFU/RAM) which had complications in the mix. Here's some bloat-o-meter for j7200_evm_a72_defconfig with ext4 support enabled: add/remove: 1/0 grow/shrink: 2/4 up/down: 224/-236 (-12) Function old new delta spl_load - 176 +176 spl_fit_read 60 104 +44 spl_load_image_ext 364 368 +4 spl_nor_load_image 120 108 -12 spl_spi_load_image 280 228 -52 spl_load_image_fat 320 264 -56 spl_mmc_load 716 600 -116 Total: Before=264556, After=264544, chg -0.00% ext4 support is +48 bytes, because the original image support was so bare-bones (just legacy/raw images). For most boards with a few load methods (where one of them isn't ext4), this series should be no bloat or a net negative. However, in the worst case this series will add 150-180 bytes. I have only tested EXT and MMC raw loaders. Please try booting your favorite board with NOR/SPI flash or SPI falcon mode. Changes in v3: - Fix using ffs instead of fls - Fix using not initializing bl_len when info->filename was NULL - Fix failing on success Changes in v2: - Use reverse-xmas-tree style for locals in spl_simple_read. This is not complete, since overhead depends on bl_mask. - Convert semihosting as well - Consolidate spi_load_image_os into spl_spi_load_image Sean Anderson (9): spl: Add generic spl_load function spl: Convert ext to use spl_load spl: Convert fat to spl_load spl: Convert mmc to spl_load spl: Convert net to spl_load spl: Convert nor to spl_load spl: Convert semihosting to spl_load spl: Convert spi to spl_load spl: spi: Consolidate spi_load_image_os into spl_spi_load_image common/spl/spl.c | 68 ++++++++++++++++++ common/spl/spl_ext.c | 24 +++++-- common/spl/spl_fat.c | 40 +++-------- common/spl/spl_mmc.c | 73 ++----------------- common/spl/spl_net.c | 24 ++----- common/spl/spl_nor.c | 35 ++-------- common/spl/spl_semihosting.c | 39 +++++------ common/spl/spl_spi.c | 131 ++++++++++------------------------- include/spl.h | 30 +++++++- 9 files changed, 193 insertions(+), 271 deletions(-) -- 2.35.1.1320.gc452695387.dirty

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[PATCH 1/2] usb: gadget: Add a config option to set the SPL product ID
by Alban Bedel 16 Jun '22

16 Jun '22

It might be desirable to have a different product ID for the SPL gadget. Several boards use dubious hack to achieve this like adding an hardcoded offset to the configurable main product ID. Add a new config option to set the product ID to use in the SPL and use it in the ethernet and download gadgets. Signed-off-by: Alban Bedel <alban.bedel(a)aerq.com> --- common/spl/Kconfig | 6 ++++++ drivers/usb/gadget/ether.c | 2 +- drivers/usb/gadget/g_dnl.c | 2 +- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index ac61b25a0660..196f3cfc5558 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1182,6 +1182,12 @@ config SPL_USB_GADGET if SPL_USB_GADGET +config SPL_USB_GADGET_PRODUCT_NUM + hex "Product ID of the SPL USB device" + default 0x0 + help + Product ID of the USB device emulated in SPL, reported to the host device. + config SPL_USB_ETHER bool "Support USB Ethernet drivers" depends on SPL_NET diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c index 430732865723..18195d3ee19b 100644 --- a/drivers/usb/gadget/ether.c +++ b/drivers/usb/gadget/ether.c @@ -2078,7 +2078,7 @@ static int eth_bind(struct usb_gadget *gadget) device_desc.idVendor = __constant_cpu_to_le16(CONFIG_USB_GADGET_VENDOR_NUM); device_desc.idProduct = - __constant_cpu_to_le16(CONFIG_USB_GADGET_PRODUCT_NUM); + __constant_cpu_to_le16(CONFIG_VAL(USB_GADGET_PRODUCT_NUM)); #else device_desc.idVendor = __constant_cpu_to_le16(RNDIS_VENDOR_NUM); diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c index afb7b74f3057..85297cc0e501 100644 --- a/drivers/usb/gadget/g_dnl.c +++ b/drivers/usb/gadget/g_dnl.c @@ -63,7 +63,7 @@ static struct usb_device_descriptor device_desc = { .bDeviceSubClass = 0, /*0x02:CDC-modem , 0x00:CDC-serial*/ .idVendor = __constant_cpu_to_le16(CONFIG_USB_GADGET_VENDOR_NUM), - .idProduct = __constant_cpu_to_le16(CONFIG_USB_GADGET_PRODUCT_NUM), + .idProduct = __constant_cpu_to_le16(CONFIG_VAL(USB_GADGET_PRODUCT_NUM)), /* .iProduct = DYNAMIC */ /* .iSerialNumber = DYNAMIC */ .bNumConfigurations = 1, -- 2.32.0

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[PATCH] imx: spl: Default to SPD when booting from USB serial download
by Alban Bedel 16 Jun '22

16 Jun '22

On the iMX platforms the USB boot is in fact boot from USB serial download and not from a USB mass storage. So returning BOOT_DEVICE_USB typically doesn't make sense as USB SPD is then used to continue booting, for this we need to return BOOT_DEVICE_BOARD. Still return BOOT_DEVICE_USB when USB mass storage support has been built in the SPL. With USB-C on both side, the programmer could switch back to device mode and use the exposed mass storage device after the serial download finished. Signed-off-by: Alban Bedel <alban.bedel(a)aerq.com> --- arch/arm/mach-imx/spl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 64ca29677212..2c2b2b126ad7 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -177,7 +177,8 @@ u32 spl_boot_device(void) case QSPI_BOOT: return BOOT_DEVICE_NOR; case USB_BOOT: - return BOOT_DEVICE_USB; + return IS_ENABLED(CONFIG_SPL_USB_STORAGE) ? + BOOT_DEVICE_USB : BOOT_DEVICE_BOARD; default: return BOOT_DEVICE_NONE; } -- 2.32.0

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[PATCH v2 0/2] usb: dwc3: Fix build without driver model
by Alban Bedel 16 Jun '22

16 Jun '22

Hi everyone, Platform with DWC3 that need USB support in the SPL might not be able to use the driver model there while the main u-boot is using driver model. This series allow building with such a configuration, it first fix 2 warnings when the core is built without driver model and then fix the SPL linking when one of the glue driver is enabled for the main u-boot. Changelog: v2: Use __maybe_unused instead of an #ifdef Alban Bedel (2): usb: dwc3: core: fix warnings when building without driver model usb: dwc3: Don't build DM drivers in SPL unless DM USB is available drivers/usb/dwc3/Makefile | 9 ++++++--- drivers/usb/dwc3/core.c | 5 ++--- 2 files changed, 8 insertions(+), 6 deletions(-) -- 2.32.0

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[PATCH] ddr:altera:soc64: Integer fix overflow that caused DDR size mismatched
by dinesh.maniyam＠intel.com 16 Jun '22

16 Jun '22

From: Dinesh Maniyam <dinesh.maniyam(a)intel.com> Convert the constant integer to 'phys_size_t' to avoid overflow when calculating the SDRAM size. Signed-off-by: Chee Hong Ang <chee.hong.ang(a)intel.com> Signed-off-by: Dinesh Maniyam <dinesh.maniyam(a)intel.com> --- drivers/ddr/altera/sdram_soc64.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index d6baac2410..1f479c514d 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -239,7 +239,8 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat *plat) { u32 dramaddrw = hmc_readl(plat, DRAMADDRW); - phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + + phys_size_t size = (phys_size_t)1 << + (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + -- 2.26.2

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[PATCH] arm: dts: socfpga: stratix10: Add freeze controller node
by dinesh.maniyam＠intel.com 16 Jun '22

16 Jun '22

From: Dinesh Maniyam <dinesh.maniyam(a)intel.com> The freeze controller is required for FPGA partial reconfig. This node is disable on default. Enable this node via u-boot fdt command when needed. Signed-off-by: Yau Wai Gan <yau.wai.gan(a)intel.com> Signed-off-by: Dinesh Maniyam <dinesh.maniyam(a)intel.com> --- arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi index 61df425f14..75a29045da 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_stratix10_socdk-u-boot.dtsi @@ -2,7 +2,7 @@ /* * U-Boot additions * - * Copyright (C) 2019-2020 Intel Corporation <www.intel.com> + * Copyright (C) 2019-2022 Intel Corporation <www.intel.com> */ #include "socfpga_stratix10-u-boot.dtsi" @@ -10,6 +10,15 @@ /{ aliases { spi0 = &qspi; + freeze_br0 = &freeze_controller; + }; + + soc { + freeze_controller: freeze_controller@f9000450 { + compatible = "altr,freeze-bridge-controller"; + reg = <0xf9000450 0x00000010>; + status = "disabled"; + }; }; }; -- 2.25.1

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