March 2022 - U-Boot

[PATCH v3 0/4] Add a clock driver for the imx8mq
by Angus Ainslie 14 Mar '22

14 Mar '22

This is a DM clock driver for the imx8mq based on the linux kernel driver and the u-boot imx8mm clock driver. It also removes some code duplication in the imx8m[nmp] clock drivers. Changes since v2: Added kernel commit IDs Re-factored rate table code to remove duplication Remove duplicate code by creating a common clk-imx8m Changes since v1: More verbose clock driver description Added forgotten dt-bindings Synced PLL frequencies with mainline kernel Angus Ainslie (4): dt-bindings: imx8mq-clock: add mainline definitions clk: imx8mq: Add a clock driver for the imx8mq clk: imx8m: reduce rate table duplication clk: imx8m: remove code duplication drivers/clk/imx/Kconfig | 16 + drivers/clk/imx/Makefile | 8 +- drivers/clk/imx/clk-imx8m.c | 108 ++++++ drivers/clk/imx/clk-imx8m.h | 12 + drivers/clk/imx/clk-imx8mm.c | 149 +------- drivers/clk/imx/clk-imx8mn.c | 149 +------- drivers/clk/imx/clk-imx8mp.c | 156 +------- drivers/clk/imx/clk-imx8mq.c | 441 +++++++++++++++++++++++ drivers/clk/imx/clk-pll14xx.c | 44 +++ drivers/clk/imx/clk.h | 21 ++ include/dt-bindings/clock/imx8mq-clock.h | 16 +- 11 files changed, 688 insertions(+), 432 deletions(-) create mode 100644 drivers/clk/imx/clk-imx8m.c create mode 100644 drivers/clk/imx/clk-imx8m.h create mode 100644 drivers/clk/imx/clk-imx8mq.c -- 2.25.1

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[PATCH] lib/acpi: Enable QEMU special cases for ARM
by Alexander Graf 14 Mar '22

14 Mar '22

With QEMU, we receive ACPI tables from the hypervisor rather than build them ourselves in U-Boot. That logic however hard codes the target to the x86 QEMU target, leaving ARM out on the fun. Let's add the ARM QEMU config as well to the ifdefs so that we can consume QEMU provided firmware tables there as well. Signed-off-by: Alexander Graf <agraf(a)csgraf.de> --- lib/acpi/Makefile | 2 ++ lib/acpi/acpi_writer.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/acpi/Makefile b/lib/acpi/Makefile index 956b5a0d72..66ba0e94ac 100644 --- a/lib/acpi/Makefile +++ b/lib/acpi/Makefile @@ -9,6 +9,7 @@ obj-y += acpi_writer.o # With QEMU the ACPI tables come from there, not from U-Boot ifndef CONFIG_QEMU +ifndef CONFIG_ARCH_QEMU obj-y += base.o obj-y += csrt.o obj-y += mcfg.o @@ -21,3 +22,4 @@ endif obj-y += facs.o obj-y += ssdt.o endif +endif diff --git a/lib/acpi/acpi_writer.c b/lib/acpi/acpi_writer.c index 946f90e8e7..9c252aa58d 100644 --- a/lib/acpi/acpi_writer.c +++ b/lib/acpi/acpi_writer.c @@ -48,7 +48,7 @@ int acpi_write_one(struct acpi_ctx *ctx, const struct acpi_writer *entry) return 0; } -#ifndef CONFIG_QEMU +#if !defined(CONFIG_QEMU) && !defined(CONFIG_ARCH_QEMU) static int acpi_write_all(struct acpi_ctx *ctx) { const struct acpi_writer *writer = -- 2.32.0

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[PATCH 0/2] J721E: Fix DFU in U-Boot
by Aswath Govindraju 14 Mar '22

14 Mar '22

The following series of patches fix USB DFU in U-Boot for J721e. Aswath Govindraju (2): phy: cadence: Sierra: Move the link operations from serdes phy to link device board: ti: j721e: evm.c: Fix the probing of in Sierra SerDes0 board/ti/j721e/evm.c | 28 ++++++----- drivers/phy/cadence/phy-cadence-sierra.c | 59 ++++++++---------------- 2 files changed, 33 insertions(+), 54 deletions(-) -- 2.17.1

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[PATCH v4 0/4] rockchip: sdhci: Fix reinit and add HS400 Enhanced Strobe support
by Alper Nebi Yasak 14 Mar '22

14 Mar '22

My rk3399-gru-kevin has some problems with the eMMC. The board can boot to U-Boot proper with the eMMC working at a low speed, but trying to reinitialize it with "mmc dev 0" or "mmc rescan" makes it unusable. If the HS400 mode is enabled, it times out while executing tuning and doesn't even start at a working state. To work around these errors, I had implemented support for the HS400 Enhanced Strobe mode as the first version of this series. I have also managed the fix the issue above (related to power-cycling the eMMC PHY), which exposed another one with this series: reinitialization at lower speeds fail if the ES bit is set. Since fixing that needed changes to this series I decided to send the previous fix as part of this instead of as an independent patch. To test, I'm building with the following configs enabled: +CONFIG_MMC_SPEED_MODE_SET=y [...] CONFIG_MMC_PWRSEQ=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y and running roughly: $ mmc rescan [0|1|3|10|11|12] $ mmc info $ mmc part $ load mmc 0:1 0xd0000000 256MiB.bin $ load mmc 0:1 0xd0000000 16MiB.bin $ load mmc 0:1 0xd0000000 8MiB.bin I used to test by loading different sizes from a very big file (~7GiB), but that's slower than reading fixed-size files for some reason I don't know. I thought loading full files would be a better test so I switched to those. Here's the differences in info and speeds I get with this: Mode | Bus Speed | Bus Width -----------------------+--------------+-------------- MMC Legacy | 25000000 | 8-bit MMC High Speed (26MHz) | 26000000 | 8-bit MMC High Speed (52MHz) | 52000000 | 8-bit HS200 (200MHz) | 200000000 | 8-bit HS400 (200MHz) | 200000000 | 8-bit DDR HS400ES (200MHz) | 200000000 | 8-bit DDR Mode | 256 MiB Load | 16 MiB Load | 8 MiB Load -----------------------+--------------+--------------+-------------- MMC Legacy | ~22.1 MiB/s | ~21.9 MiB/s | ~21.6 MiB/s MMC High Speed (26MHz) | ~22.1 MiB/s | ~21.9 MiB/s | ~21.6 MiB/s MMC High Speed (52MHz) | ~43.7 MiB/s | ~42.8 MiB/s | ~41.7 MiB/s HS200 (200MHz) | ~161.2 MiB/s | ~149.5 MiB/s | ~137.9 MiB/s HS400 (200MHz) | ~254.5 MiB/s | ~235.3 MiB/s | ~216.2 MiB/s HS400ES (200MHz) | ~254.7 MiB/s | ~238.8 MiB/s | ~216.2 MiB/s Hope I haven't missed anything. Enabling the configs above for each board is left to board maintainers as I can't test on those boards. As an aside, I want to further clean up this driver when I have the time (it's a weird combination of what could be three different drivers), but wanted to send this as it at least gets the driver to a working state. Changes in v4: - Add comment for SDHCI set_enhanced_strobe() operation - Add comment for Rockchip SDHCI set_control_reg() driver data op - Add comment for Rockchip SDHCI set_ios_post() driver data op - Add comment for Rockchip SDHCI set_enhanced_strobe() driver data op v3: https://patchwork.ozlabs.org/project/uboot/list/?series=281327&state=* Changes in v3: - Set DWCMSHC_CARD_IS_EMMC bit in rk3568_emmc_phy_init() v2: https://patchwork.ozlabs.org/project/uboot/list/?series=280494&state=* Changes in v2: - Add patch to fix PHY power cycling at higher speeds - Unset ES bit in rk3399 set_control_reg() to fix a reinit issue - Don't use unnecessary & for function pointer in ops struct - Rename rk3399_set_enhanced_strobe -> rk3399_sdhci_set_enhanced_strobe - Rename rk3568_set_enhanced_strobe -> rk3568_sdhci_set_enhanced_strobe - Let set_enhanced_strobe() unset the ES bit if mode is not HS400_ES - Rewrote cover letter v1: https://patchwork.ozlabs.org/project/uboot/list/?series=269768&state=* Alper Nebi Yasak (4): mmc: sdhci: Add HS400 Enhanced Strobe support rockchip: sdhci: Fix RK3399 eMMC PHY power cycling rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3399 rockchip: sdhci: Add HS400 Enhanced Strobe support for RK3568 drivers/mmc/rockchip_sdhci.c | 171 +++++++++++++++++++++++++++++++++-- drivers/mmc/sdhci.c | 18 ++++ include/sdhci.h | 12 +++ 3 files changed, 191 insertions(+), 10 deletions(-) -- 2.34.1

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Please pull u-boot-marvell/master
by Stefan Roese 14 Mar '22

14 Mar '22

Hi Tom, please pull the next batch of Marvell MVEBU / kwboot related fixes: ---------------------------------------------------------------- - kwboot: Misc minor improvement and fixes, e.g. mix of arguments (Pali) - PCI: a37xx: Remap IO space to bus address 0x0 (Pali) ---------------------------------------------------------------- Here the Azure build, without any issues: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=165&view=results Thanks, Stefan The following changes since commit c96137000e4cf486dcb164fd67a1a0b5b2fb99c6: Merge tag 'efi-2022-04-rc3-2' of https://source.denx.de/u-boot/custodians/u-boot-efi (2022-03-13 08:18:17 -0400) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-marvell.git for you to fetch changes up to 037bb6e2ca7c1e2371056c8b61b00842d25ea9f2: arm: a37xx: Remap IO space to bus address 0x0 (2022-03-14 14:04:18 +0100) ---------------------------------------------------------------- Pali Rohár (4): tools: kwboot: Allow to specify custom baudrate only in supported operations tools: kwboot: Check if baudrate value is supported before sending image tools: kwboot: Allow to mix positional arguments with option -b arm: a37xx: Remap IO space to bus address 0x0 arch/arm/dts/armada-3720-turris-mox.dts | 7 ++++++- arch/arm/dts/armada-37xx.dtsi | 2 +- tools/kwboot.c | 36 +++++++++++++++++++++++++++++---- 3 files changed, 39 insertions(+), 6 deletions(-)

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Please pull u-boot-x86
by Bin Meng 14 Mar '22

14 Mar '22

Hi Tom, This PR includes the following x86 changes for v2022.04: - Trivial fixes for x86 Azure results: PASS https://dev.azure.com/bmeng/GitHub/_build/results?buildId=463&view=results The following changes since commit c96137000e4cf486dcb164fd67a1a0b5b2fb99c6: Merge tag 'efi-2022-04-rc3-2' of https://source.denx.de/u-boot/custodians/u-boot-efi (2022-03-13 08:18:17 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-x86 for you to fetch changes up to 92a3e67ee9b0e1b2294a3d16e851b83440de2a1f: x86: Correct the coreboot header file in MAINTAINERS (2022-03-14 15:20:40 +0800) ---------------------------------------------------------------- Simon Glass (2): x86: Add an enum name for the GNVS firmware type x86: Correct the coreboot header file in MAINTAINERS arch/x86/include/asm/intel_gnvs.h | 8 +++++++- board/coreboot/coreboot/MAINTAINERS | 4 ++-- 2 files changed, 9 insertions(+), 3 deletions(-) Regards, Bin

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[PATCH 00/14] Add support for NVMEM API
by Sean Anderson 14 Mar '22

14 Mar '22

This adds support for the nvmem-cells properties cropping up in manyb device trees. This is an easy way to load configuration, version information, or calibration data from a non-volatile memory source. For more information, refer to patch 6 ("misc: Add support for nvmem cells"). Should this be implemented on top of/as part of syscon/regmap? In Linux, all nvmem devices must also implement regmap support, making nvmem a subset of regmap drivers. There are certainly similarities, but I don't know if we want to make this depend on regmap. For the moment I have only added some integration tests using the ethernet addresses. This hits the main code paths (looking up nvmem cells) but doesn't test writing. I can add a few stand-alone tests if desired. The patches are structured in the following manner: 1-5: These are general cleanups, and may be applied independently of the rest of the series. 6-10: Add NVMEM support 11-14: Support reading ethernet addresses using the NVMEM API and add some tests. Sean Anderson (14): sandbox: net: Remove fake-host-hwaddr sandbox: Remove eth2addr from environment test: eth: Add test for ethernet addresses sandbox: Move some mac addresses to device tree misc: i2c_eeprom: Make i2c_eeprom_write use a const buf misc: Add support for nvmem cells sandbox: Enable NVMEM rtc: Implement nvmem interface misc: i2c_eeprom: Implement nvmem interface misc: Implement nvmem interface net: Add support for reading mac addresses from nvmem cells test: Load mac address with i2c eeprom test: Load mac address using RTC test: Load mac address using misc device MAINTAINERS | 7 ++ arch/sandbox/dts/sandbox.dts | 1 - arch/sandbox/dts/sandbox64.dts | 1 - arch/sandbox/dts/test.dts | 29 ++++- board/sandbox/sandbox.env | 4 - configs/sandbox64_defconfig | 1 + configs/sandbox_defconfig | 1 + configs/sandbox_flattree_defconfig | 1 + configs/sandbox_noinst_defconfig | 1 + configs/sandbox_spl_defconfig | 1 + doc/api/index.rst | 1 + doc/api/nvmem.rst | 7 ++ drivers/misc/Kconfig | 16 +++ drivers/misc/Makefile | 1 + drivers/misc/i2c_eeprom.c | 22 +++- drivers/misc/i2c_eeprom_emul.c | 4 + drivers/misc/misc-uclass.c | 31 +++++ drivers/misc/misc_sandbox.c | 3 + drivers/misc/nvmem.c | 109 +++++++++++++++++ drivers/net/sandbox.c | 10 +- drivers/rtc/i2c_rtc_emul.c | 10 ++ drivers/rtc/rtc-uclass.c | 19 +++ include/i2c_eeprom.h | 3 +- include/nvmem.h | 185 +++++++++++++++++++++++++++++ net/eth-uclass.c | 13 +- test/dm/eth.c | 28 +++++ 26 files changed, 484 insertions(+), 25 deletions(-) create mode 100644 doc/api/nvmem.rst create mode 100644 drivers/misc/nvmem.c create mode 100644 include/nvmem.h -- 2.25.1

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[PATCH] arm: a37xx: Remap IO space to bus address 0x0
by Pali Rohár 14 Mar '22

14 Mar '22

Remap PCI I/O space to the bus address 0x0 in the Armada 37xx device-tree in order to support legacy I/O port based cards which have hardcoded I/O ports in low address space. Some legacy PCI I/O based cards do not support 32-bit I/O addressing. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- Same change was sent to linux kernel: https://lore.kernel.org/linux-arm-kernel/20220304163027.29357-1-pali@kernel… --- arch/arm/dts/armada-3720-turris-mox.dts | 7 ++++++- arch/arm/dts/armada-37xx.dtsi | 2 +- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/armada-3720-turris-mox.dts b/arch/arm/dts/armada-3720-turris-mox.dts index 1fc4a30d03e7..595b4b5abba0 100644 --- a/arch/arm/dts/armada-3720-turris-mox.dts +++ b/arch/arm/dts/armada-3720-turris-mox.dts @@ -139,7 +139,9 @@ /* * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and - * 2 size cells and also expects that the second range starts at 16 MB offset. If these + * 2 size cells and also expects that the second range starts at 16 MB offset. Also it + * expects that first range uses same address for PCI (child) and CPU (parent) cells (so + * no remapping) and that this address is the lowest from all specified ranges. If these * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window * for IO and the rest 112 MB (64+32+16) for MEM. Controller supports 32-bit IO mapping. @@ -148,6 +150,9 @@ * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff4908… * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc… * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591eb… + * Bug related to requirement of same child and parent addresses for first range is fixed + * in U-Boot version 2022.04 by following commit: + * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5… */ #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi index 9fa6457facb8..0bb4f607630a 100644 --- a/arch/arm/dts/armada-37xx.dtsi +++ b/arch/arm/dts/armada-37xx.dtsi @@ -499,7 +499,7 @@ * (totaling 127 MiB) for MEM. */ ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */ - 0x81000000 0 0xeff00000 0 0xeff00000 0 0x00100000>; /* Port 0 IO*/ + 0x81000000 0 0x00000000 0 0xeff00000 0 0x00100000>; /* Port 0 IO */ interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc 0>, <0 0 0 2 &pcie_intc 1>, -- 2.20.1

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[PATCH v2 1/3] tools: kwboot: Allow to specify custom baudrate only in supported operations
by Pali Rohár 14 Mar '22

14 Mar '22

Custom baudrate different than 115200 may be specified only when kwboot is not going to send boot/debug message pattern or when it is going to send boot message pattern with image file (in which case baudrate change happens after sending kwbimage header). BootROM detects boot/debug message pattern only at baudrate 115200. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- tools/kwboot.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/tools/kwboot.c b/tools/kwboot.c index 69d1be0f4823..986f27c2012a 100644 --- a/tools/kwboot.c +++ b/tools/kwboot.c @@ -2133,6 +2133,12 @@ main(int argc, char **argv) if (optind != argc) goto usage; + /* boot and debug message use baudrate 115200 */ + if (((bootmsg && !imgpath) || debugmsg) && baudrate != 115200) { + fprintf(stderr, "Baudrate other than 115200 cannot be used for this operation.\n"); + goto usage; + } + tty = kwboot_open_tty(ttypath, imgpath ? 115200 : baudrate); if (tty < 0) { perror(ttypath); -- 2.20.1

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[PATCH] arm64: zynqmp: Fix i2c addresses for zynqmp-p-a2197
by Michal Simek 14 Mar '22

14 Mar '22

After double checking some i2c addresses are not correct. It is visible from i2c dump ZynqMP> i2c bus Bus 3: i2c@ff020000 74: i2c-mux@74, offset len 1, flags 0 Bus 5: i2c@ff020000->i2c-mux@74->i2c@0 Bus 6: i2c@ff020000->i2c-mux@74->i2c@2 Bus 7: i2c@ff020000->i2c-mux@74->i2c@1 Bus 8: i2c@ff020000->i2c-mux@74->i2c@3 Bus 4: i2c@ff030000 (active 4) 74: i2c-mux@74, offset len 1, flags 0 Bus 9: i2c@ff030000->i2c-mux@74->i2c@0 Bus 10: i2c@ff030000->i2c-mux@74->i2c@3 Bus 11: i2c@ff030000->i2c-mux@74->i2c@4 Bus 12: i2c@ff030000->i2c-mux@74->i2c@5 (active 12) 51: generic_51, offset len 1, flags 0 60: generic_60, offset len 1, flags 0 74: generic_74, offset len 1, flags 0 Bus 13: i2c@ff030000->i2c-mux@74->i2c@6 (active 13) 51: generic_51, offset len 1, flags 0 5d: generic_5d, offset len 1, flags 0 74: generic_74, offset len 1, flags 0 ZynqMP> i2c dev 4 Setting bus to 4 ZynqMP> i2c mw 74 0 18 ZynqMP> i2c probe Valid chip addresses: 18 36 37 50 51 60 74 ZynqMP> i2c mw 74 0 20 ZynqMP> i2c probe Valid chip addresses: 51 60 74 where it is clear that si570 (u5) is at 0x60 address and 8t49n240 (u39) is also at address 0x60 based on log above. i2c address 0x74 is i2c mux and 0x51 is eeprom. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynqmp-p-a2197-00-revA.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts index 5d21795de9d0..b3fe42faeee8 100644 --- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts @@ -511,10 +511,10 @@ #address-cells = <1>; #size-cells = <0>; reg = <6>; - si570_hsdp: clock-generator@5d { /* u5 */ + si570_hsdp: clock-generator@60 { /* u5 */ #clock-cells = <0>; compatible = "silabs,si570"; - reg = <0x5d>; /* 570JAC000900DG */ + reg = <0x60>; /* 570JAC000900DG */ temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <156250000>; @@ -528,10 +528,10 @@ /* u36 0xd8 or 0xde - pcie clk buf - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ /* u37 0xd0 DNP - pcie clocking 1 - 9FGV1006BQ505LTGI - PCIe GEN 4 CLOCK GENERATOR FIXME - no linux driver */ /* u38 0xca - pcie clocking 2 - 9ZML1241EKILF PCIe GEN 4 CLOCK BUFFER FIXME - no driver */ - clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 - pcie clocking 3 */ + clock_8t49n287: clock-generator@60 { /* u39 8T49N240 - pcie clocking 3 */ #clock-cells = <1>; /* author David Cater <david.cater(a)idt.com>*/ compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */ - reg = <0xd8>; + reg = <0x60>; /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */ /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */ -- 2.35.1

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