March 2022 - U-Boot

[PATCH] mmc: dw_mmc: set host_caps mmc modes to equivalent and lower buswidth
by Jan Havran 16 Mar '22

16 Mar '22

dwmci_setup_cfg was clearing all modes except the mode equivalent to required bus width. Moreover, for buswidth = 1 was set the 4-bit mode. This sets host caps to all modes from 1-bit up to the required mode. Signed-off-by: Jan Havran <havran.jan(a)email.cz> --- drivers/mmc/dw_mmc.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 4232c5eb8c..9c139140e4 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -602,11 +602,13 @@ void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host, cfg->host_caps = host->caps; if (host->buswidth == 8) { - cfg->host_caps |= MMC_MODE_8BIT; - cfg->host_caps &= ~MMC_MODE_4BIT; - } else { - cfg->host_caps |= MMC_MODE_4BIT; + cfg->host_caps |= MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT; + } else if (host->buswidth == 4) { cfg->host_caps &= ~MMC_MODE_8BIT; + cfg->host_caps |= MMC_MODE_4BIT | MMC_MODE_1BIT; + } else { + cfg->host_caps &= ~MMC_MODE_8BIT & ~MMC_MODE_4BIT; + cfg->host_caps |= MMC_MODE_1BIT; } cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz; -- 2.35.1

2 1

[PATCH] mmc: xenon_sdhci: remove wait_dat0 SDHCI OP
by Robert Marko 16 Mar '22

16 Mar '22

Generic SDHCI driver received support for checking the busy status by polling the DAT[0] level instead of waiting for the worst MMC switch time. Unfortunately, it appears that this does not work for Xenon controllers despite being a part of the standard SDHCI registers and the Armada 3720 datasheet itself telling that BIT(20) is useful for detecting the DAT[0] busy signal. I have tried increasing the timeout value, but I have newer managed to catch DAT_LEVEL bits change from 0 at all. This issue appears to hit most if not all SoC-s supported by Xenon driver, at least A3720, A8040 and CN9130 have non working eMMC currently. So, until a better solution is found drop the wait_dat0 OP for Xenon. I was able to only test it on A3720, but it should work for others as well. Fixes: 40e6f52454fc ("drivers: mmc: Add wait_dat0 support for sdhci driver") Signed-off-by: Robert Marko <robert.marko(a)sartura.hr> --- drivers/mmc/xenon_sdhci.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/xenon_sdhci.c b/drivers/mmc/xenon_sdhci.c index e292f2903d..2f8805096c 100644 --- a/drivers/mmc/xenon_sdhci.c +++ b/drivers/mmc/xenon_sdhci.c @@ -439,6 +439,8 @@ static const struct sdhci_ops xenon_sdhci_ops = { .set_ios_post = xenon_sdhci_set_ios_post }; +static struct dm_mmc_ops xenon_mmc_ops; + static int xenon_sdhci_probe(struct udevice *dev) { struct xenon_sdhci_plat *plat = dev_get_plat(dev); @@ -452,6 +454,9 @@ static int xenon_sdhci_probe(struct udevice *dev) host->mmc->dev = dev; upriv->mmc = host->mmc; + xenon_mmc_ops = sdhci_ops; + xenon_mmc_ops.wait_dat0 = NULL; + /* Set quirks */ host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_32BIT_DMA_ADDR; @@ -568,7 +573,7 @@ U_BOOT_DRIVER(xenon_sdhci_drv) = { .id = UCLASS_MMC, .of_match = xenon_sdhci_ids, .of_to_plat = xenon_sdhci_of_to_plat, - .ops = &sdhci_ops, + .ops = &xenon_mmc_ops, .bind = xenon_sdhci_bind, .probe = xenon_sdhci_probe, .remove = xenon_sdhci_remove, -- 2.35.1

6 8

[PATCH] efi_loader: Use sysreset instead of reset command
by Masami Hiramatsu 16 Mar '22

16 Mar '22

Use sysreset_walk_halt() directly from reset-after-capsule-on-disk feature to reboot (cold reset) machine instead of using reset command interface, since this is not a command. Signed-off-by: Masami Hiramatsu <masami.hiramatsu(a)linaro.org> --- lib/efi_loader/efi_capsule.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c index 613b531b82..35907ad0d2 100644 --- a/lib/efi_loader/efi_capsule.c +++ b/lib/efi_loader/efi_capsule.c @@ -1150,9 +1150,9 @@ efi_status_t efi_launch_capsules(void) * UEFI spec requires to reset system after complete processing capsule * update on the storage. */ - log_info("Reboot after firmware update"); + log_info("Reboot after firmware update.\n"); /* Cold reset is required for loading the new firmware. */ - do_reset(NULL, 0, 0, NULL); + sysreset_walk_halt(SYSRESET_COLD); hang(); /* not reach here */

3 6

[PATCH v3 1/6] rockchip: move ROCKCHIP_STIMER_BASE to Kconfig
by Johan Jonker 16 Mar '22

16 Mar '22

Move ROCKCHIP_STIMER_BASE to Kconfig. Signed-off-by: Johan Jonker <jbx6244(a)gmail.com> --- Changed V3: add ROCKCHIP_STIMER --- arch/arm/mach-rockchip/Kconfig | 22 ++++++++++++++++++++++ arch/arm/mach-rockchip/px30/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3036/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3128/Kconfig | 3 +++ arch/arm/mach-rockchip/rk322x/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3288/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3308/Kconfig | 10 ++++++---- arch/arm/mach-rockchip/rk3328/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3368/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3399/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3568/Kconfig | 3 +++ include/configs/px30_common.h | 1 - include/configs/rk3036_common.h | 1 - include/configs/rk3128_common.h | 1 - include/configs/rk322x_common.h | 1 - include/configs/rk3288_common.h | 1 - include/configs/rk3308_common.h | 1 - include/configs/rk3328_common.h | 1 - include/configs/rk3368_common.h | 1 - include/configs/rk3399_common.h | 1 - include/configs/rk3568_common.h | 1 - 21 files changed, 55 insertions(+), 14 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index da6871eb..7a624c64 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -343,6 +343,28 @@ config ROCKCHIP_BOOT_MODE_REG The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h) according to the value from this register. +config ROCKCHIP_STIMER + bool "Rockchip STIMER support" + default y + depends on (ROCKCHIP_PX30|| \ + ROCKCHIP_RK3036|| \ + ROCKCHIP_RK3128|| \ + ROCKCHIP_RK322X|| \ + ROCKCHIP_RK3288|| \ + ROCKCHIP_RK3308|| \ + ROCKCHIP_RK3328|| \ + ROCKCHIP_RK3368|| \ + ROCKCHIP_RK3399|| \ + ROCKCHIP_RK3568) + help + Enable Rockchip STIMER support. + +config ROCKCHIP_STIMER_BASE + hex "Rockchip secure timer base address" + depends on ROCKCHIP_STIMER + help + Rockchip secure timer base address. + config ROCKCHIP_SPL_RESERVE_IRAM hex "Size of IRAM reserved in SPL" default 0 diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index aa5cc471..42cc111b 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -30,6 +30,9 @@ config TARGET_PX30_CORE config ROCKCHIP_BOOT_MODE_REG default 0xff010200 +config ROCKCHIP_STIMER_BASE + default 0xff220020 + config SYS_SOC default "px30" diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig index b746795d..111531be 100644 --- a/arch/arm/mach-rockchip/rk3036/Kconfig +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -16,6 +16,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0x200081c8 +config ROCKCHIP_STIMER_BASE + default 0x200440a0 + config SYS_SOC default "rk3036" diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig b/arch/arm/mach-rockchip/rk3128/Kconfig index b867401c..9cc494eb 100644 --- a/arch/arm/mach-rockchip/rk3128/Kconfig +++ b/arch/arm/mach-rockchip/rk3128/Kconfig @@ -16,6 +16,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0x100a0038 +config ROCKCHIP_STIMER_BASE + default 0x200440a0 + config SYS_SOC default "rk3128" diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig index 6458cd55..058f848d 100644 --- a/arch/arm/mach-rockchip/rk322x/Kconfig +++ b/arch/arm/mach-rockchip/rk322x/Kconfig @@ -8,6 +8,9 @@ config TARGET_EVB_RK3229 config ROCKCHIP_BOOT_MODE_REG default 0x110005c8 +config ROCKCHIP_STIMER_BASE + default 0x110d0020 + config SYS_SOC default "rk322x" diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index f37b1bdf..dd8c7826 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -148,6 +148,9 @@ config ROCKCHIP_FAST_SPL config ROCKCHIP_BOOT_MODE_REG default 0xff730094 +config ROCKCHIP_STIMER_BASE + default 0xff810020 + config SYS_SOC default "rk3288" diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index 8fa536e1..194353e4 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -8,6 +8,12 @@ config TARGET_ROC_RK3308_CC bool "Firefly roc-rk3308-cc" select BOARD_LATE_INIT +config ROCKCHIP_BOOT_MODE_REG + default 0xff000500 + +config ROCKCHIP_STIMER_BASE + default 0xff1b00a0 + config SYS_SOC default "rk3308" @@ -17,10 +23,6 @@ config SYS_MALLOC_F_LEN config SPL_SERIAL default y -config ROCKCHIP_BOOT_MODE_REG - default 0xff000500 - - source "board/rockchip/evb_rk3308/Kconfig" source "board/firefly/firefly-rk3308/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index d13a1690..f6f1e06a 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -15,6 +15,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0xff1005c8 +config ROCKCHIP_STIMER_BASE + default 0xff1d0020 + config SYS_SOC default "rk3328" diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index 78eb96df..104db367 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -45,6 +45,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0xff738200 +config ROCKCHIP_STIMER_BASE + default 0xff830020 + config SYS_SOC default "rk3368" diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 17628f91..4bc15c1b 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -114,6 +114,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0xff320300 +config ROCKCHIP_STIMER_BASE + default 0xff8680a0 + config SYS_SOC default "rk3399" diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index 201c63c2..4e7c02cc 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -9,6 +9,9 @@ config TARGET_EVB_RK3568 config ROCKCHIP_BOOT_MODE_REG default 0xfdc20200 +config ROCKCHIP_STIMER_BASE + default 0xfdd1c020 + config SYS_SOC default "rk3568" diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 09923871..dc609013 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -12,7 +12,6 @@ #define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff220020 #define COUNTER_FREQUENCY 24000000 /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */ diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index b133d8ec..10cba727 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -10,7 +10,6 @@ #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_ARCH_TIMER #define CONFIG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 8b7a0bbb..71f66d57 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_ARCH_TIMER #define CONFIG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index a46b1ffe..aff24018 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ -#define CONFIG_ROCKCHIP_STIMER_BASE 0x110d0020 #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_ARCH_TIMER #define CONFIG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index abbb2739..c781bc7e 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020 #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_ARCH_TIMER #define CONFIG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 496f4628..edc535fe 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -16,7 +16,6 @@ #define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0 #define CONFIG_IRAM_BASE 0xfff80000 #define CONFIG_SYS_INIT_SP_ADDR 0x00800000 #define CONFIG_SPL_STACK 0x00400000 diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index c1e26a01..8a5f0c89 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -10,7 +10,6 @@ #define CONFIG_IRAM_BASE 0xff090000 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1d0020 #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_CBSIZE 1024 diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 8b239ca0..239296c1 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -15,7 +15,6 @@ #define SDRAM_MAX_SIZE 0xff000000 #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020 #define COUNTER_FREQUENCY 24000000 #define CONFIG_IRAM_BASE 0xff8c0000 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index ed72c8bb..4037dba5 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define COUNTER_FREQUENCY 24000000 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff8680a0 #define CONFIG_IRAM_BASE 0xff8c0000 diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index afe5050e..705c3454 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define COUNTER_FREQUENCY 24000000 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xfdd1c020 #define CONFIG_IRAM_BASE 0xfdcc0000 -- 2.20.1

5 18

[PATCH] rockchip: rk3328: enable USB mass storage on Renegade
by Leonidas-Panagiotis Papadakos 16 Mar '22

16 Mar '22

This is very useful to access the LibreComputer eMMC as removable storage from a PC (e.g. like so `ums 0 mmc 0`). It has been tested as working on my Renegade board. Signed-off-by: Leonidas P. Papadakos <papadakospan at gmail.com> --- configs/roc-cc-rk3328_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index cf04bbc768..e3e40a6d64 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -36,6 +36,7 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_SPL_OF_CONTROL=y -- 2.34.1

2 1

Submitting patches for QorIQ components
by Sean Anderson 16 Mar '22

16 Mar '22

Hi all, Where should patches for QorIQ components [1] go? I have some patches for meta-qoriq [2] and dce [3], but I can't figure out where to send them to. There is no mailing list in the READMEs, and there is no way to send pull requests like on the former github repos [4]. I tried emailing the most recent committers directly, but got no response. --Sean [1] https://source.codeaurora.org/external/qoriq/qoriq-components/ [2] https://source.codeaurora.org/external/qoriq/qoriq-components/meta-qoriq/ [3] https://source.codeaurora.org/external/qoriq/qoriq-components/dce/ [4] https://github.com/qoriq-open-source/meta-qoriq-demos

2 1

[PATCH] mtd: spi-nor: Parse SFDP Command Sequence to change to Octal DDR(8D-8D-8D) mode
by JaimeLiao 16 Mar '22

16 Mar '22

Parcing table of SFDP Command Sequence to change to Octal DDR(8D-8D-8D) mode(CSODDR) and following SPI protocol to judge opcode, address, dummy and data. Enabling Octal DDR mode when nor->octal_dtr_enable didn't hook. Signed-off-by: JaimeLiao <jaimeliao.tw(a)gmail.com> --- drivers/mtd/spi/spi-nor-core.c | 114 ++++++++++++++++++++++++++++++++- include/linux/mtd/spi-nor.h | 8 ++- 2 files changed, 120 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index d5d905fa5a..058dd8e889 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -63,6 +63,9 @@ struct sfdp_parameter_header { #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */ #define SFDP_SST_ID 0x01bf /* Manufacturer specific Table */ #define SFDP_PROFILE1_ID 0xff05 /* xSPI Profile 1.0 Table */ +#define SFDP_CSODDR_ID 0xff0a /* Command Sequences to Change to Octal + * DDR (8D-8D-8D) mode + */ #define SFDP_SIGNATURE 0x50444653U #define SFDP_JESD216_MAJOR 1 @@ -172,6 +175,11 @@ struct sfdp_header { #define PROFILE1_DWORD5_DUMMY_100MHZ GENMASK(11, 7) #define PROFILE1_DUMMY_DEFAULT 20 +/* Command Sequences to Change to Octal DDR (8D-8D-8D) mode */ +#define CSODDR_LENGTH_OF_CMD GENMASK(31, 24) +#define CSODDR_DWORD1_OF_CMD GENMASK(31, 0) +#define CSODDR_DWORD2_OF_CMD GENMASK(31, 0) + struct sfdp_bfpt { u32 dwords[BFPT_DWORD_MAX]; }; @@ -2434,6 +2442,49 @@ out: return ret; } +/** + * spi_nor_parse_csoddr() - Parse Command Sequences to Change to Octal DDR (8D-8D-8D) + * mode. + * @nor: pointer to a 'struct spi_nor' + * @csoddr_header: pointer to the 'struct sfdp_parameter_header' describing + * the CSODDR table length and version. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_parse_csoddr(struct spi_nor *nor, + const struct sfdp_parameter_header *csoddr_header) +{ + u32 *table, addr; + size_t len; + int ret, i; + + len = csoddr_header->length * sizeof(*table); + table = kmalloc(len, GFP_KERNEL); + if (!table) + return -ENOMEM; + + addr = SFDP_PARAM_HEADER_PTP(csoddr_header); + ret = spi_nor_read_sfdp(nor, addr, len, table); + if (ret) + goto out; + + /* Fix endianness of the table DWORDs. */ + for (i = 0; i < csoddr_header->length; i++) + table[i] = le32_to_cpu(table[i]); + + /* Each command sequence consists of 2DWORDs(8 bytes) */ + for(i = 0; i < csoddr_header->length/2; i++) { + if(FIELD_GET(CSODDR_LENGTH_OF_CMD, table[2*i])) { + memcpy(&nor->csoddr_cmd[i].cmd_byte[0], &table[2*i], 4); + memcpy(&nor->csoddr_cmd[i].cmd_byte[4], &table[2*i+1], 4); + } + } + +out: + kfree(table); + return ret; +} + /** * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters. * @nor: pointer to a 'struct spi_nor' @@ -2540,6 +2591,10 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor, err = spi_nor_parse_profile1(nor, param_header, params); break; + case SFDP_CSODDR_ID: + err = spi_nor_parse_csoddr(nor, param_header); + break; + default: break; } @@ -3489,6 +3544,63 @@ static struct spi_nor_fixups mt35xu512aba_fixups = { }; #endif /* CONFIG_SPI_FLASH_MT35XU */ +/** + * spi_nor_generall_octal_dtr_enable() - execute command sequence to enable octal dtr mode. + * @nor: pointer to a 'struct spi_nor' + * + * Command Sequence to change to Octal DTR mode is parcing from SFDP table. + * Executing commands to enable Octal DTR mode. + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_generall_octal_dtr_enable(struct spi_nor *nor) +{ + struct spi_mem_op op; + int ret, i; + u8 opcode, buf, word_buf[2]; + u32 addr; + + /* According SPI protocol for judging combination of commands */ + for(i = 0; i < MAX_COMMAND_SEQUENCE_DTR; i++) { + if(nor->csoddr_cmd[i].cmd_byte[3]) { + if(nor->csoddr_cmd[i].cmd_byte[3] == 1) { + opcode = nor->csoddr_cmd[i].cmd_byte[2]; + ret = nor->write_reg(nor, opcode, NULL, 0); + } else if(nor->csoddr_cmd[i].cmd_byte[3] == 2 ) { + opcode = nor->csoddr_cmd[i].cmd_byte[2]; + buf = nor->csoddr_cmd[i].cmd_byte[1]; + ret = nor->write_reg(nor, opcode, &buf, 1); + } else if(nor->csoddr_cmd[i].cmd_byte[3] == 3 ) { + opcode = nor->csoddr_cmd[i].cmd_byte[2]; + word_buf[0] = nor->csoddr_cmd[i].cmd_byte[1]; + word_buf[1] = nor->csoddr_cmd[i].cmd_byte[0]; + ret = nor->write_reg(nor, opcode, word_buf, 2); + } else if(nor->csoddr_cmd[i].cmd_byte[3] > 5) { + opcode = nor->csoddr_cmd[i].cmd_byte[2]; + addr = nor->csoddr_cmd[i].cmd_byte[1] << 24 | nor->csoddr_cmd[i].cmd_byte[0] << 16 | + nor->csoddr_cmd[i].cmd_byte[7] << 8 | nor->csoddr_cmd[i].cmd_byte[7]; + buf = nor->csoddr_cmd[i].cmd_byte[5]; + op = (struct spi_mem_op) + SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1), + SPI_MEM_OP_ADDR(4, addr, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, &buf, 1)); + + ret = spi_mem_exec_op(nor->spi, &op); + } + + if (ret) { + dev_err(nor->dev, "Failed to enable octal DTR mode\n"); + return ret; + } + } + } + + nor->reg_proto = SNOR_PROTO_8_8_8_DTR; + + return 0; +} + /** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed * @nor: pointer to a 'struct spi_nor' * @@ -3499,7 +3611,7 @@ static int spi_nor_octal_dtr_enable(struct spi_nor *nor) int ret; if (!nor->octal_dtr_enable) - return 0; + nor->octal_dtr_enable = spi_nor_generall_octal_dtr_enable; if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR && nor->write_proto == SNOR_PROTO_8_8_8_DTR)) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 7ddc4ba2bf..7c4b982bf3 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -261,7 +261,8 @@ static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto) return spi_nor_get_protocol_data_nbits(proto); } -#define SPI_NOR_MAX_CMD_SIZE 8 +#define SPI_NOR_MAX_CMD_SIZE 8 +#define MAX_COMMAND_SEQUENCE_DTR 4 enum spi_nor_ops { SPI_NOR_OPS_READ = 0, SPI_NOR_OPS_WRITE, @@ -375,6 +376,10 @@ struct spi_nor_pp_command { enum spi_nor_protocol proto; }; +struct csoddr { + u8 cmd_byte[8]; +}; + enum spi_nor_read_command_index { SNOR_CMD_READ, SNOR_CMD_READ_FAST, @@ -563,6 +568,7 @@ struct spi_nor { void *priv; /* Compatibility for spi_flash, remove once sf layer is merged with mtd */ const char *name; + struct csoddr csoddr_cmd[MAX_COMMAND_SEQUENCE_DTR]; u32 size; u32 sector_size; u32 erase_size; -- 2.17.1

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[PATCH] dm: Add docs to explain how to enable DM_SERIAL for a board
by Simon Glass 16 Mar '22

16 Mar '22

This is an attempt to cover the common cases found when enabling driver model for serial on a new board. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- doc/develop/driver-model/serial-howto.rst | 138 ++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/doc/develop/driver-model/serial-howto.rst b/doc/develop/driver-model/serial-howto.rst index 1469131124b..c64a562499b 100644 --- a/doc/develop/driver-model/serial-howto.rst +++ b/doc/develop/driver-model/serial-howto.rst @@ -44,3 +44,141 @@ this involves these steps: - build and get u-boot-dtb.bin so you can test it - Your drivers can now use device tree - For device tree in SPL, define CONFIG_SPL_OF_CONTROL + + +Converting boards to CONFIG_DM_SERIAL +------------------------------------- + +If your SoC has a serial driver that uses driver model (has U_BOOT_DRIVER() in +it) then you may still find that your board has not been converted. To convert +your board, enable the option and see if you can get it working. + +Firstly you will have a lot more success if you have a method of debugging your +board, such as a JTAG connection. Failing that the debug UART is useful, +although since you are trying to get the UART driver running, it will interfere +with your efforts eventually. + +Secondly, while the UART is a relatively simple peripheral, it may need quite a +few pieces to be up and running before it will work, such as the correct pin +muxing, clocks, power domains and possibly even GPIOs, if an external +transceiver is used. Look at other boards that use the same SoC, for clues as to +what is needed. + +Thirdly, when added tags, put them in a xxx-u-boot.dtsi file, where xxx is your +board name, or SoC name. There may already be a file for your SoC which contains +what you need. U-Boot automatically includes these files: see :ref:`dttweaks`. + +Here are some things you might need to consider: + +1. The serial driver itself needs to be present before relocation, so that the +U-Boot banner appears. Make sure it has a u-boot,pre-reloc tag in the device +tree, so that the serial driver is bound when U-Boot starts. + +For example, on iMX6:: + + lpuart3: serial@5a090000 { + compatible = "fsl,imx8qm-lpuart"; + ... + }; + +put this in your xxx-u-boot.dtsi file:: + + &lpuart3 { + u-boot,dm-pre-proper; + }; + +2. If your serial port requires a particular pinmux configuration, you may need +a pinctrl driver. This needs to have a u-boot,pre-reloc tag also. Take care that +any subnodes have the same tag, if they are needed to make the correct pinctrl +available. + +For example, on RK3288, the UART2 uses uart2_xfer:: + + uart2: serial@ff690000 { + ... + pinctrl-0 = <&uart2_xfer>; + }; + +which is defined as follows:: + + pinctrl: pinctrl { + compatible = "rockchip,rk3228-pinctrl"; + + uart2: uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_up>, + <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; + }; + + ... + }; + +This means you must make the uart2-xfer node available as well as all its +parents, so put this in your xxx-u-boot.dtsi file:: + + &pinctrl { + u-boot,dm-pre-reloc; + }; + + &uart2 { + u-boot,dm-pre-reloc; + }; + + &uart2_xfer { + u-boot,dm-pre-reloc; + }; + +3. The same applies to power domains. For example, if a particular power domain +must be enabled for the serial port to work, you need to ensure it is available +before relocation: + +For example, on iMX6, put this in your xxx-u-boot.dtsi file:: + + &pd_dma { + u-boot,dm-pre-proper; + }; + + &pd_dma_lpuart3 { + u-boot,dm-pre-proper; + }; + +4. The same applies to clocks, in the same way. Make sure that when your driver +requests a clock, typically with clk_get_by_index(), it is available. + + +Generally a failure to find a required device will cause an error which you can +catch, if you have the debug UART working. U-Boot outputs serial data to the +debug UART until the point where the real serial driver takes over. This point +is marked by gd->flags having the GD_FLG_SERIAL_READY flag set. This change +happens in serial_init() in serial-uclass.c so until that point the debug UART +is used. You can see the relevant code in putc() +, for example:: + + /* if we don't have a console yet, use the debug UART */ + if (IS_ENABLED(CONFIG_DEBUG_UART) && !(gd->flags & GD_FLG_SERIAL_READY)) { + printch(c); + return; + } + ... carries on to use the console / serial driver + +Note that in device_probe() the call to pinctrl_select_state() silently fails +if the pinctrl driver fails. You can add a temporary check there if needed. + +Why do we have all these tags? The problem is that before relocation we don't +want to bind all the drivers since memory is limited and the CPU may be running +at a slow speed. So many boards will fail to boot without this optimisation, or +may take a long time to start up (e.g. hundreds of milliseconds). The tags tell +U-Boot which drivers to bind. + +The good news is that this problem is normally solved by the SoC, so that any +boards that use it will work as normal. But in some cases there are multiple +UARTs or multiple pinmux options, which means that each board may need to do +some customisation. + +Serial in SPL +------------- + +A similar process is needed in SPL, but in this case the u-boot,dm-spl or +u-boot,dm-tpl tags are used. Add these in the same way as above, to ensure that +the SPL device tree contains the required nodes (see spl/u-boot-spl.dtb for +what it actually contains). -- 2.35.1.723.g4982287a31-goog

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[PULL] u-boot-usb/master
by Marek Vasut 15 Mar '22

15 Mar '22

Bugfix for dwc2 USB driver. The following changes since commit c96137000e4cf486dcb164fd67a1a0b5b2fb99c6: Merge tag 'efi-2022-04-rc3-2' of https://source.denx.de/u-boot/custodians/u-boot-efi (2022-03-13 08:18:17 -0400) are available in the Git repository at: git://source.denx.de/u-boot-usb.git master for you to fetch changes up to 2addee35f2da178bf858403f2e2cb20a59df734f: usb: dwc2: handle return code of dev_read_size() in of to, plat function (2022-03-14 12:31:12 +0100) ---------------------------------------------------------------- Wolfgang Grandegger (1): usb: dwc2: handle return code of dev_read_size() in of to, plat function drivers/usb/gadget/dwc2_udc_otg.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)

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[PATCH] doc: board: raspberrypi: Add documentation
by matthias.bgg＠kernel.org 15 Mar '22

15 Mar '22

From: Matthias Brugger <mbrugger(a)suse.com> Add documentation about the different configuration files for the RaspberryPi board family. Signed-off-by: Matthias Brugger <mbrugger(a)suse.com> --- doc/board/raspberrypi/index.rst | 10 +++++ doc/board/raspberrypi/raspberrypi.rst | 53 +++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) create mode 100644 doc/board/raspberrypi/index.rst create mode 100644 doc/board/raspberrypi/raspberrypi.rst diff --git a/doc/board/raspberrypi/index.rst b/doc/board/raspberrypi/index.rst new file mode 100644 index 0000000000..7a283d81af --- /dev/null +++ b/doc/board/raspberrypi/index.rst @@ -0,0 +1,10 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (C) 2022 Matthias Brugger <mbrugger(a)suse.com> + +Raspberry Pi +============ + +.. toctree:: + :maxdepth: 2 + + raspberrypi diff --git a/doc/board/raspberrypi/raspberrypi.rst b/doc/board/raspberrypi/raspberrypi.rst new file mode 100644 index 0000000000..219a780e15 --- /dev/null +++ b/doc/board/raspberrypi/raspberrypi.rst @@ -0,0 +1,53 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. Copyright (C) 2022 Matthias Brugger <mbrugger(a)suse.com> + +RASPBERRY PI +============ + +About this +---------- + +This document describes the information about Raspberry PI boards +and it's usage steps. + +Raspberry Pi boards +------------------- + +List of mainline supported Rasbperry Pi boards through the following configs: + +32-bits: +^^^^^^^^ + +* rpi_defconfig + - Raspberry Pi +* rpi_0_w_defconfig + - Raspberry Pi 1 + - Raspberry Pi zero +* rpi_2_defconfig + - Raspberry Pi 2 +* rpi_3_32b_defconfig + - Raspberry Pi 3b +* rpi_4_32b_defconfig + - Raspberry Pi 4b + +64-bits: +^^^^^^^^ + +* rpi_3_defconfig + - Raspberry Pi 3b +* rpi_3_b_plus_defconfig + - Raspberry Pi 3b+ +* rpi_4_defconfig + - Raspberry Pi 4b +* rpi_arm64_defconfig + - Raspberry Pi 3b + - Raspberry Pi 3b+ + - Raspberry Pi 4b + - Raspberry Pi 400 + - Raspberry Pi CM 3 + - Raspberry Pi CM 3+ + - Raspberry Pi CM 4 + - Raspberry Pi zero 2 w + +Config rpi_arm64_defconfig uses the DTB proviede by the firmware instead of using the embedded one. It allows to actually boot the same U-Boot binary of different boards. + -- 2.34.1

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