March 2022 - U-Boot

[PATCH v3] spi: zynq_spi: add chip select decoder support
by Nikita Vasilev 20 Mar '22

20 Mar '22

Since zynq_spi device is compatible with Linux Cadence SPI driver, which supports chip select (CS) decoder, this patch adds the same logic for u-boot Zynq SPI driver. As a reference, I have used Xilinx Linux kernel 93dc4dbd16d (xilinx-v2020.2). The SPI decoder feature has been tested on ZynqMP ARM processor and result has been compared with Linux Cadence SPI driver. Signed-off-by: Nikita Vasilev <vasilevnikitad(a)gmail.com> Cc: Jagan Teki <jteki(a)openedev.com> --- drivers/spi/zynq_spi.c | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index b3e0858eb9..40a43612fb 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -29,6 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */ #define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */ #define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */ +#define ZYNQ_SPI_CR_PERI_SEL BIT(9) /* Peripheral select decode */ #define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */ #define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ #define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ @@ -62,6 +63,7 @@ struct zynq_spi_plat { u32 speed_hz; uint deactivate_delay_us; /* Delay to wait after deactivate */ uint activate_delay_us; /* Delay to wait after activate */ + u32 is_decoded_cs; }; /* zynq spi priv */ @@ -87,10 +89,13 @@ static int zynq_spi_of_to_plat(struct udevice *bus) plat->activate_delay_us = fdtdec_get_int(blob, node, "spi-activate-delay", 0); + plat->is_decoded_cs = dev_read_u32_default(bus, "is-decoded-cs", 0); + return 0; } -static void zynq_spi_init_hw(struct zynq_spi_priv *priv) +static void zynq_spi_init_hw(struct zynq_spi_priv *priv, + struct zynq_spi_platdata const *plat) { struct zynq_spi_regs *regs = priv->regs; u32 confr; @@ -114,6 +119,10 @@ static void zynq_spi_init_hw(struct zynq_spi_priv *priv) confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK | ZYNQ_SPI_CR_MSTREN_MASK; confr &= ~ZYNQ_SPI_CR_MSA_MASK; + + if (plat->is_decoded_cs) + confr |= ZYNQ_SPI_CR_PERI_SEL; + writel(confr, &regs->cr); /* Enable SPI */ @@ -150,7 +159,7 @@ static int zynq_spi_probe(struct udevice *bus) } /* init the zynq spi hw */ - zynq_spi_init_hw(priv); + zynq_spi_init_hw(priv, plat); plat->frequency = clock; plat->speed_hz = plat->frequency / 2; @@ -178,13 +187,19 @@ static void spi_cs_activate(struct udevice *dev) clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK); cr = readl(&regs->cr); - /* - * CS cal logic: CS[13:10] - * xxx0 - cs0 - * xx01 - cs1 - * x011 - cs2 - */ - cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; + + if (plat->is_decoded_cs) { + cr |= (priv->cs << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; + } else { + /* + * CS cal logic: CS[13:10] + * xxx0 - cs0 + * xx01 - cs1 + * x011 - cs2 + */ + cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; + } + writel(cr, &regs->cr); if (plat->activate_delay_us) -- 2.32.0 Changes for v3 - Still had some problems with spaces when sending patch via email. I hope that I fixed it. Changes for v2: - I have made a mistake when was trying to send patch and all tabs were gone. Since it's my first time when I send patches via email, I have some problems with it.

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[PATCH v2] spi: zynq_spi: add chip select decoder support
by Nikita Vasilev 20 Mar '22

20 Mar '22

Since zynq_spi device is compatible with Linux Cadence SPI driver, which supports chip select (CS) decoder, this patch adds the same logic for u-boot Zynq SPI driver. As a reference, I have used Xilinx Linux kernel 93dc4dbd16d (xilinx-v2020.2). The SPI decoder feature has been tested on ZynqMP ARM processor and result has been compared with Linux Cadence SPI driver. Signed-off-by: Nikita Vasilev <vasilevnikitad(a)gmail.com> Cc: Jagan Teki <jteki(a)openedev.com> --- drivers/spi/zynq_spi.c | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index b3e0858eb9..40a43612fb 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -29,6 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */ #define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */ #define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */ +#define ZYNQ_SPI_CR_PERI_SEL BIT(9) /* Peripheral select decode */ #define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */ #define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ #define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ @@ -62,6 +63,7 @@ struct zynq_spi_plat { u32 speed_hz; uint deactivate_delay_us; /* Delay to wait after deactivate */ uint activate_delay_us; /* Delay to wait after activate */ + u32 is_decoded_cs; }; /* zynq spi priv */ @@ -87,10 +89,13 @@ static int zynq_spi_of_to_plat(struct udevice *bus) plat->activate_delay_us = fdtdec_get_int(blob, node, "spi-activate-delay", 0); + plat->is_decoded_cs = dev_read_u32_default(bus, "is-decoded-cs", 0); + return 0; } -static void zynq_spi_init_hw(struct zynq_spi_priv *priv) +static void zynq_spi_init_hw(struct zynq_spi_priv *priv, + struct zynq_spi_platdata const *plat) { struct zynq_spi_regs *regs = priv->regs; u32 confr; @@ -114,6 +119,10 @@ static void zynq_spi_init_hw(struct zynq_spi_priv *priv) confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK | ZYNQ_SPI_CR_MSTREN_MASK; confr &= ~ZYNQ_SPI_CR_MSA_MASK; + + if (plat->is_decoded_cs) + confr |= ZYNQ_SPI_CR_PERI_SEL; + writel(confr, &regs->cr); /* Enable SPI */ @@ -150,7 +159,7 @@ static int zynq_spi_probe(struct udevice *bus) } /* init the zynq spi hw */ - zynq_spi_init_hw(priv); + zynq_spi_init_hw(priv, plat); plat->frequency = clock; plat->speed_hz = plat->frequency / 2; @@ -178,13 +187,19 @@ static void spi_cs_activate(struct udevice *dev) clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK); cr = readl(&regs->cr); - /* - * CS cal logic: CS[13:10] - * xxx0 - cs0 - * xx01 - cs1 - * x011 - cs2 - */ - cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; + + if (plat->is_decoded_cs) { + cr |= (priv->cs << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; + } else { + /* + * CS cal logic: CS[13:10] + * xxx0 - cs0 + * xx01 - cs1 + * x011 - cs2 + */ + cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; + } + writel(cr, &regs->cr); if (plat->activate_delay_us) -- 2.32.0 Changes for v2: - I have made a mistake when was trying to send patch and all tabs were gone. Since it's my first time when I send patches via email, I have some problems with it.

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[PATCH v3 0/2] cmd/sbi: add missing SBI information
by Heinrich Schuchardt 20 Mar '22

20 Mar '22

Let the sbi command display: * machine vendor ID * machine architecture ID * machine implementation ID Heinrich Schuchardt (2): riscv: provide missing base extension functions cmd/sbi: add missing SBI information arch/riscv/include/asm/sbi.h | 3 ++ arch/riscv/lib/sbi.c | 65 ++++++++++++++++++++++++++++++++++++ cmd/riscv/sbi.c | 13 +++++++- 3 files changed, 80 insertions(+), 1 deletion(-) -- 2.34.1

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[PATCH 0/2] Change behaviour of CONFIG_TIMER_EARLY
by Johannes Krottmayer 20 Mar '22

20 Mar '22

When CONFIG_TIMER_EARLY is selected and the timer driver implements timer_early_get_count() and timer_early_get_rate() this leads to an EAGAIN error one some configurations in... common/board_f.c:initf_dm() initf_dm() invokes dm_timer_init(), but this function returns with an EAGAIN error in, because the DM virtual root driver isn't initialized yet in... drivers/timer/timer-class.c:dm_timer_init() Moved error handling to... lib/time.c For details you can read the description in the patches. Affected drivers: drivers/timer/andes_plmt_timer.c drivers/timer/sifive_clint_timer.c drivers/timer/riscv_timer.c I don't know who maintains these base libraries and base functions, so I used the copyright holders. For the driver I added the required maintainers to CC. Signed-off-by: Johannes Krottmayer <krjdev(a)gmail.com> Cc: Wolfgang Denk <wd(a)denx.de> Cc: Thomas Chou <thomas(a)wytron.com.tw> Cc: Rick Chen <rick(a)andestech.com> Cc: Leo <ycliang(a)andestech.com> Cc: Bin Meng <bmeng.cn(a)gmail.com> Cc: Sean Anderson <seanga2(a)gmail.com> Cc: Anup Patel <anup(a)brainfault.org> Cc: Thomas Chou <thomas(a)wytron.com.tw> --- Johannes Krottmayer (2): lib: time: Change behaviour of CONFIG_TIMER_EARLY common: board_f: Fix CONFIG_TIMER_EARLY issue (EAGAIN) common/board_f.c | 6 ------ lib/time.c | 42 +++++++++++++++++++++++++++++++++--------- 2 files changed, 33 insertions(+), 15 deletions(-) -- 2.34.1

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[PATCH v2 1/1] cache: l2x0: Fix incorrect behavior if the latency is 1 cycle
by Haifeng Li 20 Mar '22

20 Mar '22

According to the PL310 TRM, 0 in the latency fields(setup/read/write) indicates 1 cycle of latency for Tag and Data RAM latency control registers. If we want to set 1 cycle of latency, we need to clear the field actually. The TRM is as below: https://developer.arm.com/documentation/ddi0246/h/programmers-model/registe… Signed-off-by: Haifeng Li <haifeng.li(a)timesintelli.com> --- drivers/cache/cache-l2x0.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c index a1556fbf17..16b583ddd2 100644 --- a/drivers/cache/cache-l2x0.c +++ b/drivers/cache/cache-l2x0.c @@ -38,19 +38,27 @@ static void l2c310_of_parse_and_init(struct udevice *dev) writel(saved_reg, &regs->pl310_aux_ctrl); - saved_reg = readl(&regs->pl310_tag_latency_ctrl); - if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3)) + if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3)) { + saved_reg = readl(&regs->pl310_tag_latency_ctrl); + clrbits_le32(&saved_reg, L310_LATENCY_CTRL_WR(7) | + L310_LATENCY_CTRL_RD(7) | + L310_LATENCY_CTRL_SETUP(7)); saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) | L310_LATENCY_CTRL_WR(tag[1] - 1) | L310_LATENCY_CTRL_SETUP(tag[2] - 1); - writel(saved_reg, &regs->pl310_tag_latency_ctrl); + writel(saved_reg, &regs->pl310_tag_latency_ctrl); + } - saved_reg = readl(&regs->pl310_data_latency_ctrl); - if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3)) + if (!dev_read_u32_array(dev, "arm,data-latency", tag, 3)) { + saved_reg = readl(&regs->pl310_data_latency_ctrl); + clrbits_le32(&saved_reg, L310_LATENCY_CTRL_WR(7) | + L310_LATENCY_CTRL_RD(7) | + L310_LATENCY_CTRL_SETUP(7)); saved_reg |= L310_LATENCY_CTRL_RD(tag[0] - 1) | L310_LATENCY_CTRL_WR(tag[1] - 1) | L310_LATENCY_CTRL_SETUP(tag[2] - 1); - writel(saved_reg, &regs->pl310_data_latency_ctrl); + writel(saved_reg, &regs->pl310_data_latency_ctrl); + } /* Enable the L2 cache */ setbits_le32(&regs->pl310_ctrl, L2X0_CTRL_EN); -- 2.17.1

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[PATCH v13 0/2] add TCP and HTTP for downloading images
by Ying-Chun Liu 20 Mar '22

20 Mar '22

From: "Ying-Chun Liu (PaulLiu)" <paul.liu(a)linaro.org> This patch is a refresh from previous patches made by Duncan Hare <DuncanCHare(a)yahoo.com>. I've contacted him and continue to work on this patch. This patch introduce a TCP stack with SACK. And a simple wget command to download images from http server. v13: Fix some issues which is reviewed by Christian Ying-Chun Liu (PaulLiu) (2): net: Add TCP protocol net: Add wget application cmd/Kconfig | 7 + cmd/net.c | 13 + include/net.h | 13 +- include/net/tcp.h | 222 ++++++++++++++ include/net/wget.h | 19 ++ net/Kconfig | 6 + net/Makefile | 2 + net/net.c | 36 +++ net/tcp.c | 698 +++++++++++++++++++++++++++++++++++++++++++++ net/wget.c | 436 ++++++++++++++++++++++++++++ 10 files changed, 1450 insertions(+), 2 deletions(-) create mode 100644 include/net/tcp.h create mode 100644 include/net/wget.h create mode 100644 net/tcp.c create mode 100644 net/wget.c -- 2.35.1

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ipq40xx serial driver not working
by Florence Riker 19 Mar '22

19 Mar '22

Hello everyone, recently I'm trying to port the newest version of u boot to my ipq4019 development board, and I found that the current serial driver for Qualcomm ipq40xx socs at u-boot-2022.01/drivers/serial/serial_msm.c is not compatible to ipq40xx despite they share the same compatible string in the device tree: u-boot-2022.01/drivers/serial/serial_msm.c: static const struct udevice_id msm_serial_ids[] = { { .compatible = "qcom,msm-uartdm-v1.4" }, { } }; u-boot-2022.01/arch/arm/dts/qcom-ipq4019.dtsi: blsp1_uart1: serial@78af000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; [...] }; I do have a confirmed working driver at hand, by comparing the code, I believe the reason behind this is the ipq40xx has a different register map than the current driver: Register map of my working diver at hand: struct ipq_serial_regs { unsigned int mr1; /* 0x00 - Operational Mode Register 1 */ unsigned int mr2; /* 0x04 - Operational Mode Register 2 */ unsigned int sr_csr; /* 0x08 - Status Register, Clock Selection Register */ unsigned char gap0[4]; /* 0x0C - gap */ unsigned int cr_misr; /* 0x10 - Command Register, Masked Interrupt Status Register */ unsigned int imr_isr; /* 0x14 - Interrupt Mask Register, Interrupt Status Register */ unsigned int ipr; /* 0x18 - Interrupt Programming Register */ unsigned int tfwr; /* 0x1C - Transmit FIFO Watermark Register */ unsigned int rfwr; /* 0x20 - Receive FIFO Watermark Register */ unsigned int hcr; /* 0x24 - Hunt Character Register */ unsigned char gap1[12]; /* 0x28 - gap */ unsigned int dmrx; /* 0x34 - RX transfer initialization */ unsigned int ncfrx_irda; /* 0x38 - Number of characters received since the end of last RX transfer, IRDA function Register */ unsigned int dmem; /* 0x3C - Data Mover Enable Register */ unsigned int ncftx; /* 0x40 - Number of characters for Transmission */ unsigned int badrr; /* 0x44 - RX FIFO Base Address */ unsigned char gap2[4]; /* 0x48 - gap */ unsigned int txfs; /* 0x4C - TX FIFO Status Register */ unsigned int rxfs; /* 0x50 - RX FIFO Status Register */ unsigned char gap3[28]; /* 0x54 - gap */ unsigned int rftf; /* 0x70 - UART Transmit and Receive FIFO Register */ }; Register definition bit at u-boot-2022.01/drivers/serial/serial_msm.c: #define UARTDM_MR1 0x00 #define UARTDM_MR2 0x04 #define UARTDM_DMRX 0x34 /* Max RX transfer length */ #define UARTDM_DMEN 0x3C /* DMA/data-packing mode */ #define UARTDM_NCF_TX 0x40 /* Number of chars to TX */ #define UARTDM_RXFS 0x50 /* RX channel status register */ #define UARTDM_ISR_TX_READY 0x80 /* TX FIFO empty */ #define UARTDM_CSR 0xA0 #define UARTDM_SR 0xA4 /* Status register */ #define UARTDM_CR 0xA8 /* Command register */ #define UARTDM_IMR 0xB0 /* Interrupt mask register */ #define UARTDM_ISR 0xB4 /* Interrupt status register */ #define UARTDM_TF 0x100 /* UART Transmit FIFO register */ #define UARTDM_RF 0x140 /* UART Receive FIFO register */ As you can see, for example: the working one's Transmit and Receive register definition is at an address of base + 0x70 while the current one's is at base + 0x100 and base + 0x140, so when the device is reading and sending things using current driver, they are doing it with wrong address and the serial won't work. I think this should be somehow fixed. Thanks.

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Please pull u-boot-video
by Anatolij Gustschin 19 Mar '22

19 Mar '22

Hi Tom, please pull video fixes for v2022.04-rc4. CI: https://source.denx.de/u-boot/custodians/u-boot-video/-/pipelines/11220 Thanks, Anatolij The following changes since commit 589c659035a44a683b087fd75fe0b7667f7be7f5: Merge branch '2022-03-08-assorted-fixes' (2022-03-08 08:42:51 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-video.git tags/video-20220314 for you to fetch changes up to d6213e206c441a3b2b83c0588954c851c3610d97: Nokia RX-51: Convert to CONFIG_DM_VIDEO (2022-03-09 21:28:53 +0100) ---------------------------------------------------------------- - fix display of the u-boot logo on Apple devices - convert Nokia RX-51 to CONFIG_DM_VIDEO ---------------------------------------------------------------- Janne Grunau (1): video: bmp: Support x2r10g10b10 pixel format Pali Rohár (2): video: Allow drivers to allocate the frame buffer themselves Nokia RX-51: Convert to CONFIG_DM_VIDEO board/nokia/rx51/rx51.c | 40 +++++++++++++++---------- configs/nokia_rx51_defconfig | 7 +++-- drivers/video/video-uclass.c | 7 ++++- drivers/video/video_bmp.c | 70 +++++++++++++++++++++++++++++++++++--------- include/configs/nokia_rx51.h | 11 ++----- 5 files changed, 93 insertions(+), 42 deletions(-)

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Please pull u-boot-dm/next
by Simon Glass 19 Mar '22

19 Mar '22

Hi Tom, I have a passing run without the coreboot test. Are you seeing problems with that? I may need to move the downloads into the docker image. https://source.denx.de/u-boot/custodians/u-boot-dm/-/pipelines/11350 The following changes since commit 297e6eb8dcf9d90aaf9b0d146cdd502403003d04: Merge tag 'xilinx-for-v2022.07-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next (2022-03-16 12:52:02 -0400) are available in the Git repository at: git://git.denx.de/u-boot-dm.git tags/dm-pull-18mar22 for you to fetch changes up to 40c8bdd87e3baa44314720d0d51d90c41e633ca3: binman: Support splitting an ELF file into multiple nodes (2022-03-18 19:24:25 -0600) ---------------------------------------------------------------- binman FIT improvements various minor sandbox improvements ---------------------------------------------------------------- Jan Kiszka (1): binman: Include also subnodes in generator nodes Philippe Reynes (1): tools: binman: main.py: add build-sandbox in sys.path Simon Glass (28): binman: Complete elf test coverage sandbox: Show a message when writing out the ram buffer sandbox: Add the handoff header for spl sandbox: Open host file for read-only access if needed sandbox: Slow down the LCD sync rate sandbox: test: Tidy up spl_test_load() calls patman: Define Commit.path in the constructor dtoc: Make GetArgs() more flexible moveconfig: Remove remove_defconfig() moveconfig: Use re.fullmatch() to avoid extra check spl: Correct Kconfig help for TPL_BINMAN_SYMBOLS dtoc: Tidy up implementation of AddStringList() elf: Rename load_segments() and module failure binman: Tweak collect_contents_to_file() and docs binman: Rename ExpandToLimit to extend_to_limit binman: Rename ExpandEntries to gen_entries binman: Refactor fit to generate output at the end binman: Rename tools parameter to btools binman: Change how faked blobs are created binman: Make fake blobs zero-sized by default binman: Allow mkimage to use a non-zero fake-blob size binman: Read the fit entries only once binman: Update fit to move node reading into the ReadNode() method binman: Fix some pylint warnings in fit binman: Add a consistent way to report errors with fit binman: Update fit to use node instead of subnode binman: Keep a separate list of entries for fit binman: Support splitting an ELF file into multiple nodes arch/sandbox/cpu/spl.c | 1 + arch/sandbox/cpu/state.c | 3 +- common/spl/Kconfig | 6 +- drivers/block/sandbox.c | 11 +- drivers/video/video-uclass.c | 2 +- test/image/spl_load.c | 6 +- tools/binman/binman.rst | 32 +- tools/binman/control.py | 2 +- tools/binman/elf.py | 10 +- tools/binman/elf_test.py | 66 +++- tools/binman/entries.rst | 146 ++++++++ tools/binman/entry.py | 51 +-- tools/binman/etype/_testing.py | 2 +- tools/binman/etype/blob.py | 10 +- tools/binman/etype/blob_ext_list.py | 2 +- tools/binman/etype/blob_phase.py | 2 +- tools/binman/etype/files.py | 2 +- tools/binman/etype/fit.py | 512 ++++++++++++++++++++------- tools/binman/etype/gbb.py | 4 +- tools/binman/etype/intel_ifwi.py | 4 +- tools/binman/etype/mkimage.py | 19 +- tools/binman/etype/section.py | 24 +- tools/binman/etype/vblock.py | 4 +- tools/binman/ftest.py | 209 +++++++++-- tools/binman/main.py | 1 + .../binman/test/{088_expand_size.dts => 088_extend_size.dts} | 8 +- .../{089_expand_size_bad.dts => 089_extend_size_bad.dts} | 2 +- .../test/{121_entry_expand.dts => 121_entry_extend.dts} | 0 ...122_entry_expand_twice.dts => 122_entry_extend_twice.dts} | 0 ...entry_expand_section.dts => 123_entry_extend_section.dts} | 0 tools/binman/test/170_fit_fdt.dts | 3 + tools/binman/test/224_fit_bad_oper.dts | 2 - tools/binman/test/225_expand_size_bad.dts | 10 + tools/binman/test/226_fit_split_elf.dts | 67 ++++ tools/binman/test/227_fit_bad_dir.dts | 9 + tools/binman/test/228_fit_bad_dir_config.dts | 9 + tools/binman/test/229_mkimage_missing.dts | 18 + tools/dtoc/fdt.py | 4 +- tools/dtoc/fdt_util.py | 12 +- tools/dtoc/test/dtoc_test_simple.dts | 2 + tools/dtoc/test_fdt.py | 14 +- tools/moveconfig.py | 16 +- tools/patman/commit.py | 2 + 43 files changed, 1051 insertions(+), 258 deletions(-) rename tools/binman/test/{088_expand_size.dts => 088_extend_size.dts} (88%) rename tools/binman/test/{089_expand_size_bad.dts => 089_extend_size_bad.dts} (90%) rename tools/binman/test/{121_entry_expand.dts => 121_entry_extend.dts} (100%) rename tools/binman/test/{122_entry_expand_twice.dts => 122_entry_extend_twice.dts} (100%) rename tools/binman/test/{123_entry_expand_section.dts => 123_entry_extend_section.dts} (100%) create mode 100644 tools/binman/test/225_expand_size_bad.dts create mode 100644 tools/binman/test/226_fit_split_elf.dts create mode 100644 tools/binman/test/227_fit_bad_dir.dts create mode 100644 tools/binman/test/228_fit_bad_dir_config.dts create mode 100644 tools/binman/test/229_mkimage_missing.dts Regards, Simon

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[PATCH 1/2] board: tbs2910: Enable Link Time Optimizations in defconfig
by Soeren Moch 19 Mar '22

19 Mar '22

This saves about 12 kBytes image size and helps to stay within the size limit. Suggested-by: Tom Rini <trini(a)konsulko.com> Signed-off-by: Soeren Moch <smoch(a)web.de> --- Cc: Stefano Babic <sbabic(a)denx.de> Cc: Fabio Estevam <festevam(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: u-boot(a)lists.denx.de Unfortunately we already are at the size limit for U-Boot v2022.04-rc3. Maybe Tom can pick up this patch directly, otherwise it's also fine for me to take this through the imx tree. --- configs/tbs2910_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index e1278f2e70..8a33160564 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -14,6 +14,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6q-tbs2910" CONFIG_PRE_CON_BUF_ADDR=0x7c000000 CONFIG_CMD_HDMIDETECT=y CONFIG_AHCI=y +CONFIG_LTO=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y -- 2.25.1

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