March 2022 - U-Boot

[PATCH v2 0/5] sunxi: remove lowlevel_init
by Andre Przywara 21 Mar '22

21 Mar '22

Hi, a smallish update, following the comments of the diligent reviewers (thanks Samuel and Simon!). ARMV7_SET_CORTEX_SMPEN is now a blind symbol, set by the SoCs that need it. The rest are more cosmetic changes, see below for a changelog. ================== For a long time the Allwinner platform was using the lowlevel_init() routine in U-Boot's boot process, even though there did not seem to be a real need for that. The README file suggests it should only be used for "bare minimum" tasks to reach board_init_f(). The routines called in arch/arm/mach-sunxi/board.c:s_init() did nothing that really warranted the early and special execution. Since we always run with an SPL, the board_init_f() routine in there seems to be the right place for early peripherals initialisation. Having those routines in s_init() actually forced other parts of U-Boot to follow suit: for instance we added a lowlevel_init() function to the armv8 side, just for sunxi. The same game seems to repeat for the ARM9 support we need for the F1C100s chip, and possibly for the RISC-V part as well. To avoid this and to cleanup some code on the way, remove the need for lowlevel_init for sunxi completely, by: - moving the early peripheral init (clocks, timer, pinmux) to board_init_f(). This also avoids executing those bits a second time when we boot up U-Boot proper. (patch 1/5) - move the "SRAM setup" bits for just a few old SoCs into a separate file, and include this only if needed. (patch 3/5) - move the ACTLR.SMPEN bit setting from board.c into start.S, because we actually need to set this bit early. Other platforms should be able to scrap their own copies and piggy back on this change. (patch 2/5) This allows us to actually remove the lowlevel_init.S file from armv8 in patch 4/5, as sunxi was the only user. For good measure, we also clean up some bits in sunxi_common.h. (patch 5/5) I compile tested this for all sunxi boards, and boot tested (into Linux) on Pine64, PineH64, BananaPi M1, OrangePi Zero. But there is a high chance of something breaking, so please give it a good shake on whatever Allwinner hardware you have access to. Thanks, Andre Changelog v1 ... v2: - Move i2c_init_board() into existing I2C guard (patch 1/5) - Make ARMV7_SET_CORTEX_SMPEN a blind symbol and select it (patch 2/5) - Use sunxi_get_sram_id() instead of open coding it (patch 3/5) - More precise wording in patch 4/5 commit message (lowlevel_init.S) - Add Reviewed-by: and Tested-by: tags Andre Przywara (5): sunxi: move non-essential code out of s_init() sunxi: move Cortex SMPEN setting into start.S sunxi: move early "SRAM setup" into separate file armv8: remove no longer needed lowlevel_init.S sunxi-common.h: remove pointless #ifdefs arch/arm/Kconfig | 3 - arch/arm/cpu/armv7/Kconfig | 5 ++ arch/arm/cpu/armv7/start.S | 11 +++ arch/arm/cpu/armv7/sunxi/Makefile | 3 + arch/arm/cpu/armv7/sunxi/sram.c | 40 +++++++++++ arch/arm/cpu/armv8/Makefile | 1 - arch/arm/cpu/armv8/lowlevel_init.S | 43 ------------ arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 1 + arch/arm/mach-sunxi/Kconfig | 6 +- arch/arm/mach-sunxi/board.c | 76 +++++---------------- include/configs/sunxi-common.h | 7 -- 11 files changed, 82 insertions(+), 114 deletions(-) create mode 100644 arch/arm/cpu/armv7/sunxi/sram.c delete mode 100644 arch/arm/cpu/armv8/lowlevel_init.S -- 2.17.6

4 11

[PATCH v4] wdt: nuvoton: Add support for Nuvoton
by Jim Liu 21 Mar '22

21 Mar '22

Add watchdog controller driver for NPCM7xx/npcm8xx Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> Reviewed-by: Stefan Roese <sr(a)denx.de> Changes for v4: - add a bit of detail about the device in Kconfig - lower-case hex change - remove the reset function delay.Actually when setting writel NPCM_WTR the watchdog is resetting the BMC --- drivers/watchdog/Kconfig | 8 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/npcm_wdt.c | 117 ++++++++++++++++++++++++++++++++++++ 3 files changed, 126 insertions(+) create mode 100644 drivers/watchdog/npcm_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index f90f0ca02b..d33882fb6a 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -196,6 +196,14 @@ config WDT_MTK The watchdog timer is stopped when initialized. It performs full SoC reset. +config WDT_NPCM + bool "Nuvoton watchdog timer support" + depends on WDT && ARCH_NPCM + help + This enables Nuvoton npcm7xx/npcm8xx watchdog timer driver, + The watchdog timer is stopped when initialized. + It performs full SoC reset. + config WDT_OCTEONTX bool "OcteonTX core watchdog support" depends on WDT && (ARCH_OCTEONTX || ARCH_OCTEONTX2) diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index a35bd559f5..1089cd21f5 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o obj-$(CONFIG_WDT_MTK) += mtk_wdt.o +obj-$(CONFIG_WDT_NPCM) += npcm_wdt.o obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c new file mode 100644 index 0000000000..0aedb2fbe7 --- /dev/null +++ b/drivers/watchdog/npcm_wdt.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Nuvoton Technology, Inc + */ + +#include <dm.h> +#include <errno.h> +#include <log.h> +#include <wdt.h> +#include <asm/io.h> +#include <linux/delay.h> +#include <linux/err.h> + +#define NPCM_WTCLK (BIT(10) | BIT(11)) /* Clock divider */ +#define NPCM_WTE BIT(7) /* Enable */ +#define NPCM_WTIE BIT(6) /* Enable irq */ +#define NPCM_WTIS (BIT(4) | BIT(5)) /* Interval selection */ +#define NPCM_WTIF BIT(3) /* Interrupt flag*/ +#define NPCM_WTRF BIT(2) /* Reset flag */ +#define NPCM_WTRE BIT(1) /* Reset enable */ +#define NPCM_WTR BIT(0) /* Reset counter */ + +struct npcm_wdt_priv { + void __iomem *regs; +}; + +static int npcm_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + struct npcm_wdt_priv *priv = dev_get_priv(dev); + u32 time_out, val; + + time_out = (u32)(timeout_ms) / 1000; + if (time_out < 2) + val = 0x800; + else if (time_out < 3) + val = 0x420; + else if (time_out < 6) + val = 0x810; + else if (time_out < 11) + val = 0x430; + else if (time_out < 22) + val = 0x820; + else if (time_out < 44) + val = 0xc00; + else if (time_out < 87) + val = 0x830; + else if (time_out < 173) + val = 0xc10; + else if (time_out < 688) + val = 0xc20; + else + val = 0xc30; + + val |= NPCM_WTRE | NPCM_WTE | NPCM_WTR | NPCM_WTIE; + writel(val, priv->regs); + + return 0; +} + +static int npcm_wdt_stop(struct udevice *dev) +{ + struct npcm_wdt_priv *priv = dev_get_priv(dev); + + writel(0, priv->regs); + + return 0; +} + +static int npcm_wdt_reset(struct udevice *dev) +{ + struct npcm_wdt_priv *priv = dev_get_priv(dev); + + writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, priv->regs); + + return 0; +} + +static int npcm_wdt_of_to_plat(struct udevice *dev) +{ + struct npcm_wdt_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) + return -EINVAL; + + return 0; +} + +static const struct wdt_ops npcm_wdt_ops = { + .start = npcm_wdt_start, + .reset = npcm_wdt_reset, + .stop = npcm_wdt_stop, +}; + +static const struct udevice_id npcm_wdt_ids[] = { + { .compatible = "nuvoton,npcm750-wdt" }, + { .compatible = "nuvoton,npcm845-wdt" }, + { } +}; + +static int npcm_wdt_probe(struct udevice *dev) +{ + debug("%s() wdt%u\n", __func__, dev_seq(dev)); + npcm_wdt_stop(dev); + + return 0; +} + +U_BOOT_DRIVER(npcm_wdt) = { + .name = "npcm_wdt", + .id = UCLASS_WDT, + .of_match = npcm_wdt_ids, + .probe = npcm_wdt_probe, + .priv_auto = sizeof(struct npcm_wdt_priv), + .of_to_plat = npcm_wdt_of_to_plat, + .ops = &npcm_wdt_ops, +}; -- 2.17.1

4 3

[PATCH v3 0/6] imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards
by Ariel D'Alessandro 21 Mar '22

21 Mar '22

Introduce BSH SystemMaster (SMM) S2 board family, which consists of: iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards. This patchset also adds support for NXP TJA11xx Ethernet PHYs. Changes in v3: * Added nxp-c45-tja11xx driver. * Added ethernet support to iMX8MN BSH SMM S2 boards. Changes in v2: * Properly added MAINTAINERS entry. * Fixed binman configuration. * Picked device tree from kernel. * Removed CONFIG_SPL_BUILD anti-pattern in board config. * Removed downstream stuff in bootargs. * Added board documentation. Ariel D'Alessandro (4): phy: nxp-c45-tja11xx: Rename functions to be c45 tja11xx specific iopoll: Extend read_poll_timeout macro to support variable parameters net: phy: Add phy_modify() accessor bsh: imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards Michael Trimarchi (2): imx8m: add regs used by GPMI net: phy: nxp-tja11xx: Add NXP TJA11xx PHY driver arch/arm/dts/Makefile | 2 + arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi | 423 ++++++++ .../dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi | 225 +++++ arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi | 15 + arch/arm/dts/imx8mn-bsh-smm-s2.dts | 48 + arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi | 15 + arch/arm/dts/imx8mn-bsh-smm-s2pro.dts | 80 ++ arch/arm/include/asm/arch-imx8m/imx-regs.h | 7 + arch/arm/mach-imx/imx8m/Kconfig | 15 + arch/arm/mach-socfpga/reset_manager_s10.c | 20 +- board/bsh/imx8mn_smm_s2/Kconfig | 49 + board/bsh/imx8mn_smm_s2/MAINTAINERS | 8 + board/bsh/imx8mn_smm_s2/Makefile | 13 + board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c | 941 ++++++++++++++++++ board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c | 941 ++++++++++++++++++ board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c | 23 + board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg | 10 + board/bsh/imx8mn_smm_s2/spl.c | 93 ++ configs/imx8mn_bsh_smm_s2_defconfig | 97 ++ configs/imx8mn_bsh_smm_s2pro_defconfig | 94 ++ doc/board/bsh/imx8mn_bsh_smm_s2.rst | 62 ++ doc/board/bsh/index.rst | 9 + doc/board/index.rst | 1 + drivers/mmc/rockchip_sdhci.c | 9 +- drivers/net/phy/Kconfig | 5 + drivers/net/phy/Makefile | 1 + drivers/net/phy/nxp-c45-tja11xx.c | 6 +- drivers/net/phy/nxp-tja11xx.c | 277 ++++++ drivers/net/phy/phy.c | 23 + include/configs/imx8mn_bsh_smm_s2.h | 52 + include/configs/imx8mn_bsh_smm_s2_common.h | 62 ++ include/configs/imx8mn_bsh_smm_s2pro.h | 35 + include/linux/iopoll.h | 12 +- include/phy.h | 3 + 34 files changed, 3654 insertions(+), 22 deletions(-) create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2.dts create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mn-bsh-smm-s2pro.dts create mode 100644 board/bsh/imx8mn_smm_s2/Kconfig create mode 100644 board/bsh/imx8mn_smm_s2/MAINTAINERS create mode 100644 board/bsh/imx8mn_smm_s2/Makefile create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c create mode 100644 board/bsh/imx8mn_smm_s2/ddr3l_timing_512m.c create mode 100644 board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c create mode 100644 board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg create mode 100644 board/bsh/imx8mn_smm_s2/spl.c create mode 100644 configs/imx8mn_bsh_smm_s2_defconfig create mode 100644 configs/imx8mn_bsh_smm_s2pro_defconfig create mode 100644 doc/board/bsh/imx8mn_bsh_smm_s2.rst create mode 100644 doc/board/bsh/index.rst create mode 100644 drivers/net/phy/nxp-tja11xx.c create mode 100644 include/configs/imx8mn_bsh_smm_s2.h create mode 100644 include/configs/imx8mn_bsh_smm_s2_common.h create mode 100644 include/configs/imx8mn_bsh_smm_s2pro.h -- 2.34.1

4 11

FIT image with different load addresses
by Chris Packham 21 Mar '22

21 Mar '22

Hi, I've got 2 ARM64 boards. The can both use the same kernel and initrd except dram on one starts at 0 and on the other at 0x200000000. Is it possible to set the loadaddr and entrypoint in a FIT image such that it will work for both boards? If I put 2 kernel entries using the same binary will the resulting image have a double up on the kernel data or are things smart enough to realize the binary is the same. Thanks, Chris

1 0

[PATCH v2] efi_loader: Use sysreset instead of reset command
by Masami Hiramatsu 21 Mar '22

21 Mar '22

Use sysreset_walk_halt() directly from reset-after-capsule-on-disk feature to reboot (cold reset) machine instead of using reset command interface, since this is not a command. Note that this will make CONFIG_EFI_CAPSULE_ON_DISK depending on the CONFIG_SYSRESET. Signed-off-by: Masami Hiramatsu <masami.hiramatsu(a)linaro.org> --- Changes in v2: - Add CONFIG_SYSRESET dependency. - Fix to add #include <sysreset.h> --- lib/efi_loader/Kconfig | 1 + lib/efi_loader/efi_capsule.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index e5e35fe51f..33138237cc 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -130,6 +130,7 @@ config EFI_RUNTIME_UPDATE_CAPSULE config EFI_CAPSULE_ON_DISK bool "Enable capsule-on-disk support" + depends on SYSRESET select EFI_HAVE_CAPSULE_SUPPORT help Select this option if you want to use capsule-on-disk feature, diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c index 613b531b82..a3d1d7e95a 100644 --- a/lib/efi_loader/efi_capsule.c +++ b/lib/efi_loader/efi_capsule.c @@ -18,6 +18,7 @@ #include <malloc.h> #include <mapmem.h> #include <sort.h> +#include <sysreset.h> #include <asm/global_data.h> #include <crypto/pkcs7.h> @@ -1150,9 +1151,9 @@ efi_status_t efi_launch_capsules(void) * UEFI spec requires to reset system after complete processing capsule * update on the storage. */ - log_info("Reboot after firmware update"); + log_info("Reboot after firmware update.\n"); /* Cold reset is required for loading the new firmware. */ - do_reset(NULL, 0, 0, NULL); + sysreset_walk_halt(SYSRESET_COLD); hang(); /* not reach here */

3 4

[PATCH 0/2] enable DM_SERIAL on imx8mn-evk and imx8mn-ddr4-evk
by Heiko Thiery 21 Mar '22

21 Mar '22

I was only able to test it on a 8MNANOD3L-EVK board. Please help testing this change on the other 2 eval boards (8MNANOLPD4-EVK, 8MNANOD4-EVK). Heiko Thiery (2): ARM: imx: imx8mn-evk: enable DM_SERIAL ARM: imx: imx8mn-ddr4-evk: enable DM_SERIAL configs/imx8mn_ddr4_evk_defconfig | 2 ++ configs/imx8mn_evk_defconfig | 2 ++ 2 files changed, 4 insertions(+) -- 2.30.2

3 5

[PATCH v5] wdt: nuvoton: Add support for Nuvoton
by Jim Liu 21 Mar '22

21 Mar '22

Add watchdog controller driver for NPCM7xx/npcm8xx Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> Reviewed-by: Stefan Roese <sr(a)denx.de> Reviewed-by: Simon Glass <sjg(a)chromium.org> Changes for v2: - coding style cleanup - change register type from struct Changes for v3: - remove common.h Changes for v4: - add a bit of detail about the device in Kconfig - lower-case hex change - remove the reset function delay. Actually when setting writel(NPCM_WTR )the watchdog is resetting the BMC changes for v5: - modify compatible name to support all NPCM SOC --- drivers/watchdog/Kconfig | 8 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/npcm_wdt.c | 116 ++++++++++++++++++++++++++++++++++++ 3 files changed, 125 insertions(+) create mode 100644 drivers/watchdog/npcm_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index f90f0ca02b..d33882fb6a 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -196,6 +196,14 @@ config WDT_MTK The watchdog timer is stopped when initialized. It performs full SoC reset. +config WDT_NPCM + bool "Nuvoton watchdog timer support" + depends on WDT && ARCH_NPCM + help + This enables Nuvoton npcm7xx/npcm8xx watchdog timer driver, + The watchdog timer is stopped when initialized. + It performs full SoC reset. + config WDT_OCTEONTX bool "OcteonTX core watchdog support" depends on WDT && (ARCH_OCTEONTX || ARCH_OCTEONTX2) diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index a35bd559f5..1089cd21f5 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o obj-$(CONFIG_WDT_MTK) += mtk_wdt.o +obj-$(CONFIG_WDT_NPCM) += npcm_wdt.o obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c new file mode 100644 index 0000000000..3fedc544b9 --- /dev/null +++ b/drivers/watchdog/npcm_wdt.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Nuvoton Technology, Inc + */ + +#include <dm.h> +#include <errno.h> +#include <log.h> +#include <wdt.h> +#include <asm/io.h> +#include <linux/delay.h> +#include <linux/err.h> + +#define NPCM_WTCLK (BIT(10) | BIT(11)) /* Clock divider */ +#define NPCM_WTE BIT(7) /* Enable */ +#define NPCM_WTIE BIT(6) /* Enable irq */ +#define NPCM_WTIS (BIT(4) | BIT(5)) /* Interval selection */ +#define NPCM_WTIF BIT(3) /* Interrupt flag*/ +#define NPCM_WTRF BIT(2) /* Reset flag */ +#define NPCM_WTRE BIT(1) /* Reset enable */ +#define NPCM_WTR BIT(0) /* Reset counter */ + +struct npcm_wdt_priv { + void __iomem *regs; +}; + +static int npcm_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + struct npcm_wdt_priv *priv = dev_get_priv(dev); + u32 time_out, val; + + time_out = (u32)(timeout_ms) / 1000; + if (time_out < 2) + val = 0x800; + else if (time_out < 3) + val = 0x420; + else if (time_out < 6) + val = 0x810; + else if (time_out < 11) + val = 0x430; + else if (time_out < 22) + val = 0x820; + else if (time_out < 44) + val = 0xc00; + else if (time_out < 87) + val = 0x830; + else if (time_out < 173) + val = 0xc10; + else if (time_out < 688) + val = 0xc20; + else + val = 0xc30; + + val |= NPCM_WTRE | NPCM_WTE | NPCM_WTR | NPCM_WTIE; + writel(val, priv->regs); + + return 0; +} + +static int npcm_wdt_stop(struct udevice *dev) +{ + struct npcm_wdt_priv *priv = dev_get_priv(dev); + + writel(0, priv->regs); + + return 0; +} + +static int npcm_wdt_reset(struct udevice *dev) +{ + struct npcm_wdt_priv *priv = dev_get_priv(dev); + + writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, priv->regs); + + return 0; +} + +static int npcm_wdt_of_to_plat(struct udevice *dev) +{ + struct npcm_wdt_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) + return -EINVAL; + + return 0; +} + +static const struct wdt_ops npcm_wdt_ops = { + .start = npcm_wdt_start, + .reset = npcm_wdt_reset, + .stop = npcm_wdt_stop, +}; + +static const struct udevice_id npcm_wdt_ids[] = { + { .compatible = "nuvoton,npcm-wdt" }, + { } +}; + +static int npcm_wdt_probe(struct udevice *dev) +{ + debug("%s() wdt%u\n", __func__, dev_seq(dev)); + npcm_wdt_stop(dev); + + return 0; +} + +U_BOOT_DRIVER(npcm_wdt) = { + .name = "npcm_wdt", + .id = UCLASS_WDT, + .of_match = npcm_wdt_ids, + .probe = npcm_wdt_probe, + .priv_auto = sizeof(struct npcm_wdt_priv), + .of_to_plat = npcm_wdt_of_to_plat, + .ops = &npcm_wdt_ops, +}; -- 2.17.1

1 0

Re: Pull request for efi-2022-04-rc5
by Tom Rini 21 Mar '22

21 Mar '22

On Sun, Mar 20, 2022 at 06:24:51PM +0100, Heinrich Schuchardt wrote: > Dear Tom, > > The following changes since commit 9776c4e9d00ac49d6388ffe9e084ff03b37ae479: > > Merge tag 'u-boot-rockchip-20220318' of > https://source.denx.de/u-boot/custodians/u-boot-rockchip (2022-03-18 > 16:37:39 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-efi.git > tags/efi-2022-04-rc5 > > for you to fetch changes up to 9c045a49a9c96ffb6e6b43f7e615fc2bd0e2077d: > > efi_loader: move dtbdump.c, initrddump.c to lib/efi_loader > (2022-03-20 17:01:00 +0100) > Applied to u-boot/master, thanks! -- Tom

1 0

[PATCH 1/2] pmic: pca9450: Add upstream regulators subnode match
by Marek Vasut 21 Mar '22

21 Mar '22

The upstream DT regulators node subnodes are named BUCKn and LDOn, the downstream DT regulators node subnodes are named buckn and ldon, add the upstream match. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Fabio Estevam <festevam(a)denx.de> Cc: Peng Fan <peng.fan(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- drivers/power/pmic/pca9450.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index 2394b196c56..26c876c9c45 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR; static const struct pmic_child_info pmic_children_info[] = { /* buck */ { .prefix = "b", .driver = PCA9450_REGULATOR_DRIVER}, + { .prefix = "B", .driver = PCA9450_REGULATOR_DRIVER}, /* ldo */ { .prefix = "l", .driver = PCA9450_REGULATOR_DRIVER}, + { .prefix = "L", .driver = PCA9450_REGULATOR_DRIVER}, { }, }; -- 2.34.1

3 6

[PATCH v3] spi: zynq_spi: add chip select decoder support
by Nikita Vasilev 20 Mar '22

20 Mar '22

Since zynq_spi device is compatible with Linux Cadence SPI driver, which supports chip select (CS) decoder, this patch adds the same logic for u-boot Zynq SPI driver. As a reference, I have used Xilinx Linux kernel 93dc4dbd16d (xilinx-v2020.2). The SPI decoder feature has been tested on ZynqMP ARM processor and result has been compared with Linux Cadence SPI driver. Signed-off-by: Nikita Vasilev <vasilevnikitad(a)gmail.com> Cc: Jagan Teki <jteki(a)openedev.com> --- drivers/spi/zynq_spi.c | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c index b3e0858eb9..40a43612fb 100644 --- a/drivers/spi/zynq_spi.c +++ b/drivers/spi/zynq_spi.c @@ -29,6 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */ #define ZYNQ_SPI_CR_CPOL_MASK BIT(1) /* Clock polarity */ #define ZYNQ_SPI_CR_MSTREN_MASK BIT(0) /* Mode select */ +#define ZYNQ_SPI_CR_PERI_SEL BIT(9) /* Peripheral select decode */ #define ZYNQ_SPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */ #define ZYNQ_SPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */ #define ZYNQ_SPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */ @@ -62,6 +63,7 @@ struct zynq_spi_plat { u32 speed_hz; uint deactivate_delay_us; /* Delay to wait after deactivate */ uint activate_delay_us; /* Delay to wait after activate */ + u32 is_decoded_cs; }; /* zynq spi priv */ @@ -87,10 +89,13 @@ static int zynq_spi_of_to_plat(struct udevice *bus) plat->activate_delay_us = fdtdec_get_int(blob, node, "spi-activate-delay", 0); + plat->is_decoded_cs = dev_read_u32_default(bus, "is-decoded-cs", 0); + return 0; } -static void zynq_spi_init_hw(struct zynq_spi_priv *priv) +static void zynq_spi_init_hw(struct zynq_spi_priv *priv, + struct zynq_spi_platdata const *plat) { struct zynq_spi_regs *regs = priv->regs; u32 confr; @@ -114,6 +119,10 @@ static void zynq_spi_init_hw(struct zynq_spi_priv *priv) confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK | ZYNQ_SPI_CR_MSTREN_MASK; confr &= ~ZYNQ_SPI_CR_MSA_MASK; + + if (plat->is_decoded_cs) + confr |= ZYNQ_SPI_CR_PERI_SEL; + writel(confr, &regs->cr); /* Enable SPI */ @@ -150,7 +159,7 @@ static int zynq_spi_probe(struct udevice *bus) } /* init the zynq spi hw */ - zynq_spi_init_hw(priv); + zynq_spi_init_hw(priv, plat); plat->frequency = clock; plat->speed_hz = plat->frequency / 2; @@ -178,13 +187,19 @@ static void spi_cs_activate(struct udevice *dev) clrbits_le32(&regs->cr, ZYNQ_SPI_CR_CS_MASK); cr = readl(&regs->cr); - /* - * CS cal logic: CS[13:10] - * xxx0 - cs0 - * xx01 - cs1 - * x011 - cs2 - */ - cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; + + if (plat->is_decoded_cs) { + cr |= (priv->cs << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; + } else { + /* + * CS cal logic: CS[13:10] + * xxx0 - cs0 + * xx01 - cs1 + * x011 - cs2 + */ + cr |= (~(1 << priv->cs) << ZYNQ_SPI_CR_SS_SHIFT) & ZYNQ_SPI_CR_CS_MASK; + } + writel(cr, &regs->cr); if (plat->activate_delay_us) -- 2.32.0 Changes for v4 - Still had some problems with spaces when sending patch via email. I hope that it is last email. I will not spam anymore Changes for v3 - Still had some problems with spaces when sending patch via email. I hope that I fixed it. Changes for v2: - I have made a mistake when was trying to send patch and all tabs were gone. Since it's my first time when I send patches via email, I have some problems with it.

1 0