March 2022 - U-Boot

[PATCH] cmd: pxe_utils: sysboot: replace cls command by video_clear in PXE parser
by Patrick Delaunay 22 Mar '22

22 Mar '22

Since the commit bfaa51dd4adf ("cmd: add serial console support for the cls command") the cls command is not enough to clear the video display when ANSI console is activated. This patch clears the video device with the video_clear() API before to display the bitmap used for the PXE background. This patch avoids to display the LOGO, activated by default with commit 7a8555d87136 ("video: Show the U-Boot logo by default"). Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- boot/pxe_utils.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c index 0c24becae3..115d33b845 100644 --- a/boot/pxe_utils.c +++ b/boot/pxe_utils.c @@ -14,6 +14,7 @@ #include <lcd.h> #include <net.h> #include <fdt_support.h> +#include <video.h> #include <linux/libfdt.h> #include <linux/string.h> #include <linux/ctype.h> @@ -1511,13 +1512,17 @@ void handle_pxe_menu(struct pxe_context *ctx, struct pxe_menu *cfg) void *choice; struct menu *m; int err; + struct udevice *dev; if (IS_ENABLED(CONFIG_CMD_BMP)) { /* display BMP if available */ if (cfg->bmp) { if (get_relfile(ctx, cfg->bmp, image_load_addr, NULL)) { - if (CONFIG_IS_ENABLED(CMD_CLS)) - run_command("cls", 0); + if (IS_ENABLED(CONFIG_DM_VIDEO)) { + err = uclass_first_device_err(UCLASS_VIDEO, &dev); + if (!err) + video_clear(dev); + } bmp_display(image_load_addr, BMP_ALIGN_CENTER, BMP_ALIGN_CENTER); } else { -- 2.25.1

2 1

[PATCH 2/2] ram: k3-ddrss: Fix register definitions
by Dominic Rath 22 Mar '22

22 Mar '22

The K3 DDRSS used by AM64x and J721e (and probably J7200 in the future) used to define only two register ranges: one labeled "cfg" that was internally referenced as "DDRSS wrapper", and the LPDDR4 FSP handshake registers in the CTRL_MMR register space, labeled "ctrl_mmr_lp4". The address specified as the "cfg" register space was actually the DDR controller's configuration registers, not the wrapper. The "cfg" registers were mostly used correctly as the address passed to Cadence code that actually configured the DDR controller and subsystems, but the code also attempted to use this register space when it actually wanted to write the DDRSS_V2A_CTL_REG and DDRSS_ECC_CTRL_REG registers. This patch adds a third register property "ddrss", uses that for the DDRSS wrapper, and continues to use the "cfg" property for the actual controller configuration registers. The "cfg" register space was also configured too small at 16 KB. The TRMs say the range is 32KB, and the PHY registers actually start at the 16KB offset. Signed-off-by: Dominic Rath <rath(a)ibv-augsburg.net> --- arch/arm/dts/k3-am64-ddr.dtsi | 5 +++-- arch/arm/dts/k3-j721e-ddr.dtsi | 5 +++-- drivers/ram/k3-ddrss/k3-ddrss.c | 12 ++++++++++-- 3 files changed, 16 insertions(+), 6 deletions(-) diff --git a/arch/arm/dts/k3-am64-ddr.dtsi b/arch/arm/dts/k3-am64-ddr.dtsi index 026a547f0e..967bd55e75 100644 --- a/arch/arm/dts/k3-am64-ddr.dtsi +++ b/arch/arm/dts/k3-am64-ddr.dtsi @@ -6,9 +6,10 @@ / { memorycontroller: memorycontroller@f300000 { compatible = "ti,am64-ddrss"; - reg = <0x00 0x0f308000 0x00 0x4000>, + reg = <0x00 0x0f300000 0x00 0x200>, + <0x00 0x0f308000 0x00 0x8000>, <0x00 0x43014000 0x00 0x100>; - reg-names = "cfg", "ctrl_mmr_lp4"; + reg-names = "ddrss", "cfg", "ctrl_mmr_lp4"; power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>, <&k3_pds 55 TI_SCI_PD_SHARED>; clocks = <&k3_clks 138 0>, <&k3_clks 16 4>; diff --git a/arch/arm/dts/k3-j721e-ddr.dtsi b/arch/arm/dts/k3-j721e-ddr.dtsi index 21d63802a5..8f1b792849 100644 --- a/arch/arm/dts/k3-j721e-ddr.dtsi +++ b/arch/arm/dts/k3-j721e-ddr.dtsi @@ -6,9 +6,10 @@ / { memorycontroller: memorycontroller@0298e000 { compatible = "ti,j721e-ddrss"; - reg = <0x0 0x02990000 0x0 0x4000>, + reg = <0x0 0x02980000 0x0 0x200>, + <0x0 0x02990000 0x0 0x8000>, <0x0 0x0114000 0x0 0x100>; - reg-names = "cfg", "ctrl_mmr_lp4"; + reg-names = "ddrss", "cfg", "ctrl_mmr_lp4"; power-domains = <&k3_pds 47 TI_SCI_PD_SHARED>, <&k3_pds 90 TI_SCI_PD_SHARED>; clocks = <&k3_clks 47 2>, <&k3_clks 30 9>; diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 261ba64506..7e2a4c5811 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -105,6 +105,7 @@ struct k3_msmc { struct k3_ddrss_desc { struct udevice *dev; void __iomem *ddrss_ss_cfg; + void __iomem *ddrss_ctrl_cfg; void __iomem *ddrss_ctrl_mmr; struct power_domain ddrcfg_pwrdmn; struct power_domain ddrdata_pwrdmn; @@ -314,13 +315,20 @@ static int k3_ddrss_ofdata_to_priv(struct udevice *dev) debug("%s(dev=%p)\n", __func__, dev); - reg = dev_read_addr_name(dev, "cfg"); + reg = dev_read_addr_name(dev, "ddrss"); if (reg == FDT_ADDR_T_NONE) { dev_err(dev, "No reg property for DDRSS wrapper logic\n"); return -EINVAL; } ddrss->ddrss_ss_cfg = (void *)reg; + reg = dev_read_addr_name(dev, "cfg"); + if (reg == FDT_ADDR_T_NONE) { + dev_err(dev, "No reg property for controller registers\n"); + return -EINVAL; + } + ddrss->ddrss_ctrl_cfg = (void *)reg; + reg = dev_read_addr_name(dev, "ctrl_mmr_lp4"); if (reg == FDT_ADDR_T_NONE) { dev_err(dev, "No reg property for CTRL MMR\n"); @@ -403,7 +411,7 @@ void k3_lpddr4_init(struct k3_ddrss_desc *ddrss) hang(); } - config->ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg; + config->ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ctrl_cfg; config->infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler; status = driverdt->init(pd, config); -- 2.35.1

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[PATCH v3 1/2] ARM: dts: at91: rename sama7g5ek.dts to at91-sama7g5ek.dts
by Eugen Hristev 22 Mar '22

22 Mar '22

In Linux this DT file is named at91-sama7g5ek.dts. Rename it accordingly. Signed-off-by: Eugen Hristev <eugen.hristev(a)microchip.com> --- arch/arm/dts/Makefile | 2 +- .../dts/{sama7g5ek-u-boot.dtsi => at91-sama7g5ek-u-boot.dtsi} | 3 ++- arch/arm/dts/{sama7g5ek.dts => at91-sama7g5ek.dts} | 2 +- configs/sama7g5ek_mmc1_defconfig | 2 +- configs/sama7g5ek_mmc_defconfig | 2 +- 5 files changed, 6 insertions(+), 5 deletions(-) rename arch/arm/dts/{sama7g5ek-u-boot.dtsi => at91-sama7g5ek-u-boot.dtsi} (89%) rename arch/arm/dts/{sama7g5ek.dts => at91-sama7g5ek.dts} (99%) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 960f1a9fd4..771115dc53 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1044,7 +1044,7 @@ dtb-$(CONFIG_TARGET_OMAP5_UEVM) += \ omap5-uevm.dtb dtb-$(CONFIG_TARGET_SAMA7G5EK) += \ - sama7g5ek.dtb + at91-sama7g5ek.dtb dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \ at91-sama5d2_ptc_ek.dtb diff --git a/arch/arm/dts/sama7g5ek-u-boot.dtsi b/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi similarity index 89% rename from arch/arm/dts/sama7g5ek-u-boot.dtsi rename to arch/arm/dts/at91-sama7g5ek-u-boot.dtsi index 5e1a0d53a5..652464f1e8 100644 --- a/arch/arm/dts/sama7g5ek-u-boot.dtsi +++ b/arch/arm/dts/at91-sama7g5ek-u-boot.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * sama7g5ek-u-boot.dts - Device Tree file for SAMA7G5 SoC u-boot properties. + * at91-sama7g5ek-u-boot.dtsi - Device Tree file for SAMA7G5 SoC u-boot + * properties. * * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries * diff --git a/arch/arm/dts/sama7g5ek.dts b/arch/arm/dts/at91-sama7g5ek.dts similarity index 99% rename from arch/arm/dts/sama7g5ek.dts rename to arch/arm/dts/at91-sama7g5ek.dts index ac6f23f64e..38b3245751 100644 --- a/arch/arm/dts/sama7g5ek.dts +++ b/arch/arm/dts/at91-sama7g5ek.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * sama7g5ek.dts - Device Tree file for SAMA7G5 EK + * at91-sama7g5ek.dts - Device Tree file for SAMA7G5 EK * SAMA7G5 Evaluation Kit * * Copyright (c) 2020, Microchip Technology Inc. diff --git a/configs/sama7g5ek_mmc1_defconfig b/configs/sama7g5ek_mmc1_defconfig index 15a5c54e75..2da3fd0e68 100644 --- a/configs/sama7g5ek_mmc1_defconfig +++ b/configs/sama7g5ek_mmc1_defconfig @@ -8,7 +8,7 @@ CONFIG_SYS_MEMTEST_START=0x60000000 CONFIG_SYS_MEMTEST_END=0x70000000 CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="sama7g5ek" +CONFIG_DEFAULT_DEVICE_TREE="at91-sama7g5ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xe1824200 CONFIG_DEBUG_UART_CLOCK=200000000 diff --git a/configs/sama7g5ek_mmc_defconfig b/configs/sama7g5ek_mmc_defconfig index 7abd5c8a38..a33f794494 100644 --- a/configs/sama7g5ek_mmc_defconfig +++ b/configs/sama7g5ek_mmc_defconfig @@ -8,7 +8,7 @@ CONFIG_SYS_MEMTEST_START=0x60000000 CONFIG_SYS_MEMTEST_END=0x70000000 CONFIG_ENV_SIZE=0x4000 CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="sama7g5ek" +CONFIG_DEFAULT_DEVICE_TREE="at91-sama7g5ek" CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xe1824200 CONFIG_DEBUG_UART_CLOCK=200000000 -- 2.25.1

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[PATCH] board: at91: sama5d2: set blue led on at boot time
by Eugen Hristev 22 Mar '22

22 Mar '22

From: Mihai Sain <mihai.sain(a)microchip.com> Set blue led on at boot time in order to highlight that u-boot is loaded. This is done for all sama5d2 based boards which contain an RGB led. Signed-off-by: Mihai Sain <mihai.sain(a)microchip.com> --- board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c | 9 +++++++++ board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 9 +++++++++ board/atmel/sama5d2_icp/sama5d2_icp.c | 9 +++++++++ board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c | 9 +++++++++ board/atmel/sama5d2_xplained/sama5d2_xplained.c | 9 +++++++++ 5 files changed, 45 insertions(+) diff --git a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c index 8c0cf3da54..b69f1c8cfa 100644 --- a/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c +++ b/board/atmel/sama5d27_som1_ek/sama5d27_som1_ek.c @@ -22,6 +22,13 @@ extern void at91_pda_detect(void); DECLARE_GLOBAL_DATA_PTR; +static void rgb_leds_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 10, 0); /* LED RED */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 1, 0); /* LED GREEN */ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 31, 1); /* LED BLUE */ +} + #ifdef CONFIG_CMD_USB static void board_usb_hw_init(void) { @@ -71,6 +78,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + rgb_leds_init(); + #ifdef CONFIG_CMD_USB board_usb_hw_init(); #endif diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 32d51bba7d..67ada27072 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -22,6 +22,13 @@ extern void at91_pda_detect(void); DECLARE_GLOBAL_DATA_PTR; +static void rgb_leds_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 6, 0); /* LED RED */ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 7, 0); /* LED GREEN */ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 8, 1); /* LED BLUE */ +} + #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { @@ -64,6 +71,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + rgb_leds_init(); + return 0; } diff --git a/board/atmel/sama5d2_icp/sama5d2_icp.c b/board/atmel/sama5d2_icp/sama5d2_icp.c index 3f33fcfc46..da697a7b0f 100644 --- a/board/atmel/sama5d2_icp/sama5d2_icp.c +++ b/board/atmel/sama5d2_icp/sama5d2_icp.c @@ -19,6 +19,13 @@ DECLARE_GLOBAL_DATA_PTR; +static void rgb_leds_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 0, 0); /* LED RED */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 1, 0); /* LED GREEN */ + atmel_pio4_set_pio_output(AT91_PIO_PORTA, 31, 1); /* LED BLUE */ +} + int board_late_init(void) { return 0; @@ -52,6 +59,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + rgb_leds_init(); + return 0; } diff --git a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c index 2a2439c53a..cca5bd1d8a 100644 --- a/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c +++ b/board/atmel/sama5d2_ptc_ek/sama5d2_ptc_ek.c @@ -25,6 +25,13 @@ extern void at91_pda_detect(void); DECLARE_GLOBAL_DATA_PTR; +static void rgb_leds_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 0); /* LED RED */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 8, 0); /* LED GREEN */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 6, 1); /* LED BLUE */ +} + #ifdef CONFIG_NAND_ATMEL static void board_nand_hw_init(void) { @@ -113,6 +120,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + rgb_leds_init(); + #ifdef CONFIG_NAND_ATMEL board_nand_hw_init(); #endif diff --git a/board/atmel/sama5d2_xplained/sama5d2_xplained.c b/board/atmel/sama5d2_xplained/sama5d2_xplained.c index 8b5cd533d0..4bbb05c2fb 100644 --- a/board/atmel/sama5d2_xplained/sama5d2_xplained.c +++ b/board/atmel/sama5d2_xplained/sama5d2_xplained.c @@ -21,6 +21,13 @@ extern void at91_pda_detect(void); DECLARE_GLOBAL_DATA_PTR; +static void rgb_leds_init(void) +{ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 6, 1); /* LED RED */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 5, 1); /* LED GREEN */ + atmel_pio4_set_pio_output(AT91_PIO_PORTB, 0, 0); /* LED BLUE */ +} + #ifdef CONFIG_CMD_USB static void board_usb_hw_init(void) { @@ -70,6 +77,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + rgb_leds_init(); + #ifdef CONFIG_CMD_USB board_usb_hw_init(); #endif -- 2.25.1

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[PATCH 0/4] Add support for sam9x60_curiosity
by Durai Manickam KR 22 Mar '22

22 Mar '22

This patch series adds support for sam9x60_curiosity. Durai Manickam KR (4): board: Add sam9x60_curiosity support ARM: dts: Add device tree files for sam9x60_curiosity configs: Add sam9x60_curiosity_mmc_defconfig configs: Add sam9x60_curiosity_nandflash_defconfig arch/arm/dts/Makefile | 2 + .../dts/at91-sam9x60_curiosity-u-boot.dtsi | 79 ++++++++++ arch/arm/dts/at91-sam9x60_curiosity.dts | 74 ++++++++++ arch/arm/mach-at91/Kconfig | 10 ++ board/atmel/sam9x60_curiosity/Kconfig | 15 ++ board/atmel/sam9x60_curiosity/MAINTAINERS | 8 + board/atmel/sam9x60_curiosity/Makefile | 7 + .../sam9x60_curiosity/sam9x60_curiosity.c | 139 ++++++++++++++++++ configs/sam9x60_curiosity_mmc_defconfig | 82 +++++++++++ configs/sam9x60_curiosity_nandflash_defconfig | 82 +++++++++++ include/configs/sam9x60_curiosity.h | 67 +++++++++ 11 files changed, 565 insertions(+) create mode 100644 arch/arm/dts/at91-sam9x60_curiosity-u-boot.dtsi create mode 100644 arch/arm/dts/at91-sam9x60_curiosity.dts create mode 100644 board/atmel/sam9x60_curiosity/Kconfig create mode 100644 board/atmel/sam9x60_curiosity/MAINTAINERS create mode 100644 board/atmel/sam9x60_curiosity/Makefile create mode 100644 board/atmel/sam9x60_curiosity/sam9x60_curiosity.c create mode 100644 configs/sam9x60_curiosity_mmc_defconfig create mode 100644 configs/sam9x60_curiosity_nandflash_defconfig create mode 100644 include/configs/sam9x60_curiosity.h -- 2.25.1

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[PATCH v6] wdt: nuvoton: Add support for Nuvoton
by Jim Liu 22 Mar '22

22 Mar '22

Add watchdog controller driver for NPCM7xx/npcm8xx Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> Reviewed-by: Stefan Roese <sr(a)denx.de> Reviewed-by: Simon Glass <sjg(a)chromium.org> Changes for v2: - coding style cleanup - change register type from struct Changes for v3: - remove common.h Changes for v4: - add a bit of detail about the device in Kconfig - lower-case hex change - remove the reset function delay. Actually when setting writel(NPCM_WTR )the watchdog is resetting the BMC changes for v5: - modify compatible name to support all NPCM SOC changes for v6: - followed linux kernel to modify compatible name --- drivers/watchdog/Kconfig | 8 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/npcm_wdt.c | 116 ++++++++++++++++++++++++++++++++++++ 3 files changed, 125 insertions(+) create mode 100644 drivers/watchdog/npcm_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index f90f0ca02b..d33882fb6a 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -196,6 +196,14 @@ config WDT_MTK The watchdog timer is stopped when initialized. It performs full SoC reset. +config WDT_NPCM + bool "Nuvoton watchdog timer support" + depends on WDT && ARCH_NPCM + help + This enables Nuvoton npcm7xx/npcm8xx watchdog timer driver, + The watchdog timer is stopped when initialized. + It performs full SoC reset. + config WDT_OCTEONTX bool "OcteonTX core watchdog support" depends on WDT && (ARCH_OCTEONTX || ARCH_OCTEONTX2) diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index a35bd559f5..1089cd21f5 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o obj-$(CONFIG_WDT_MTK) += mtk_wdt.o +obj-$(CONFIG_WDT_NPCM) += npcm_wdt.o obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c new file mode 100644 index 0000000000..256020f5d3 --- /dev/null +++ b/drivers/watchdog/npcm_wdt.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Nuvoton Technology, Inc + */ + +#include <dm.h> +#include <errno.h> +#include <log.h> +#include <wdt.h> +#include <asm/io.h> +#include <linux/delay.h> +#include <linux/err.h> + +#define NPCM_WTCLK (BIT(10) | BIT(11)) /* Clock divider */ +#define NPCM_WTE BIT(7) /* Enable */ +#define NPCM_WTIE BIT(6) /* Enable irq */ +#define NPCM_WTIS (BIT(4) | BIT(5)) /* Interval selection */ +#define NPCM_WTIF BIT(3) /* Interrupt flag*/ +#define NPCM_WTRF BIT(2) /* Reset flag */ +#define NPCM_WTRE BIT(1) /* Reset enable */ +#define NPCM_WTR BIT(0) /* Reset counter */ + +struct npcm_wdt_priv { + void __iomem *regs; +}; + +static int npcm_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + struct npcm_wdt_priv *priv = dev_get_priv(dev); + u32 time_out, val; + + time_out = (u32)(timeout_ms) / 1000; + if (time_out < 2) + val = 0x800; + else if (time_out < 3) + val = 0x420; + else if (time_out < 6) + val = 0x810; + else if (time_out < 11) + val = 0x430; + else if (time_out < 22) + val = 0x820; + else if (time_out < 44) + val = 0xc00; + else if (time_out < 87) + val = 0x830; + else if (time_out < 173) + val = 0xc10; + else if (time_out < 688) + val = 0xc20; + else + val = 0xc30; + + val |= NPCM_WTRE | NPCM_WTE | NPCM_WTR | NPCM_WTIE; + writel(val, priv->regs); + + return 0; +} + +static int npcm_wdt_stop(struct udevice *dev) +{ + struct npcm_wdt_priv *priv = dev_get_priv(dev); + + writel(0, priv->regs); + + return 0; +} + +static int npcm_wdt_reset(struct udevice *dev) +{ + struct npcm_wdt_priv *priv = dev_get_priv(dev); + + writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, priv->regs); + + return 0; +} + +static int npcm_wdt_of_to_plat(struct udevice *dev) +{ + struct npcm_wdt_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) + return -EINVAL; + + return 0; +} + +static const struct wdt_ops npcm_wdt_ops = { + .start = npcm_wdt_start, + .reset = npcm_wdt_reset, + .stop = npcm_wdt_stop, +}; + +static const struct udevice_id npcm_wdt_ids[] = { + { .compatible = "nuvoton,npcm750-wdt" }, + { } +}; + +static int npcm_wdt_probe(struct udevice *dev) +{ + debug("%s() wdt%u\n", __func__, dev_seq(dev)); + npcm_wdt_stop(dev); + + return 0; +} + +U_BOOT_DRIVER(npcm_wdt) = { + .name = "npcm_wdt", + .id = UCLASS_WDT, + .of_match = npcm_wdt_ids, + .probe = npcm_wdt_probe, + .priv_auto = sizeof(struct npcm_wdt_priv), + .of_to_plat = npcm_wdt_of_to_plat, + .ops = &npcm_wdt_ops, +}; -- 2.17.1

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[PATCH v2 0/3] malloc: Enable profiling dlmalloc with valgrind
by Sean Anderson 22 Mar '22

22 Mar '22

This series adds support for running valgrind against U-Boot's internal malloc. This allows for much more useful reports to be generated. Changes in v2: - Fix one branch of rEALLOc missing a VALGRING_*_BLOCK call - Add some additional suppressions for cALLOc and rEALLOc - Simplify calloc clearing logic - Drop incorrect sbrk patch Sean Anderson (3): Add valgrind headers to U-Boot malloc: Annotate allocator for valgrind doc: sandbox: Document how to run sandbox with valgrind Kconfig | 14 + Licenses/README | 1 + Licenses/bzip2-1.0.6.txt | 30 + common/dlmalloc.c | 35 +- common/malloc_simple.c | 10 + doc/arch/sandbox.rst | 14 +- include/malloc.h | 4 + include/valgrind/memcheck.h | 251 ++ include/valgrind/valgrind.h | 7106 +++++++++++++++++++++++++++++++++++ scripts/u-boot.supp | 53 + 10 files changed, 7513 insertions(+), 5 deletions(-) create mode 100644 Licenses/bzip2-1.0.6.txt create mode 100644 include/valgrind/memcheck.h create mode 100644 include/valgrind/valgrind.h create mode 100644 scripts/u-boot.supp -- 2.31.0

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[PATCH] board: kontron: increase the CONFIG_SYS_MALLOC_F_LEN
by Heiko Thiery 21 Mar '22

21 Mar '22

Signed-off-by: Heiko Thiery <heiko.thiery(a)gmail.com> --- configs/kontron_pitx_imx8m_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig index 76430213e3..30c3586937 100644 --- a/configs/kontron_pitx_imx8m_defconfig +++ b/configs/kontron_pitx_imx8m_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_IMX8M=y CONFIG_SYS_TEXT_BASE=0x40200000 CONFIG_SYS_MALLOC_LEN=0x600000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -- 2.30.2

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[PATCH 0/2] sunxi: Fix Ethernet on mostly A20 boards
by Andre Przywara 21 Mar '22

21 Mar '22

Hi, testing on a BananaPi M1 board revealed that Ethernet has regressed since the last release due to not only one, but two bugs: - The pinmux and GMAC clock setup for the A20 GMAC is apparently called too early now. - The updated RGMII phy-mode properties are now taken for real, so many boards are using the wrong RX/TX line delay setup, with mostly fatal consequences. Fix those two issues to bring Ethernet back on those affected boards. I refrained from just syncing the DTs from the kernel (to fix the second issue): Recent changes in the mainline DTs require newer kernels to work, which breaks Linux distro installer ISO images running via UEFI. We need to find a solution for that, but not in -rc4, which would be rather late for a normal DT sync anyway. Please have a look and test on your board! Cheers, Andre Andre Przywara (2): sunxi: Fix old GMAC pinmux setup sunxi: dts: Update RGMII phy-mode properties arch/arm/dts/sun50i-a64-sopine-baseboard.dts | 2 +- arch/arm/dts/sun50i-h5-nanopi-neo2.dts | 2 +- arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts | 2 +- arch/arm/dts/sun6i-a31-hummingbird.dts | 2 +- arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts | 2 +- arch/arm/dts/sun7i-a20-bananapi.dts | 2 +- arch/arm/dts/sun7i-a20-bananapro.dts | 2 +- arch/arm/dts/sun7i-a20-cubietruck.dts | 2 +- arch/arm/dts/sun7i-a20-olinuxino-lime2.dts | 2 +- arch/arm/dts/sun7i-a20-pcduino3-nano.dts | 2 +- arch/arm/dts/sun8i-a83t-bananapi-m3.dts | 2 +- arch/arm/dts/sun8i-a83t-cubietruck-plus.dts | 2 +- arch/arm/dts/sun8i-h3-orangepi-plus.dts | 2 +- arch/arm/dts/sunxi-bananapi-m2-plus.dtsi | 2 +- arch/arm/mach-sunxi/board.c | 1 - board/sunxi/board.c | 3 +++ 16 files changed, 17 insertions(+), 15 deletions(-) -- 2.35.1

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[PATCH v3 0/3] EFI: Use sysreset instead of reset command
by Masami Hiramatsu 21 Mar '22

21 Mar '22

Hi, Here is the 3rd version of the series to use sysreset instead of do_reset command interface for resetting after capsule update on disk. This change requires EFI capsule update on disk to depends on sysreset. This adds two fixes from the previous patch: - [1/3] Disable 'capsule disk-update' of efidebug command when CONFIG_EFI_CAPSULE_ON_DISK is disabled. - [2/3] Make efi_load_capsule_drivers() available even if the CONFIG_EFI_CAPSULE_ON_DISK is disabled. And add Reviewed-by from Simon and Heinrich to [3/3]. Thank you, --- Masami Hiramatsu (3): cmd: efidebug: Disable 'capsule disk-update' when CONFIG_EFI_CAPSULE_ON_DISK=n efi_loader: Make efi_load_capsule_drivers() available even if EFI_CAPSULE_ON_DISK=n efi_loader: Use sysreset instead of reset command cmd/efidebug.c | 4 +++ lib/efi_loader/Kconfig | 1 + lib/efi_loader/efi_capsule.c | 65 +++++++++++++++++++++--------------------- 3 files changed, 38 insertions(+), 32 deletions(-) -- Masami Hiramatsu <masami.hiramatsu(a)linaro.org>

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