March 2022 - U-Boot

[PATCH] i2c: fix always-true condition in i2c_probe_chip()
by Nikita Yushchenko 23 Mar '22

23 Mar '22

Per dm_i2c_ops.probe_chip documentation, i2c_probe_chip() shall fallback to default probe method when .probe_chip() returns -ENOSYS. Signed-off-by: Nikita Yushchenko <nikita.yoush(a)cogentembedded.com> --- drivers/i2c/i2c-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index 5539becc19..335911c46b 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -280,7 +280,7 @@ static int i2c_probe_chip(struct udevice *bus, uint chip_addr, if (ops->probe_chip) { ret = ops->probe_chip(bus, chip_addr, chip_flags); - if (!ret || ret != -ENOSYS) + if (ret != -ENOSYS) return ret; } -- 2.30.2

2 2

[PATCH 1/2] mmc: fix error message for unaligned erase request
by Patrick Delaunay 23 Mar '22

23 Mar '22

Fix the end address in the message for unaligned erase request in mmc_berase() when start + blkcnt is aligned to erase_grp_size. for example: - start = 0x2000 - 26 - count = 26 - erase_grp_size = 0x400 Caution! Your devices Erase group is 0x400 The erase range would be change to 0x2000~0x27ff But no issue when the end address is not aligned, for example - start = 0x2000 - 2 * 26 - count = 26 - erase_grp_size = 0x400 Caution! Your devices Erase group is 0x400 The erase range would be change to 0x2000~0x23ff Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- drivers/mmc/mmc_write.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c index d23b7d9729..eab94c7b60 100644 --- a/drivers/mmc/mmc_write.c +++ b/drivers/mmc/mmc_write.c @@ -102,7 +102,7 @@ ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt) "The erase range would be change to " "0x" LBAF "~0x" LBAF "\n\n", mmc->erase_grp_size, start & ~(mmc->erase_grp_size - 1), - ((start + blkcnt + mmc->erase_grp_size) + ((start + blkcnt + mmc->erase_grp_size - 1) & ~(mmc->erase_grp_size - 1)) - 1); while (blk < blkcnt) { -- 2.25.1

3 4

Re: QEMU NUMA and U-Boot
by Heinrich Schuchardt 23 Mar '22

23 Mar '22

On 7/6/21 6:13 PM, François Ozog wrote: > Hi Heinrich, U-Boot 2021-07rc5 does not take into account memory > description when using Qemu 5.2 NUMA configuration to adapt memory map > (kernel_addr_r...): > > -smp 4 \ > -m 8G,slots=2,maxmem=16G \ > -object memory-backend-ram,size=4G,id=m0 \ > -object memory-backend-ram,size=4G,id=m1 \ > -numa node,cpus=0-1,nodeid=0,memdev=m0 \ > -numa node,cpus=2-3,nodeid=1,memdev=m1 > > kernel_addr_r is still 0x4040000 and thus you can't use it to bootefi. > > fdt addr 0x13ede6de0; fdt print > > Displays fdt while I think it should not. > > If I load the kernel at dram.start, the load works but not boot > > U-Boot 2021.07 (Jul 06 2021 - 13:26:43 +0000) > > > DRAM:4 GiB > > Flash: 64 MiB > > Loading Environment from Flash... OK > > In:pl011@9000000 > > Out: pl011@9000000 > > Err: pl011@9000000 > > Net: eth0: virtio-net#32 > > Hit any key to stop autoboot:0 > > => > > => bdinfo > > boot_params = 0x0000000000000000 > > DRAM bank = 0x0000000000000000 > > -> start= 0x0000000140000000 > > -> size = 0x0000000100000000 > > flashstart= 0x0000000000000000 > > flashsize = 0x0000000004000000 > > flashoffset = 0x00000000000bc990 > > baudrate= 115200 bps > > relocaddr = 0x000000013ff27000 > > reloc off = 0x000000013ff27000 > > Build = 64-bit > > current eth = virtio-net#32 > > ethaddr = 52:52:52:52:52:52 > > IP addr = <NULL> > > fdt_blob= 0x000000013ede6de0 > > new_fdt = 0x000000013ede6de0 > > fdt_size= 0x0000000000100000 > > lmb_dump_all: > > memory.cnt= 0x1 > > memory.reg[0x0].base = 0x140000000 > > .size = 0x100000000 > > > reserved.cnt= 0x0 > > arch_number = 0x0000000000000000 > > TLB addr= 0x000000013fff0000 > > irq_sp= 0x000000013ede6dd0 > > sp start= 0x000000013ede6dd0 > > Early malloc usage: 3a8 / 2000 > > => load virtio 0:1 0x140000000 /oskit.efi > > 853424 bytes read in 1 ms (813.9 MiB/s) > > => bootefi0x140000000 0x13ede6dd0 > > ERROR: Failed to register WaitForKey event > > Setting OsIndications failed > > Error: Cannot initialize UEFI sub-system, r = 9 > > > I think there is a need to calculate memory map based on previous > firmware (TFA, QEMU can be considered as previous frimware) information > (DT or blob_list). > > What do you think ? > > Cheers > > FF > > -- > > François-Frédéric Ozog | /Director Business Development/ > T: +33.67221.6485 > francois.ozog(a)linaro.org <mailto:francois.ozog@linaro.org> | Skype: ffozog > > The kernel load address is hard coded here: include/configs/qemu-arm.h:41: "kernel_addr_r=0x40400000\0" \ bdinfo shows: DRAM start = 0x140000000 DRAM size = 0x100000000 fdt addr $fdt_addr fdt printf shows two memory areas. One at 40000000, one at 140000000. Your use case is well beyond the typical U-Boot usage. So I guess it will be up to Linaro to provide the necessary patches: * determine the active CPU * determine the RAM assigned to the active CPU according to the numa-node-id in the device-tree * make sure that U-Boot only uses the memory of the active CPU internally * make sure that the UEFI memory map contains a compliant description * possibly, dynamically set up the environment variables +CC Tuomas Tynkkynen (maintainer for qemu_arm64_defconfig) Best regards Heinrich

4 12

[PATCH] arm: kirkwood: Sheevaplug : Use Marvell uclass mvgbe and PHY driver for Ethernet
by Tony Dinh 23 Mar '22

23 Mar '22

The Globalscale Technologies Sheevaplug board has the network chip Marvell 88E1116R. Use uclass mvgbe and the compatible driver M88E1310 driver to bring up Ethernet. - Currently, CONFIG_RESET_PHY_R symbol is used in arch/arm/mach-kirkwood/include/mach/config.h for all Kirkwood boards with mv8831116 PHY, with each board defines the function reset_phy(). Undefine it for this board. - Add board_eth_init() to use uclass mvgbe to bring up the network. And remove ad-hoc code. - Enable CONFIG_PHY_MARVELL to properly configure the network. - Miscellaneous changes: Move constants to .c file and remove header file board/Marvell/sheevaplug/sheevaplug.h, use BIT macro, and add/cleanup comments. Signed-off-by: Tony Dinh <mibodhi(a)gmail.com> --- board/Marvell/sheevaplug/sheevaplug.c | 83 +++++---------------------- board/Marvell/sheevaplug/sheevaplug.h | 24 -------- configs/sheevaplug_defconfig | 1 + include/configs/sheevaplug.h | 17 +++--- 4 files changed, 22 insertions(+), 103 deletions(-) delete mode 100644 board/Marvell/sheevaplug/sheevaplug.h diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c index 5952d158b2..26ee39ef77 100644 --- a/board/Marvell/sheevaplug/sheevaplug.c +++ b/board/Marvell/sheevaplug/sheevaplug.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2021 Tony Dinh <mibodhi(a)gmail.com> + * Copyright (C) 2021-2022 Tony Dinh <mibodhi(a)gmail.com> * (C) Copyright 2009 * Marvell Semiconductor <www.marvell.com> * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> @@ -8,17 +8,21 @@ #include <common.h> #include <init.h> -#include <miiphy.h> -#include <net.h> +#include <netdev.h> #include <asm/global_data.h> #include <asm/mach-types.h> #include <asm/arch/cpu.h> #include <asm/arch/soc.h> #include <asm/arch/mpp.h> -#include "sheevaplug.h" +#include <linux/bitops.h> DECLARE_GLOBAL_DATA_PTR; +#define SHEEVAPLUG_OE_LOW (~(0)) +#define SHEEVAPLUG_OE_HIGH (~(0)) +#define SHEEVAPLUG_OE_VAL_LOW BIT(29) /* USB_PWEN low */ +#define SHEEVAPLUG_OE_VAL_HIGH BIT(17) /* LED pin high */ + int board_early_init_f(void) { /* @@ -88,6 +92,11 @@ int board_early_init_f(void) return 0; } +int board_eth_init(struct bd_info *bis) +{ + return cpu_eth_init(bis); +} + int board_init(void) { /* @@ -95,72 +104,8 @@ int board_init(void) */ gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG; - /* adress of boot parameters */ + /* address of boot parameters */ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; return 0; } - -static int fdt_get_phy_addr(const char *path) -{ - const void *fdt = gd->fdt_blob; - const u32 *reg; - const u32 *val; - int node, phandle, addr; - - /* Find the node by its full path */ - node = fdt_path_offset(fdt, path); - if (node >= 0) { - /* Look up phy-handle */ - val = fdt_getprop(fdt, node, "phy-handle", NULL); - if (val) { - phandle = fdt32_to_cpu(*val); - if (!phandle) - return -1; - /* Follow it to its node */ - node = fdt_node_offset_by_phandle(fdt, phandle); - if (node) { - /* Look up reg */ - reg = fdt_getprop(fdt, node, "reg", NULL); - if (reg) { - addr = fdt32_to_cpu(*reg); - return addr; - } - } - } - } - return -1; -} - -#ifdef CONFIG_RESET_PHY_R -/* Configure and enable MV88E1116 PHY */ -void reset_phy(void) -{ - u16 reg; - int phyaddr; - char *name = "ethernet-controller@72000"; - char *eth0_path = "/ocp@f1000000/ethernet-controller@72000/ethernet0-port@0"; - - if (miiphy_set_current_dev(name)) - return; - - phyaddr = fdt_get_phy_addr(eth0_path); - if (phyaddr < 0) - return; - - /* - * Enable RGMII delay on Tx and Rx for CPU port - * Ref: sec 4.7.2 of chip datasheet - */ - miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 2); - miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg); - reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); - miiphy_write(name, phyaddr, MV88E1116_MAC_CTRL_REG, reg); - miiphy_write(name, phyaddr, MV88E1116_PGADR_REG, 0); - - /* reset the phy */ - miiphy_reset(name, phyaddr); - - printf("88E1116 Initialized on %s\n", name); -} -#endif /* CONFIG_RESET_PHY_R */ diff --git a/board/Marvell/sheevaplug/sheevaplug.h b/board/Marvell/sheevaplug/sheevaplug.h deleted file mode 100644 index e026c1b53b..0000000000 --- a/board/Marvell/sheevaplug/sheevaplug.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> - */ - -#ifndef __SHEEVAPLUG_H -#define __SHEEVAPLUG_H - -#define SHEEVAPLUG_OE_LOW (~(0)) -#define SHEEVAPLUG_OE_HIGH (~(0)) -#define SHEEVAPLUG_OE_VAL_LOW (1 << 29) /* USB_PWEN low */ -#define SHEEVAPLUG_OE_VAL_HIGH (1 << 17) /* LED pin high */ - -/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) - -#endif /* __SHEEVAPLUG_H */ diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index 0c5031b2d2..41bf1065b0 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -50,6 +50,7 @@ CONFIG_SYS_SATA_MAX_DEVICE=2 CONFIG_MVEBU_MMC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y +CONFIG_PHY_MARVELL=y CONFIG_DM_ETH=y CONFIG_MVGBE=y CONFIG_MII=y diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h index 4499a63aed..276c134a20 100644 --- a/include/configs/sheevaplug.h +++ b/include/configs/sheevaplug.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * (C) Copyright 2022 Tony Dinh <mibodhi(a)gmail.com> * (C) Copyright 2009-2014 * Gerald Kerma <dreagle(a)doukki.net> * Marvell Semiconductor <www.marvell.com> @@ -11,13 +12,6 @@ #include "mv-common.h" -/* - * Environment variables configurations - */ -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ /* * Environment is right behind U-Boot in flash. Make sure U-Boot * doesn't grow into the environment area. @@ -29,7 +23,7 @@ */ #define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ - "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS_DEFAULT \ + "=ttyS0,115200 mtdparts=" CONFIG_MTDPARTS_DEFAULT \ "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \ "x_bootcmd_usb=usb start\0" \ "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" @@ -37,13 +31,16 @@ /* * Ethernet Driver configuration */ -#ifdef CONFIG_CMD_NET #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ #define CONFIG_PHY_BASE_ADR 0 -#endif /* CONFIG_CMD_NET */ +#ifdef CONFIG_RESET_PHY_R +#undef CONFIG_RESET_PHY_R /* remove legacy reset_phy() */ +#endif /* * SATA driver configuration + * + * The original Sheevaplug board does not have eSATA, so allow SATA to be disabled. */ #ifdef CONFIG_SATA #define CONFIG_LBA48 -- 2.30.2

3 9

[PATCH v7] wdt: nuvoton: Add support for Nuvoton
by Jim Liu 23 Mar '22

23 Mar '22

Add watchdog controller driver for NPCM7xx/npcm8xx Signed-off-by: Jim Liu <JJLIU0(a)nuvoton.com> Reviewed-by: Stefan Roese <sr(a)denx.de> Reviewed-by: Simon Glass <sjg(a)chromium.org> Changes for v2: - coding style cleanup - change register type from struct Changes for v3: - remove common.h Changes for v4: - add a bit of detail about the device in Kconfig - lower-case hex change - remove the reset function delay. Actually when setting writel(NPCM_WTR )the watchdog is resetting the BMC changes for v5: - modify compatible name to support all NPCM SOC changes for v6: - followed linux kernel to modify compatible name change for v7: - add second compatible name to driver --- drivers/watchdog/Kconfig | 8 +++ drivers/watchdog/Makefile | 1 + drivers/watchdog/npcm_wdt.c | 117 ++++++++++++++++++++++++++++++++++++ 3 files changed, 126 insertions(+) create mode 100644 drivers/watchdog/npcm_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index f90f0ca02b..d33882fb6a 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -196,6 +196,14 @@ config WDT_MTK The watchdog timer is stopped when initialized. It performs full SoC reset. +config WDT_NPCM + bool "Nuvoton watchdog timer support" + depends on WDT && ARCH_NPCM + help + This enables Nuvoton npcm7xx/npcm8xx watchdog timer driver, + The watchdog timer is stopped when initialized. + It performs full SoC reset. + config WDT_OCTEONTX bool "OcteonTX core watchdog support" depends on WDT && (ARCH_OCTEONTX || ARCH_OCTEONTX2) diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index a35bd559f5..1089cd21f5 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_WDT_MPC8xx) += mpc8xx_wdt.o obj-$(CONFIG_WDT_MT7620) += mt7620_wdt.o obj-$(CONFIG_WDT_MT7621) += mt7621_wdt.o obj-$(CONFIG_WDT_MTK) += mtk_wdt.o +obj-$(CONFIG_WDT_NPCM) += npcm_wdt.o obj-$(CONFIG_WDT_OCTEONTX) += octeontx_wdt.o obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c new file mode 100644 index 0000000000..0aedb2fbe7 --- /dev/null +++ b/drivers/watchdog/npcm_wdt.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2022 Nuvoton Technology, Inc + */ + +#include <dm.h> +#include <errno.h> +#include <log.h> +#include <wdt.h> +#include <asm/io.h> +#include <linux/delay.h> +#include <linux/err.h> + +#define NPCM_WTCLK (BIT(10) | BIT(11)) /* Clock divider */ +#define NPCM_WTE BIT(7) /* Enable */ +#define NPCM_WTIE BIT(6) /* Enable irq */ +#define NPCM_WTIS (BIT(4) | BIT(5)) /* Interval selection */ +#define NPCM_WTIF BIT(3) /* Interrupt flag*/ +#define NPCM_WTRF BIT(2) /* Reset flag */ +#define NPCM_WTRE BIT(1) /* Reset enable */ +#define NPCM_WTR BIT(0) /* Reset counter */ + +struct npcm_wdt_priv { + void __iomem *regs; +}; + +static int npcm_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags) +{ + struct npcm_wdt_priv *priv = dev_get_priv(dev); + u32 time_out, val; + + time_out = (u32)(timeout_ms) / 1000; + if (time_out < 2) + val = 0x800; + else if (time_out < 3) + val = 0x420; + else if (time_out < 6) + val = 0x810; + else if (time_out < 11) + val = 0x430; + else if (time_out < 22) + val = 0x820; + else if (time_out < 44) + val = 0xc00; + else if (time_out < 87) + val = 0x830; + else if (time_out < 173) + val = 0xc10; + else if (time_out < 688) + val = 0xc20; + else + val = 0xc30; + + val |= NPCM_WTRE | NPCM_WTE | NPCM_WTR | NPCM_WTIE; + writel(val, priv->regs); + + return 0; +} + +static int npcm_wdt_stop(struct udevice *dev) +{ + struct npcm_wdt_priv *priv = dev_get_priv(dev); + + writel(0, priv->regs); + + return 0; +} + +static int npcm_wdt_reset(struct udevice *dev) +{ + struct npcm_wdt_priv *priv = dev_get_priv(dev); + + writel(NPCM_WTR | NPCM_WTRE | NPCM_WTE, priv->regs); + + return 0; +} + +static int npcm_wdt_of_to_plat(struct udevice *dev) +{ + struct npcm_wdt_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) + return -EINVAL; + + return 0; +} + +static const struct wdt_ops npcm_wdt_ops = { + .start = npcm_wdt_start, + .reset = npcm_wdt_reset, + .stop = npcm_wdt_stop, +}; + +static const struct udevice_id npcm_wdt_ids[] = { + { .compatible = "nuvoton,npcm750-wdt" }, + { .compatible = "nuvoton,npcm845-wdt" }, + { } +}; + +static int npcm_wdt_probe(struct udevice *dev) +{ + debug("%s() wdt%u\n", __func__, dev_seq(dev)); + npcm_wdt_stop(dev); + + return 0; +} + +U_BOOT_DRIVER(npcm_wdt) = { + .name = "npcm_wdt", + .id = UCLASS_WDT, + .of_match = npcm_wdt_ids, + .probe = npcm_wdt_probe, + .priv_auto = sizeof(struct npcm_wdt_priv), + .of_to_plat = npcm_wdt_of_to_plat, + .ops = &npcm_wdt_ops, +}; -- 2.17.1

4 3

[PATCH] image-fdt: save name of FIT configuration in '/chosen' node
by Daniel Golle 22 Mar '22

22 Mar '22

It can be useful for the OS (Linux) to know which configuration has been chosen by U-Boot when launching a FIT image. Store the name of the FIT configuration node used in a new string attribute called 'bootconf' in the '/chosen' node in device tree. Signed-off-by: Daniel Golle <daniel(a)makrotopia.org> --- boot/image-fdt.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/boot/image-fdt.c b/boot/image-fdt.c index 692a9ad3e4..4017bc94a6 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -601,6 +601,12 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, goto err; } + /* Store name of configuration node as bootconf in /chosen node */ + if (images->fit_uname_cfg) + fdt_find_and_setprop(blob, "/chosen", "bootconf", + images->fit_uname_cfg, + strlen(images->fit_uname_cfg) + 1, 1); + /* Update ethernet nodes */ fdt_fixup_ethernet(blob); #if CONFIG_IS_ENABLED(CMD_PSTORE) -- 2.35.1

2 4

[PATCH v2] dm: Add docs to explain how to enable DM_SERIAL for a board
by Simon Glass 22 Mar '22

22 Mar '22

This is an attempt to cover the common cases found when enabling driver model for serial on a new board. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: - Add an example patch - Mention removing old code that is not used doc/develop/driver-model/serial-howto.rst | 152 ++++++++++++++++++++++ 1 file changed, 152 insertions(+) diff --git a/doc/develop/driver-model/serial-howto.rst b/doc/develop/driver-model/serial-howto.rst index 1469131124b..e595049c0a3 100644 --- a/doc/develop/driver-model/serial-howto.rst +++ b/doc/develop/driver-model/serial-howto.rst @@ -44,3 +44,155 @@ this involves these steps: - build and get u-boot-dtb.bin so you can test it - Your drivers can now use device tree - For device tree in SPL, define CONFIG_SPL_OF_CONTROL + + +Converting boards to CONFIG_DM_SERIAL +------------------------------------- + +If your SoC has a serial driver that uses driver model (has U_BOOT_DRIVER() in +it) then you may still find that your board has not been converted. To convert +your board, enable the option and see if you can get it working. + +Firstly you will have a lot more success if you have a method of debugging your +board, such as a JTAG connection. Failing that the debug UART is useful, +although since you are trying to get the UART driver running, it will interfere +with your efforts eventually. + +Secondly, while the UART is a relatively simple peripheral, it may need quite a +few pieces to be up and running before it will work, such as the correct pin +muxing, clocks, power domains and possibly even GPIOs, if an external +transceiver is used. Look at other boards that use the same SoC, for clues as to +what is needed. + +Thirdly, when added tags, put them in a xxx-u-boot.dtsi file, where xxx is your +board name, or SoC name. There may already be a file for your SoC which contains +what you need. U-Boot automatically includes these files: see :ref:`dttweaks`. + +Here are some things you might need to consider: + +1. The serial driver itself needs to be present before relocation, so that the +U-Boot banner appears. Make sure it has a u-boot,pre-reloc tag in the device +tree, so that the serial driver is bound when U-Boot starts. + +For example, on iMX8:: + + lpuart3: serial@5a090000 { + compatible = "fsl,imx8qm-lpuart"; + ... + }; + +put this in your xxx-u-boot.dtsi file:: + + &lpuart3 { + u-boot,dm-pre-proper; + }; + +2. If your serial port requires a particular pinmux configuration, you may need +a pinctrl driver. This needs to have a u-boot,pre-reloc tag also. Take care that +any subnodes have the same tag, if they are needed to make the correct pinctrl +available. + +For example, on RK3288, the UART2 uses uart2_xfer:: + + uart2: serial@ff690000 { + ... + pinctrl-0 = <&uart2_xfer>; + }; + +which is defined as follows:: + + pinctrl: pinctrl { + compatible = "rockchip,rk3228-pinctrl"; + + uart2: uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_up>, + <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>; + }; + + ... + }; + +This means you must make the uart2-xfer node available as well as all its +parents, so put this in your xxx-u-boot.dtsi file:: + + &pinctrl { + u-boot,dm-pre-reloc; + }; + + &uart2 { + u-boot,dm-pre-reloc; + }; + + &uart2_xfer { + u-boot,dm-pre-reloc; + }; + +3. The same applies to power domains. For example, if a particular power domain +must be enabled for the serial port to work, you need to ensure it is available +before relocation: + +For example, on iMX8, put this in your xxx-u-boot.dtsi file:: + + &pd_dma { + u-boot,dm-pre-proper; + }; + + &pd_dma_lpuart3 { + u-boot,dm-pre-proper; + }; + +4. The same applies to clocks, in the same way. Make sure that when your driver +requests a clock, typically with clk_get_by_index(), it is available. + + +Generally a failure to find a required device will cause an error which you can +catch, if you have the debug UART working. U-Boot outputs serial data to the +debug UART until the point where the real serial driver takes over. This point +is marked by gd->flags having the GD_FLG_SERIAL_READY flag set. This change +happens in serial_init() in serial-uclass.c so until that point the debug UART +is used. You can see the relevant code in putc() +, for example:: + + /* if we don't have a console yet, use the debug UART */ + if (IS_ENABLED(CONFIG_DEBUG_UART) && !(gd->flags & GD_FLG_SERIAL_READY)) { + printch(c); + return; + } + ... carries on to use the console / serial driver + +Note that in device_probe() the call to pinctrl_select_state() silently fails +if the pinctrl driver fails. You can add a temporary check there if needed. + +Why do we have all these tags? The problem is that before relocation we don't +want to bind all the drivers since memory is limited and the CPU may be running +at a slow speed. So many boards will fail to boot without this optimisation, or +may take a long time to start up (e.g. hundreds of milliseconds). The tags tell +U-Boot which drivers to bind. + +The good news is that this problem is normally solved by the SoC, so that any +boards that use it will work as normal. But in some cases there are multiple +UARTs or multiple pinmux options, which means that each board may need to do +some customisation. + +Serial in SPL +------------- + +A similar process is needed in SPL, but in this case the u-boot,dm-spl or +u-boot,dm-tpl tags are used. Add these in the same way as above, to ensure that +the SPL device tree contains the required nodes (see spl/u-boot-spl.dtb for +what it actually contains). + +Removing old code +----------------- + +In some cases there may be initialisation code that is no-longer needed when +driver model is used, such as setting up the pin muxing, or enabling a clock. +Be sure to remove this. + +Example patch +------------- + +See this serial_patch_ for iMX7. + +.. _serial_patch: https://patchwork.ozlabs.org/project/uboot/patch/20220314232406.1945308-1-f… -- 2.35.1.723.g4982287a31-goog

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[PATCH v5 0/3] Add a clock driver for the imx8mq
by Angus Ainslie 22 Mar '22

22 Mar '22

This is a DM clock driver for the imx8mq based on the linux kernel driver and the u-boot imx8mm clock driver. It also removes some code duplication in the imx8m[nmp] clock drivers. Changes since V4 Rebased onto [1] so patch 4 of 4 was dropped. Added CLK_COMPOSITE_CCF Fixed const* clock definitions Changes since v3: Fixed driver spelling Moved rate macros out of the header into the dot c Changes since v2: Added kernel commit IDs Re-factored rate table code to remove duplication Remove duplicate code by creating a common clk-imx8m Changes since v1: More verbose clock driver description Added forgotten dt-bindings Synced PLL frequencies with mainline kernel [1] https://patchwork.ozlabs.org/project/uboot/patch/20220320203446.740178-2-se… Angus Ainslie (3): dt-bindings: imx8mq-clock: add mainline definitions clk: imx8mq: Add a clock driver for the imx8mq clk: imx8m: reduce rate table duplication drivers/clk/imx/Kconfig | 18 + drivers/clk/imx/Makefile | 2 + drivers/clk/imx/clk-imx8mm.c | 60 +--- drivers/clk/imx/clk-imx8mn.c | 60 +--- drivers/clk/imx/clk-imx8mp.c | 65 +--- drivers/clk/imx/clk-imx8mq.c | 440 +++++++++++++++++++++++ drivers/clk/imx/clk-pll14xx.c | 61 ++++ drivers/clk/imx/clk.h | 4 + include/dt-bindings/clock/imx8mq-clock.h | 16 +- 9 files changed, 560 insertions(+), 166 deletions(-) create mode 100644 drivers/clk/imx/clk-imx8mq.c -- 2.25.1

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[PATCH] mtd: mxs_nand: default to legacy bch and rename to modern bch option
by Sean Nyekjaer 22 Mar '22

22 Mar '22

Linux kernel defaults to use legacy bch setting, this was creating a mismatch between U-boot and Linux default settings. Fixes: 51cdf83eea ("mtd: gpmi: provide the option to use legacy bch geometry") Signed-off-by: Sean Nyekjaer <sean(a)geanix.com> --- drivers/mtd/nand/raw/mxs_nand.c | 2 +- drivers/mtd/nand/raw/mxs_nand_dt.c | 2 +- include/mxs_nand.h | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index e6bbfac4d6..49795e20d2 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -1119,7 +1119,7 @@ static int mxs_nand_set_geometry(struct mtd_info *mtd, struct bch_geometry *geo) } if ((!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0) && - mtd->oobsize < 1024) || nand_info->legacy_bch_geometry) { + mtd->oobsize < 1024) || !nand_info->modern_bch_geometry) { dev_warn(mtd->dev, "use legacy bch geometry\n"); return mxs_nand_legacy_calc_ecc_layout(geo, mtd); } diff --git a/drivers/mtd/nand/raw/mxs_nand_dt.c b/drivers/mtd/nand/raw/mxs_nand_dt.c index 878796d555..bbb7396324 100644 --- a/drivers/mtd/nand/raw/mxs_nand_dt.c +++ b/drivers/mtd/nand/raw/mxs_nand_dt.c @@ -92,7 +92,7 @@ static int mxs_nand_dt_probe(struct udevice *dev) info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc"); - info->legacy_bch_geometry = dev_read_bool(dev, "fsl,legacy-bch-geometry"); + info->modern_bch_geometry = dev_read_bool(dev, "fsl,modern-bch-geometry"); if (IS_ENABLED(CONFIG_CLK) && IS_ENABLED(CONFIG_IMX8)) { /* Assigned clock already set clock */ diff --git a/include/mxs_nand.h b/include/mxs_nand.h index c0cefaca90..7e254d6b31 100644 --- a/include/mxs_nand.h +++ b/include/mxs_nand.h @@ -43,8 +43,8 @@ struct mxs_nand_info { struct udevice *dev; unsigned int max_ecc_strength_supported; bool use_minimum_ecc; - /* legacy bch geometry flag */ - bool legacy_bch_geometry; + /* modern bch geometry flag */ + bool modern_bch_geometry; int cur_chip; uint32_t cmd_queue_len; -- 2.31.0

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[PATCH 0/4] Add support for sam9x60_curiosity
by Durai Manickam KR 22 Mar '22

22 Mar '22

This patch series adds support for sam9x60_curiosity. Durai Manickam KR (4): board: Add sam9x60_curiosity support ARM: dts: Add device tree files for sam9x60_curiosity configs: Add sam9x60_curiosity_mmc_defconfig configs: Add sam9x60_curiosity_nandflash_defconfig arch/arm/dts/Makefile | 2 + .../dts/at91-sam9x60_curiosity-u-boot.dtsi | 79 ++++++++++ arch/arm/dts/at91-sam9x60_curiosity.dts | 74 ++++++++++ arch/arm/mach-at91/Kconfig | 7 + board/atmel/sam9x60_curiosity/Kconfig | 15 ++ board/atmel/sam9x60_curiosity/MAINTAINERS | 8 + board/atmel/sam9x60_curiosity/Makefile | 7 + .../sam9x60_curiosity/sam9x60_curiosity.c | 139 ++++++++++++++++++ configs/sam9x60_curiosity_mmc_defconfig | 82 +++++++++++ configs/sam9x60_curiosity_nandflash_defconfig | 82 +++++++++++ include/configs/sam9x60_curiosity.h | 67 +++++++++ 11 files changed, 562 insertions(+) create mode 100644 arch/arm/dts/at91-sam9x60_curiosity-u-boot.dtsi create mode 100644 arch/arm/dts/at91-sam9x60_curiosity.dts create mode 100644 board/atmel/sam9x60_curiosity/Kconfig create mode 100644 board/atmel/sam9x60_curiosity/MAINTAINERS create mode 100644 board/atmel/sam9x60_curiosity/Makefile create mode 100644 board/atmel/sam9x60_curiosity/sam9x60_curiosity.c create mode 100644 configs/sam9x60_curiosity_mmc_defconfig create mode 100644 configs/sam9x60_curiosity_nandflash_defconfig create mode 100644 include/configs/sam9x60_curiosity.h -- 2.25.1

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