March 2022 - U-Boot

[PATCH] efi_loader: Expose relocated address for gdb debugging purposes
by Alexander von Gluck IV 24 Mar '22

24 Mar '22

* If users want to debug EFI applications via qemu + GDB, they need to know the relocated address of the application to align their symbols to in GDB via add-symbol-file. * This exposes where EFI applications are relocated to enable debugging EFI applications via qemu + gdb * Usage is generally determining the address, then add-symbol-file (efi loader) (address) * The address can change, but is generally consistent with the same qemu version and u-boot binary. (allowing you to boot once, find the address, then reboot with qemu -s -S --- lib/efi_loader/efi_image_loader.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c index 773bd0677c..2b8c1ef464 100644 --- a/lib/efi_loader/efi_image_loader.c +++ b/lib/efi_loader/efi_image_loader.c @@ -906,6 +906,8 @@ efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle, ret = EFI_OUT_OF_RESOURCES; goto err; } + log_info("64-bit EFI image loaded at relocated address %p\n", efi_reloc); + handle->entry = efi_reloc + opt->AddressOfEntryPoint; rel_size = opt->DataDirectory[rel_idx].Size; rel = efi_reloc + opt->DataDirectory[rel_idx].VirtualAddress; @@ -922,6 +924,8 @@ efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle, ret = EFI_OUT_OF_RESOURCES; goto err; } + log_info("32-bit EFI image loaded at relocated address %p\n", efi_reloc); + handle->entry = efi_reloc + opt->AddressOfEntryPoint; rel_size = opt->DataDirectory[rel_idx].Size; rel = efi_reloc + opt->DataDirectory[rel_idx].VirtualAddress; -- 2.35.1

3 3

[PATCH u-boot-marvell] arm: a37xx: espressobin: Fix non-working SPI
by Pali Rohár 24 Mar '22

24 Mar '22

Commit 0934dddc6436 ("arm: a37xx: Update DTS files to version from upstream Linux kernel") ported Linux's device-tree files for Armada 3720 SOCs. This broke SPI support on some Espressobin boards and results in following U-Boot error: Loading Environment from SPIFlash... jedec_spi_nor flash@0: unrecognized JEDEC id bytes: f7, 30, 0b *** Warning - spi_flash_probe_bus_cs() failed, using default environment Before that commit DT node for SPI was called 'spi-flash@0' and after that commit it is called 'flash@0'. Before that commit 'spi-max-frequency' was set to 50000000 and after it is 104000000. Rename DT node 'spi-flash@0 in armada-3720-espressobin-u-boot.dtsi to 'flash@0' and set custom U-Boot 'spi-max-frequency' back to 50000000. With this change SPI is working on Espressobin again and it is detected with JEDEC ids ef, 60, 16 on our tested unit. Loading Environment from SPIFlash... SF: Detected w25q32dw with page size 256 Bytes, erase size 4 KiB, total 4 MiB OK Note that it is unknown why spi-max-frequency with value 104000000 does not work in U-Boot as it works fine with Linux kernel. Also note that in defconfig file configs/mvebu_espressobin-88f3720_defconfig is set option CONFIG_SF_DEFAULT_SPEED=40000000 which is different value than in DT. Fixes: 0934dddc6436 ("arm: a37xx: Update DTS files to version from upstream Linux kernel") Signed-off-by: Pali Rohár <pali(a)kernel.org> --- Hello Stefan, like with USB3.0 port on Turris MOX, this is SPI regression on Espressobin in U-Boot 2022.04. Could you send this fix to master to have SPI working in U-Boot 2022.04? I do not know what is wrong with SPI frequency and we have different value in defconfig and different value in DTS file and another value in kernel DTS file. So the best for now is to stick with old value which was used in U-Boot. I have tested also Turris MOX with current U-Boot from master branch and it does not have any issue with SPI, like Espressobin. --- arch/arm/dts/armada-3720-espressobin-u-boot.dtsi | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/armada-3720-espressobin-u-boot.dtsi b/arch/arm/dts/armada-3720-espressobin-u-boot.dtsi index 3e01c64a4bdb..2ffdc65e9f47 100644 --- a/arch/arm/dts/armada-3720-espressobin-u-boot.dtsi +++ b/arch/arm/dts/armada-3720-espressobin-u-boot.dtsi @@ -1,8 +1,15 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH &spi0 { - spi-flash@0 { + flash@0 { + /* + * For some unknown reason U-Boot SPI driver cannot access + * SPI-NOR with higher frequency. Linux kernel SPI driver + * does not have this problem. + */ + spi-max-frequency = <50000000>; + +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH partitions { compatible = "fixed-partitions"; #address-cells = <1>; @@ -19,8 +26,8 @@ }; }; }; -}; #endif +}; /* * U-Boot requires to have this eMMC node by default in "okay" status. U-Boot -- 2.20.1

2 6

[RFC] Dumping load addresses - bootefi qemu gdb remote debugging
by Alex 24 Mar '22

24 Mar '22

Good morning! So, some time ago I wrote a short guide on how to debug EFI bootloaders started by u-boot in qemu. https://www.haiku-os.org/blog/kallisti5/2021-01-17_debugging_riscv-64_bootl… At the time it worked, however figuring the elf load addresses from u-boot was extremely difficult and required compiling it with full tracing and taking guesses at various EFI: Entry efi_load_image messages until I found the correct address. Is there an easier way to find the load addresses? If not, a more verbose message on non-debug builds might be extremely useful here. "positioning image at address 0xfe6b0000" or something using the leveraged kernel_addr_r (0x84000000) was not enough. -- Alex

3 2

[PATCH v3 0/8] tpm: rng: Move TPM RNG functionality to driver model
by Sughosh Ganu 24 Mar '22

24 Mar '22

The TPM device provides the random number generator(RNG) functionality, whereby sending a command to the TPM device results in the TPM device responding with random bytes. There was a discussion on the mailing list earlier[1], where it was explained that platforms with a TPM device can install the EFI_RNG_PROTOCOL for getting the random bytes instead of populating the dtb with the kaslr-seed property. That would make it possible to measure the dtb. This patchset moves the already existing functions for getting random bytes from the TPM device to drivers complying with the RNG uclass. This is done since the EFI_RNG_PROTOCOL's get_rng routine uses the RNG uclass's dm_rng_read api to get the random bytes. The TPM uclass driver adds the RNG child device as part of it's post_probe function. The TPM uclass driver's child_pre_probe function initialises the TPM parent device for use -- this enables the RNG child device to be used subsequently. Some additional changes have also been made to facilitate the use of the RNG devices, including extending the 'rng' command to take the RNG device as one of the command-line parameters. This series depends on a patch[2] from Simon Glass for moving the TPM device version detection functions to the tpm_api.h header as static inline functions. Using this patch, a couple of patches[3][4] from the series are no longer needed. [1] - https://lore.kernel.org/u-boot/20220103120738.47835-1-ilias.apalodimas@lina… [2] - https://lore.kernel.org/u-boot/20220301001125.1554442-2-sjg@chromium.org/T/… [3] - https://lore.kernel.org/u-boot/20220228120638.678137-7-sughosh.ganu@linaro.… [4] - https://lore.kernel.org/u-boot/20220228120638.678137-6-sughosh.ganu@linaro.… Changes since V2: * Export the existing tpm*_get_random functions to the driver model instead of moving them to the drivers/rng/ directory. * Enable DM_RNG when CONFIG_TPM is enabled to build the RNG uclass code * Additional patch for a document for the 'rng' command as suggested by Simon Glass * Additional patch for unit test for the 'rng' command as suggested by Simon Glass Sughosh Ganu (8): tpm: rng: Change tpm_get_random to return an int tpm: Fix the return type of tpm_startup tpm: rng: Add driver model interface for TPM RNG device tpm: Add the RNG child device qemu: arm: Remove platform specific function to get RNG device cmd: rng: Add support for selecting RNG device doc: rng: Add documentation for the rng command test: rng: Add a UT testcase for the rng command board/emulation/qemu-arm/qemu-arm.c | 42 -------------------- cmd/Kconfig | 1 + cmd/rng.c | 31 +++++++++++---- doc/usage/index.rst | 1 + doc/usage/rng.rst | 25 ++++++++++++ drivers/tpm/tpm-uclass.c | 60 +++++++++++++++++++++++++++-- include/tpm-v1.h | 4 +- include/tpm-v2.h | 4 +- include/tpm_api.h | 6 +-- lib/Kconfig | 1 + lib/tpm-v1.c | 28 ++++++++++---- lib/tpm-v2.c | 21 +++++++--- lib/tpm_api.c | 28 +++++++++++--- test/dm/rng.c | 29 ++++++++++++++ 14 files changed, 201 insertions(+), 80 deletions(-) create mode 100644 doc/usage/rng.rst -- 2.25.1

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[RESEND PATCH] gpio: rgpio2p: Enhance reading of GPIO pin value
by Christoph Fritz 24 Mar '22

24 Mar '22

Add support for reading GPIO pin value when function is output. With this patch applied, gpio toggle command is working. Signed-off-by: Christoph Fritz <chf.fritz(a)googlemail.com> Cc: Fabio Estevam <festevam(a)gmail.com> Reviewed-by: Peng Fan <peng.fan(a)nxp.com> --- drivers/gpio/imx_rgpio2p.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/imx_rgpio2p.c b/drivers/gpio/imx_rgpio2p.c index 0e2874ca95c..175e460aff5 100644 --- a/drivers/gpio/imx_rgpio2p.c +++ b/drivers/gpio/imx_rgpio2p.c @@ -39,6 +39,14 @@ static int imx_rgpio2p_is_output(struct gpio_regs *regs, int offset) return val & (1 << offset) ? 1 : 0; } +static int imx_rgpio2p_bank_get_direction(struct gpio_regs *regs, int offset) +{ + if ((readl(&regs->gpio_pddr) >> offset) & 0x01) + return IMX_RGPIO2P_DIRECTION_OUT; + + return IMX_RGPIO2P_DIRECTION_IN; +} + static void imx_rgpio2p_bank_direction(struct gpio_regs *regs, int offset, enum imx_rgpio2p_direction direction) { @@ -67,7 +75,11 @@ static void imx_rgpio2p_bank_set_value(struct gpio_regs *regs, int offset, static int imx_rgpio2p_bank_get_value(struct gpio_regs *regs, int offset) { - return (readl(&regs->gpio_pdir) >> offset) & 0x01; + if (imx_rgpio2p_bank_get_direction(regs, offset) == + IMX_RGPIO2P_DIRECTION_IN) + return (readl(&regs->gpio_pdir) >> offset) & 0x01; + + return (readl(&regs->gpio_pdor) >> offset) & 0x01; } static int imx_rgpio2p_direction_input(struct udevice *dev, unsigned offset) -- 2.30.2

2 1

[PATCH v3 0/9] imx8mm: add pwm-imx backlight support
by Tommaso Merciai 24 Mar '22

24 Mar '22

Hi, This series add support for pwm/backlight on i.MX8MM evk, separe also CONFIG_DM_PWM pwm-imx implementation from non dm implementation moving pwm-imx-util into pwm-imx with driver refactoring. 1. add pwm ctrl registers fields for i.MX8MM SOC 2. add pwm_regs struct for i.MX8MM SOC 3. add pwm clocks support for i.MX8MM SOC 4. move pwm-imx-util into pwm-imx 5. get and enable per/ipg clock using dm 6. introduce pwm_dm_imx_get_parms 7. separe dm from non dm implementation into pwm-imx driver 8. add pwm1/backlight dts support for imx8mm_evk 9. add pwm backlight configs support for imx8mm_evk Tommaso Merciai (9): arch: mach-imx: imx8m: add pwm ctrl registers fields defines arch: mach-imx: imx8m: add pwm_regs struct in imx-regs clk: imx8mm: add pwm clocks support drivers: pwm: pwm-imx: move pwm-imx-util into pwm-imx driver: pwm: pwm-imx: get and enable per/ipg clock using dm driver: pwm: pwm-imx: introduce pwm_dm_imx_get_parms driver: pwm: pwm-imx: separe dm from non dm implementation arm: dts: imx8mm_evk: add pwm1/backlight support configs: imx8mm_evk: add pwm backlight support arch/arm/dts/imx8mm-evk.dtsi | 21 +++ arch/arm/include/asm/arch-imx8m/imx-regs.h | 17 +++ configs/imx8mm_evk_defconfig | 5 + drivers/clk/imx/clk-imx8mm.c | 28 ++++ drivers/pwm/Makefile | 2 +- drivers/pwm/pwm-imx-util.c | 80 ----------- drivers/pwm/pwm-imx-util.h | 15 -- drivers/pwm/pwm-imx.c | 155 +++++++++++++++++++-- 8 files changed, 213 insertions(+), 110 deletions(-) delete mode 100644 drivers/pwm/pwm-imx-util.c delete mode 100644 drivers/pwm/pwm-imx-util.h -- 2.25.1

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[PATCH 1/3] rng: add OP-TEE based Random Number Generator
by Patrick Delaunay 24 Mar '22

24 Mar '22

Add driver for OP-TEE based Random Number Generator on ARM SoCs where hardware entropy sources are not accessible to normal world and the RNG service is provided by a HWRNG Trusted Application (TA). This driver is based on the linux driver: char/hw_random/optee-rng.c Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- MAINTAINERS | 1 + drivers/rng/Kconfig | 8 +++ drivers/rng/Makefile | 1 + drivers/rng/optee_rng.c | 156 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 166 insertions(+) create mode 100644 drivers/rng/optee_rng.c diff --git a/MAINTAINERS b/MAINTAINERS index f25ca7cd00..3356c65dd0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -481,6 +481,7 @@ F: drivers/power/regulator/stpmic1.c F: drivers/ram/stm32mp1/ F: drivers/remoteproc/stm32_copro.c F: drivers/reset/stm32-reset.c +F: drivers/rng/optee_rng.c F: drivers/rng/stm32mp1_rng.c F: drivers/rtc/stm32_rtc.c F: drivers/serial/serial_stm32.* diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig index b1c5ab93d1..a02c585f61 100644 --- a/drivers/rng/Kconfig +++ b/drivers/rng/Kconfig @@ -31,6 +31,14 @@ config RNG_MSM This driver provides support for the Random Number Generator hardware found on Qualcomm SoCs. +config RNG_OPTEE + bool "OP-TEE based Random Number Generator support" + depends on DM_RNG && OPTEE + help + This driver provides support for OP-TEE based Random Number + Generator on ARM SoCs where hardware entropy sources are not + accessible to normal world. + config RNG_STM32MP1 bool "Enable random number generator for STM32MP1" depends on ARCH_STM32MP diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile index 39f7ee3f03..435b3b965a 100644 --- a/drivers/rng/Makefile +++ b/drivers/rng/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_DM_RNG) += rng-uclass.o obj-$(CONFIG_RNG_MESON) += meson-rng.o obj-$(CONFIG_RNG_SANDBOX) += sandbox_rng.o obj-$(CONFIG_RNG_MSM) += msm_rng.o +obj-$(CONFIG_RNG_OPTEE) += optee_rng.o obj-$(CONFIG_RNG_STM32MP1) += stm32mp1_rng.o obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o diff --git a/drivers/rng/optee_rng.c b/drivers/rng/optee_rng.c new file mode 100644 index 0000000000..a0833d0862 --- /dev/null +++ b/drivers/rng/optee_rng.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ +#define LOG_CATEGORY UCLASS_RNG + +#include <common.h> + +#include <rng.h> +#include <tee.h> +#include <dm/device.h> +#include <dm/device_compat.h> +#include <linux/sizes.h> + +#define TEE_ERROR_HEALTH_TEST_FAIL 0x00000001 + +/* + * TA_CMD_GET_ENTROPY - Get Entropy from RNG + * + * param[0] (inout memref) - Entropy buffer memory reference + * param[1] unused + * param[2] unused + * param[3] unused + * + * Result: + * TEE_SUCCESS - Invoke command success + * TEE_ERROR_BAD_PARAMETERS - Incorrect input param + * TEE_ERROR_NOT_SUPPORTED - Requested entropy size greater than size of pool + * TEE_ERROR_HEALTH_TEST_FAIL - Continuous health testing failed + */ +#define TA_CMD_GET_ENTROPY 0x0 + +#define MAX_ENTROPY_REQ_SZ SZ_4K + +#define TA_HWRNG_UUID { 0xab7a617c, 0xb8e7, 0x4d8f, \ + { 0x83, 0x01, 0xd0, 0x9b, 0x61, 0x03, 0x6b, 0x64 } } + +/** + * struct optee_rng_priv - OP-TEE Random Number Generator private data + * @session_id: RNG TA session identifier. + */ +struct optee_rng_priv { + u32 session_id; +}; + +static int get_optee_rng_data(struct udevice *dev, + struct tee_shm *entropy_shm_pool, + void *buf, size_t *size) +{ + struct optee_rng_priv *priv = dev_get_priv(dev); + int ret = 0; + struct tee_invoke_arg arg; + struct tee_param param; + + memset(&arg, 0, sizeof(arg)); + memset(&param, 0, sizeof(param)); + + /* Invoke TA_CMD_GET_ENTROPY function of Trusted App */ + arg.func = TA_CMD_GET_ENTROPY; + arg.session = priv->session_id; + + /* Fill invoke cmd params */ + param.attr = TEE_PARAM_ATTR_TYPE_MEMREF_INOUT; + param.u.memref.shm = entropy_shm_pool; + param.u.memref.size = *size; + + ret = tee_invoke_func(dev->parent, &arg, 1, &param); + if (ret || arg.ret) { + if (!ret) + ret = -EPROTO; + dev_err(dev, "TA_CMD_GET_ENTROPY invoke err: %d 0x%x\n", ret, arg.ret); + *size = 0; + + return ret; + } + + memcpy(buf, param.u.memref.shm->addr, param.u.memref.size); + *size = param.u.memref.size; + + return 0; +} + +static int optee_rng_read(struct udevice *dev, void *buf, size_t len) +{ + size_t read = 0, rng_size = 0; + struct tee_shm *entropy_shm_pool; + u8 *data = buf; + int ret; + + ret = tee_shm_alloc(dev->parent, MAX_ENTROPY_REQ_SZ, 0, &entropy_shm_pool); + if (ret) { + dev_err(dev, "tee_shm_alloc failed: %d\n", ret); + return ret; + } + + while (read < len) { + rng_size = min(len - read, (size_t)MAX_ENTROPY_REQ_SZ); + ret = get_optee_rng_data(dev, entropy_shm_pool, data, &rng_size); + if (ret) + goto shm_free; + data += rng_size; + read += rng_size; + } + +shm_free: + tee_shm_free(entropy_shm_pool); + + return ret; +} + +static int optee_rng_probe(struct udevice *dev) +{ + const struct tee_optee_ta_uuid uuid = TA_HWRNG_UUID; + struct optee_rng_priv *priv = dev_get_priv(dev); + struct tee_open_session_arg sess_arg; + int ret; + + memset(&sess_arg, 0, sizeof(sess_arg)); + + /* Open session with hwrng Trusted App */ + tee_optee_ta_uuid_to_octets(sess_arg.uuid, &uuid); + sess_arg.clnt_login = TEE_LOGIN_PUBLIC; + + ret = tee_open_session(dev->parent, &sess_arg, 0, NULL); + if (ret || sess_arg.ret) { + if (!ret) + ret = -EIO; + dev_err(dev, "can't open session: %d 0x%x\n", ret, sess_arg.ret); + return ret; + } + priv->session_id = sess_arg.session; + + return 0; +} + +static int optee_rng_remove(struct udevice *dev) +{ + struct optee_rng_priv *priv = dev_get_priv(dev); + + tee_close_session(dev->parent, priv->session_id); + + return 0; +} + +static const struct dm_rng_ops optee_rng_ops = { + .read = optee_rng_read, +}; + +U_BOOT_DRIVER(optee_rng) = { + .name = "optee-rng", + .id = UCLASS_RNG, + .ops = &optee_rng_ops, + .probe = optee_rng_probe, + .remove = optee_rng_remove, + .priv_auto = sizeof(struct optee_rng_priv), +}; -- 2.25.1

3 5

[PATCH v4 0/4] Add a clock driver for the imx8mq
by Angus Ainslie 24 Mar '22

24 Mar '22

This is a DM clock driver for the imx8mq based on the linux kernel driver and the u-boot imx8mm clock driver. It also removes some code duplication in the imx8m[nmp] clock drivers. Changes since v3: Fixed driver spelling Moved rate macros out of the header into the dot c Changes since v2: Added kernel commit IDs Re-factored rate table code to remove duplication Remove duplicate code by creating a common clk-imx8m Changes since v1: More verbose clock driver description Added forgotten dt-bindings Synced PLL frequencies with mainline kernel Angus Ainslie (4): dt-bindings: imx8mq-clock: add mainline definitions clk: imx8mq: Add a clock driver for the imx8mq clk: imx8m: reduce rate table duplication clk: imx8m: remove code duplication drivers/clk/imx/Kconfig | 16 + drivers/clk/imx/Makefile | 8 +- drivers/clk/imx/clk-imx8m.c | 108 ++++++ drivers/clk/imx/clk-imx8m.h | 12 + drivers/clk/imx/clk-imx8mm.c | 149 +------- drivers/clk/imx/clk-imx8mn.c | 149 +------- drivers/clk/imx/clk-imx8mp.c | 156 +------- drivers/clk/imx/clk-imx8mq.c | 441 +++++++++++++++++++++++ drivers/clk/imx/clk-pll14xx.c | 61 ++++ drivers/clk/imx/clk.h | 4 + include/dt-bindings/clock/imx8mq-clock.h | 16 +- 11 files changed, 688 insertions(+), 432 deletions(-) create mode 100644 drivers/clk/imx/clk-imx8m.c create mode 100644 drivers/clk/imx/clk-imx8m.h create mode 100644 drivers/clk/imx/clk-imx8mq.c -- 2.25.1

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[PATCH v2] mtd: gpmi: fix the bch setting backward compatible issue
by Han Xu 24 Mar '22

24 Mar '22

Previous u-boot code changed the default bch setting behavior and caused backward compatible issue. This fix choose the legacy bch geometry back again as the default option. If the minimum ecc strength that NAND chips required need to be chosen, it can be enabled by either adding DT flag "fsl,use-minimum-ecc" or CONFIG_NAND_MXS_USE_MINIMUM_ECC in configs. The unused flag "fsl,legacy-bch-geometry" get removed. Fixes: 51cdf83eea mtd: gpmi: provide the option to use legacy bch geometry Fixes: 616f03daba mtd: gpmi: change the BCH layout setting for large oob NAND Tested-by: Tim Harvey <tharvey(a)gateworks.com> Signed-off-by: Han Xu <han.xu(a)nxp.com> Changes in v2: -- change the commit log about backward compatible issue is in u-boot -- removed the unused flag -- add fixes and test tag --- drivers/mtd/nand/raw/mxs_nand.c | 71 ++++++++++++++++++++++++++---- drivers/mtd/nand/raw/mxs_nand_dt.c | 2 - include/mxs_nand.h | 2 - 3 files changed, 62 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index 748056a43e..ee5d7fde9c 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -195,6 +195,7 @@ static inline int mxs_nand_legacy_calc_ecc_layout(struct bch_geometry *geo, struct nand_chip *chip = mtd_to_nand(mtd); struct mxs_nand_info *nand_info = nand_get_controller_data(chip); unsigned int block_mark_bit_offset; + int corr, ds_corr; /* The default for the length of Galois Field. */ geo->gf_len = 13; @@ -225,6 +226,17 @@ static inline int mxs_nand_legacy_calc_ecc_layout(struct bch_geometry *geo, geo->ecc_strength = min(round_down(geo->ecc_strength, 2), nand_info->max_ecc_strength_supported); + /* check ecc strength, same as nand_ecc_is_strong_enough() did*/ + if (chip->ecc_step_ds) { + corr = mtd->writesize * geo->ecc_strength / + geo->ecc_chunkn_size; + ds_corr = mtd->writesize * chip->ecc_strength_ds / + chip->ecc_step_ds; + if (corr < ds_corr || + geo->ecc_strength < chip->ecc_strength_ds) + return -EINVAL; + } + block_mark_bit_offset = mtd->writesize * 8 - (geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - 1) + MXS_NAND_METADATA_SIZE * 8); @@ -1111,6 +1123,7 @@ static int mxs_nand_set_geometry(struct mtd_info *mtd, struct bch_geometry *geo) struct nand_chip *chip = mtd_to_nand(mtd); struct nand_chip *nand = mtd_to_nand(mtd); struct mxs_nand_info *nand_info = nand_get_controller_data(nand); + int err; if (chip->ecc_strength_ds > nand_info->max_ecc_strength_supported) { printf("unsupported NAND chip, minimum ecc required %d\n" @@ -1118,19 +1131,57 @@ static int mxs_nand_set_geometry(struct mtd_info *mtd, struct bch_geometry *geo) return -EINVAL; } - if ((!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0) && - mtd->oobsize < 1024) || nand_info->legacy_bch_geometry) { - dev_warn(mtd->dev, "use legacy bch geometry\n"); - return mxs_nand_legacy_calc_ecc_layout(geo, mtd); + /* use the legacy bch setting by default */ + if ((!nand_info->use_minimum_ecc && mtd->oobsize < 1024) || + !(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0)) { + dev_dbg(mtd->dev, "use legacy bch geometry\n"); + err = mxs_nand_legacy_calc_ecc_layout(geo, mtd); + if (!err) + return 0; } - if (mtd->oobsize > 1024 || chip->ecc_step_ds < mtd->oobsize) - return mxs_nand_calc_ecc_for_large_oob(geo, mtd); + /* for large oob nand */ + if (mtd->oobsize > 1024) { + dev_dbg(mtd->dev, "use large oob bch geometry\n"); + err = mxs_nand_calc_ecc_for_large_oob(geo, mtd); + if (!err) + return 0; + } - return mxs_nand_calc_ecc_layout_by_info(geo, mtd, - chip->ecc_strength_ds, chip->ecc_step_ds); + /* otherwise use the minimum ecc nand chips required */ + dev_dbg(mtd->dev, "use minimum ecc bch geometry\n"); + err = mxs_nand_calc_ecc_layout_by_info(geo, mtd, chip->ecc_strength_ds, + chip->ecc_step_ds); - return 0; + if (err) + dev_err(mtd->dev, "none of the bch geometry setting works\n"); + + return err; +} + +void mxs_nand_dump_geo(struct mtd_info *mtd) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct mxs_nand_info *nand_info = nand_get_controller_data(nand); + struct bch_geometry *geo = &nand_info->bch_geometry; + + dev_dbg(mtd->dev, "BCH Geometry :\n" + "GF Length\t\t: %u\n" + "ECC Strength\t\t: %u\n" + "ECC for Meta\t\t: %u\n" + "ECC Chunk0 Size\t\t: %u\n" + "ECC Chunkn Size\t\t: %u\n" + "ECC Chunk Count\t\t: %u\n" + "Block Mark Byte Offset\t: %u\n" + "Block Mark Bit Offset\t: %u\n", + geo->gf_len, + geo->ecc_strength, + geo->ecc_for_meta, + geo->ecc_chunk0_size, + geo->ecc_chunkn_size, + geo->ecc_chunk_count, + geo->block_mark_byte_offset, + geo->block_mark_bit_offset); } /* @@ -1159,6 +1210,8 @@ int mxs_nand_setup_ecc(struct mtd_info *mtd) if (ret) return ret; + mxs_nand_dump_geo(mtd); + /* Configure BCH and set NFC geometry */ mxs_reset_block(&bch_regs->hw_bch_ctrl_reg); diff --git a/drivers/mtd/nand/raw/mxs_nand_dt.c b/drivers/mtd/nand/raw/mxs_nand_dt.c index 878796d555..b9833a646f 100644 --- a/drivers/mtd/nand/raw/mxs_nand_dt.c +++ b/drivers/mtd/nand/raw/mxs_nand_dt.c @@ -92,8 +92,6 @@ static int mxs_nand_dt_probe(struct udevice *dev) info->use_minimum_ecc = dev_read_bool(dev, "fsl,use-minimum-ecc"); - info->legacy_bch_geometry = dev_read_bool(dev, "fsl,legacy-bch-geometry"); - if (IS_ENABLED(CONFIG_CLK) && IS_ENABLED(CONFIG_IMX8)) { /* Assigned clock already set clock */ struct clk gpmi_clk; diff --git a/include/mxs_nand.h b/include/mxs_nand.h index 66c909318d..741dc8734e 100644 --- a/include/mxs_nand.h +++ b/include/mxs_nand.h @@ -44,8 +44,6 @@ struct mxs_nand_info { struct udevice *dev; unsigned int max_ecc_strength_supported; bool use_minimum_ecc; - /* legacy bch geometry flag */ - bool legacy_bch_geometry; int cur_chip; uint32_t cmd_queue_len; -- 2.17.1

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[RFC] serial: mxc: get the clock frequency from the used clock for the device
by Heiko Thiery 24 Mar '22

24 Mar '22

With the clock driver enabled for the imx8mq, it was noticed that the frequency used to calculate the baud rate is always taken from the root clock of UART1. This can cause problems if UART1 is not used as console and the settings are different from UART1. The result is that the console output is garbage. To do this correctly the UART frequency is taken from the used device. For the implementations that don't have the igp clock frequency written or can't return it the old way is tried. Signed-off-by: Heiko Thiery <heiko.thiery(a)gmail.com> --- drivers/serial/serial_mxc.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index e4970a169b..6fdb2b2397 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -3,6 +3,7 @@ * (c) 2007 Sascha Hauer <s.hauer(a)pengutronix.de> */ +#include <clk.h> #include <common.h> #include <dm.h> #include <errno.h> @@ -266,9 +267,19 @@ __weak struct serial_device *default_serial_console(void) int mxc_serial_setbrg(struct udevice *dev, int baudrate) { struct mxc_serial_plat *plat = dev_get_plat(dev); - u32 clk = imx_get_uartclk(); + u32 rate = 0; + + if (IS_ENABLED(CONFIG_CLK)) { + struct clk clk; + if(!clk_get_by_name(dev, "ipg", &clk)) + rate = clk_get_rate(&clk); + } + + /* as fallback we try to get the clk rate that way */ + if (rate == 0) + rate = imx_get_uartclk(); - _mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte); + _mxc_serial_setbrg(plat->reg, rate, baudrate, plat->use_dte); return 0; } -- 2.30.2

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