March 2022 - U-Boot

[PATCH v3 0/3] test: test UEFI boot manager
by Heinrich Schuchardt 26 Mar '22

26 Mar '22

A unit test for the boot manager is provided. In the test a disk images is prepared and bound as device in the sandbox. intrddump.efi is run as boot binary. The CRC32 of the initrd image presented via the EFI_LOAD_FILE2_PROTOCOL is checked. The initrddump.efi application is adjusted to better fit into the Python test framework. The unit test patch was dropped when merging the series "[PATCH v2 0/9] efi_loader: booting via short-form device-path" https://lists.denx.de/pipermail/u-boot/2022-March/478410.html due to test failures caused by initrddump.efi. Heinrich Schuchardt (3): efi_loader: nocolor command line attr for initrddump.efi efi_loader: initrddump: drain input before prompt test: test UEFI boot manager lib/efi_loader/initrddump.c | 91 ++++++++++++++++--- test/py/tests/test_efi_bootmgr/conftest.py | 42 +++++++++ .../test_efi_bootmgr/test_efi_bootmgr.py | 31 +++++++ 3 files changed, 151 insertions(+), 13 deletions(-) create mode 100644 test/py/tests/test_efi_bootmgr/conftest.py create mode 100644 test/py/tests/test_efi_bootmgr/test_efi_bootmgr.py -- 2.34.1

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Pull request: u-boot-sunxi/master fix for v2022.04
by Andre Przywara 26 Mar '22

26 Mar '22

Hi Tom, please pull the master branch from u-boot-sunxi, containing two regression fixes for 2022.04, related to Allwinner networking: ------------------------- - Fix A20 GBit Ethernet operation - Update board .dts files to provide correct RGMII PHY mode ------------------------- Tested on BananaPi M1, Pine64 LTS, and Pine H64. Thanks, Andre =============== The following changes since commit cbc05bba8cb7da62eae65f41e1b0ddbcadc06bba: doc: update doc/sphinx/requirements.txt (2022-03-25 08:59:49 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-sunxi.git master for you to fetch changes up to 85da5587629b12220c2f19ac0780ca8f4c482f16: sunxi: dts: Update RGMII phy-mode properties (2022-03-26 00:16:44 +0000) ---------------------------------------------------------------- Andre Przywara (2): sunxi: Fix old GMAC pinmux setup sunxi: dts: Update RGMII phy-mode properties arch/arm/dts/sun50i-a64-sopine-baseboard.dts | 2 +- arch/arm/dts/sun50i-h5-nanopi-neo2.dts | 2 +- arch/arm/dts/sun50i-h5-orangepi-zero-plus.dts | 2 +- arch/arm/dts/sun6i-a31-hummingbird.dts | 2 +- arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts | 2 +- arch/arm/dts/sun7i-a20-bananapi.dts | 2 +- arch/arm/dts/sun7i-a20-bananapro.dts | 2 +- arch/arm/dts/sun7i-a20-cubietruck.dts | 2 +- arch/arm/dts/sun7i-a20-olinuxino-lime2.dts | 2 +- arch/arm/dts/sun7i-a20-pcduino3-nano.dts | 2 +- arch/arm/dts/sun8i-a83t-bananapi-m3.dts | 2 +- arch/arm/dts/sun8i-a83t-cubietruck-plus.dts | 2 +- arch/arm/dts/sun8i-h3-orangepi-plus.dts | 2 +- arch/arm/dts/sunxi-bananapi-m2-plus.dtsi | 2 +- arch/arm/mach-sunxi/board.c | 1 - board/sunxi/board.c | 3 +++ 16 files changed, 17 insertions(+), 15 deletions(-)

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[PATCH v2 0/2] Add pmic bootcount driver
by Philip Oberfichtner 26 Mar '22

26 Mar '22

This series adds a new bootcount driver. The required register definitions and the actual driver are separated in two patches. Changes in v2: - Migrated bootcount driver to driver model - Introduced error handling. Previously errors were ignored. Philip Oberfichtner (2): power: pfuze100: Add MEMx register definitions bootcount: Add pmic pfuze100 bootcount driver drivers/bootcount/Kconfig | 7 ++ drivers/bootcount/Makefile | 1 + drivers/bootcount/pmic_pfuze100.c | 161 ++++++++++++++++++++++++++++++ include/power/pfuze100_pmic.h | 5 + 4 files changed, 174 insertions(+) create mode 100644 drivers/bootcount/pmic_pfuze100.c -- 2.34.1

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[PATCH 0/3] Support pwm driver for aspeed ast26xx
by Billy Tsai 26 Mar '22

26 Mar '22

This series adds driver support for the PWM controller found in Aspeed's AST2600 BMC SoCs, but isn't compatible with the AST2400 and AST2500. Billy Tsai (3): pwm: Add Aspeed ast2600 PWM support pinctrl: Add the pinctrl setting for PWM. ARM: dts: ast2600: Add PWM to device tree arch/arm/dts/ast2600-evb.dts | 20 ++ arch/arm/dts/ast2600.dtsi | 95 +++++++++ drivers/pinctrl/aspeed/pinctrl_ast2600.c | 120 +++++++++++ drivers/pwm/Kconfig | 8 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-aspeed.c | 251 +++++++++++++++++++++++ 6 files changed, 495 insertions(+) create mode 100644 drivers/pwm/pwm-aspeed.c -- 2.25.1

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[PATCH] cmd: test: pinmux: Do not check all empty spaces
by Michal Simek 26 Mar '22

26 Mar '22

There is really no value to check empty spaces. That's why use ut_assert_nextlinen() instead of ut_assert_nextline(). This change ensures that PINMUX_SIZE can be increased without changing tests. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- https://lore.kernel.org/all/3a6be84c8354f38754a9838670cc0319e84f29e8.164562… --- test/cmd/pinmux.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/test/cmd/pinmux.c b/test/cmd/pinmux.c index 8ae807b53779..ba338b8dce85 100644 --- a/test/cmd/pinmux.c +++ b/test/cmd/pinmux.c @@ -16,18 +16,18 @@ static int dm_test_cmd_pinmux_status_pinname(struct unit_test_state *uts) /* Test that 'pinmux status <pinname>' displays the selected pin. */ console_record_reset(); run_command("pinmux status a5", 0); - ut_assert_nextline("a5 : gpio input . "); + ut_assert_nextlinen("a5 : gpio input ."); ut_assert_console_end(); console_record_reset(); run_command("pinmux status P7", 0); - ut_assert_nextline("P7 : GPIO2 bias-pull-down input-enable. "); + ut_assert_nextlinen("P7 : GPIO2 bias-pull-down input-enable."); ut_assert_console_end(); console_record_reset(); run_command("pinmux status P9", 0); - ut_assert_nextline("single-pinctrl pinctrl-single-no-width: missing register width"); - ut_assert_nextline("P9 not found"); + ut_assert_nextlinen("single-pinctrl pinctrl-single-no-width: missing register width"); + ut_assert_nextlinen("P9 not found"); ut_assert_console_end(); return 0; -- 2.35.1

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[PATCH 1/2] Split CONFIG_CC_OPTIMIZE_FOR_SIZE into two configs
by Sean Anderson 26 Mar '22

26 Mar '22

This adds a separate CONFIG_CC_OPTIMIZE_FOR_SPEED option in a choice, in preparation for adding another optimization option. Also convert SH's makefile to use this new option. Signed-off-by: Sean Anderson <sean.anderson(a)seco.com> --- Kconfig | 17 ++++++++++++++--- Makefile | 4 +++- arch/sh/lib/Makefile | 2 +- 3 files changed, 18 insertions(+), 5 deletions(-) diff --git a/Kconfig b/Kconfig index 9dd9ec7f6d..8159c596c0 100644 --- a/Kconfig +++ b/Kconfig @@ -72,15 +72,26 @@ config CLANG_VERSION int default $(shell,$(srctree)/scripts/clang-version.sh $(CC)) +choice + prompt "Optimization level" + default CC_OPTIMIZE_FOR_SIZE + config CC_OPTIMIZE_FOR_SIZE bool "Optimize for size" - default y help - Enabling this option will pass "-Os" instead of "-O2" to gcc - resulting in a smaller U-Boot image. + Enabling this option will pass "-Os" to gcc, resulting in a smaller + U-Boot image. This option is enabled by default for U-Boot. +config CC_OPTIMIZE_FOR_SPEED + bool "Optimize for speed" + help + Enabling this option will pass "-O2" to gcc, resulting in a faster + U-Boot image. + +endchoice + config OPTIMIZE_INLINING bool "Allow compiler to uninline functions marked 'inline' in full U-Boot" help diff --git a/Makefile b/Makefile index 4b152249ca..1d3331c69f 100644 --- a/Makefile +++ b/Makefile @@ -682,7 +682,9 @@ endif ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE KBUILD_CFLAGS += -Os -else +endif + +ifdef CONFIG_CC_OPTIMIZE_FOR_SPEED KBUILD_CFLAGS += -O2 endif diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile index 9618da1cb3..e7520a328d 100644 --- a/arch/sh/lib/Makefile +++ b/arch/sh/lib/Makefile @@ -12,7 +12,7 @@ obj-$(CONFIG_CMD_SH_ZIMAGEBOOT) += zimageboot.o udivsi3-y := udivsi3_i4i-Os.o -ifneq ($(CONFIG_CC_OPTIMIZE_FOR_SIZE),y) +ifeq ($(CONFIG_CC_OPTIMIZE_FOR_SPEED),y) udivsi3-$(CONFIG_CPU_SH4) := udivsi3_i4i.o endif udivsi3-y += udivsi3.o -- 2.25.1

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[PATCH] pci: Add defines for normal and subtractive PCI bridges
by Pali Rohár 26 Mar '22

26 Mar '22

Add following two new PCI class codes defines into pci_ids.h include file: PCI_CLASS_BRIDGE_PCI_NORMAL PCI_CLASS_BRIDGE_PCI_SUBTRACTIVE And use these defines in all U-Boot code for describing PCI class codes for normal and subtractive PCI bridges. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- Same macros were included also into Linux kernel pci_ids.h file: https://lore.kernel.org/linux-pci/20220217213218.GA307343@bhelgaas/ --- board/armltd/vexpress64/pcie.c | 2 +- drivers/pci/pci-aardvark.c | 2 +- drivers/pci/pci-rcar-gen3.c | 2 +- drivers/pci/pci_mvebu.c | 2 +- drivers/pci/pci_tegra.c | 4 ++-- drivers/pci/pcie_dw_mvebu.c | 4 ++-- drivers/pci/pcie_fsl.c | 2 +- drivers/pci/pcie_imx.c | 4 ++-- drivers/pci/pcie_iproc.c | 2 +- drivers/pci/pcie_rockchip.c | 2 +- include/pci_ids.h | 2 ++ 11 files changed, 15 insertions(+), 13 deletions(-) diff --git a/board/armltd/vexpress64/pcie.c b/board/armltd/vexpress64/pcie.c index 1e74158630b5..e553da86e0e0 100644 --- a/board/armltd/vexpress64/pcie.c +++ b/board/armltd/vexpress64/pcie.c @@ -150,7 +150,7 @@ static void xr3pci_init(void) /* allow ECRC */ writel(0x6006, XR3_CONFIG_BASE + XR3PCI_PEX_SPC2); /* setup the correct class code for the host bridge */ - writel(PCI_CLASS_BRIDGE_PCI << 16, XR3_CONFIG_BASE + XR3PCI_BRIDGE_PCI_IDS); + writel(PCI_CLASS_BRIDGE_PCI_NORMAL << 8, XR3_CONFIG_BASE + XR3PCI_BRIDGE_PCI_IDS); /* reset phy and root complex */ writel(JUNO_RESET_CTRL_PHY | JUNO_RESET_CTRL_RC, diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c index 4f7e61ecf166..b0fc9caabbec 100644 --- a/drivers/pci/pci-aardvark.c +++ b/drivers/pci/pci-aardvark.c @@ -800,7 +800,7 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie) */ reg = advk_readl(pcie, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION); reg &= ~0xffffff00; - reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8; + reg |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8; advk_writel(pcie, reg, ADVK_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION); /* Enable generation and checking of ECRC on PCIe Root Port */ diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index 34a561ef8b4b..49029238d350 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -289,7 +289,7 @@ static int rcar_gen3_pcie_hw_init(struct udevice *dev) * class to match. Hardware takes care of propagating the IDSETR * settings, so there is no need to bother with a quirk. */ - writel(PCI_CLASS_BRIDGE_PCI << 16, priv->regs + IDSETR1); + writel(PCI_CLASS_BRIDGE_PCI_NORMAL << 8, priv->regs + IDSETR1); /* * Setup Secondary Bus Number & Subordinate Bus Number, even though diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index f47a0a9ea36b..2de2a5430b22 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -514,7 +514,7 @@ static int mvebu_pcie_probe(struct udevice *dev) */ reg = readl(pcie->base + MVPCIE_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION); reg &= ~0xffffff00; - reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8; + reg |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8; writel(reg, pcie->base + MVPCIE_ROOT_PORT_PCI_CFG_OFF + PCI_CLASS_REVISION); /* diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index fc05ee00f1fc..f8d66c0e1c6a 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -325,8 +325,8 @@ static int pci_tegra_read_config(const struct udevice *bus, pci_dev_t bdf, /* fixup root port class */ if (PCI_BUS(bdf) == 0) { if ((offset & ~3) == PCI_CLASS_REVISION) { - value &= ~0x00ff0000; - value |= PCI_CLASS_BRIDGE_PCI << 16; + value &= ~0x00ffff00; + value |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8; } } #endif diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index 0490fd337705..99891dce61d5 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -539,9 +539,9 @@ static int pcie_dw_mvebu_probe(struct udevice *dev) PCIE_ATU_TYPE_MEM, pcie->mem.phys_start, pcie->mem.bus_start, pcie->mem.size); - /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */ + /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI_NORMAL */ clrsetbits_le32(pcie->ctrl_base + PCI_CLASS_REVISION, - 0xffff << 16, PCI_CLASS_BRIDGE_PCI << 16); + 0xffffff << 8, PCI_CLASS_BRIDGE_PCI_NORMAL << 8); pcie_dw_set_host_bars(pcie->ctrl_base); diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index cc6efdd5b464..f5ba34970f15 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -532,7 +532,7 @@ static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie) fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val); val &= 0xff; - val |= PCI_CLASS_BRIDGE_PCI << 16; + val |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8; fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val); if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 756166fd3eaa..2cec3900e9ad 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -300,9 +300,9 @@ static int imx_pcie_regions_setup(struct imx_pcie_priv *priv) setbits_le32(priv->dbi_base + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */ + /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI_NORMAL */ setbits_le32(priv->dbi_base + PCI_CLASS_REVISION, - PCI_CLASS_BRIDGE_PCI << 16); + PCI_CLASS_BRIDGE_PCI_NORMAL << 8); /* Region #0 is used for Outbound CFG space access. */ writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT); diff --git a/drivers/pci/pcie_iproc.c b/drivers/pci/pcie_iproc.c index 85dfab5c720f..d6d3a9e20250 100644 --- a/drivers/pci/pcie_iproc.c +++ b/drivers/pci/pcie_iproc.c @@ -1123,7 +1123,7 @@ static int iproc_pcie_check_link(struct iproc_pcie *pcie) PCI_BRIDGE_CTRL_REG_OFFSET, 4, &class); class &= ~PCI_BRIDGE_CTRL_REG_CLASS_MASK; - class |= (PCI_CLASS_BRIDGE_PCI << 8); + class |= PCI_CLASS_BRIDGE_PCI_NORMAL; iproc_pci_raw_config_write32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET, 4, class); diff --git a/drivers/pci/pcie_rockchip.c b/drivers/pci/pcie_rockchip.c index 67039d2a29f8..72b41398f27b 100644 --- a/drivers/pci/pcie_rockchip.c +++ b/drivers/pci/pcie_rockchip.c @@ -351,7 +351,7 @@ static int rockchip_pcie_init_port(struct udevice *dev) /* Initialize Root Complex registers. */ writel(PCIE_LM_VENDOR_ROCKCHIP, priv->apb_base + PCIE_LM_VENDOR_ID); - writel(PCI_CLASS_BRIDGE_PCI << 16, + writel(PCI_CLASS_BRIDGE_PCI_NORMAL << 8, priv->apb_base + PCIE_RC_BASE + PCI_CLASS_REVISION); writel(PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS, priv->apb_base + PCIE_LM_RCBAR); diff --git a/include/pci_ids.h b/include/pci_ids.h index 3c5434c0eda8..88b0a6404585 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -55,6 +55,8 @@ #define PCI_CLASS_BRIDGE_EISA 0x0602 #define PCI_CLASS_BRIDGE_MC 0x0603 #define PCI_CLASS_BRIDGE_PCI 0x0604 +#define PCI_CLASS_BRIDGE_PCI_NORMAL 0x060400 +#define PCI_CLASS_BRIDGE_PCI_SUBTRACTIVE 0x060401 #define PCI_CLASS_BRIDGE_PCMCIA 0x0605 #define PCI_CLASS_BRIDGE_NUBUS 0x0606 #define PCI_CLASS_BRIDGE_CARDBUS 0x0607 -- 2.20.1

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[PATCH 1/2] sandbox: video: Replace PCI_CLASS_* macros by one from pci_ids.h
by Pali Rohár 26 Mar '22

26 Mar '22

Replace old macros PCI_CLASS_CODE_COMM and PCI_CLASS_SUB_CODE_COMM_SERIAL by new macros defined in pci_ids.h. Old macros would be deleted in followup commit. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- arch/sandbox/include/asm/test.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index 0d83f4dc1bcb..015e96d53f87 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -9,6 +9,7 @@ #define __ASM_TEST_H #include <video.h> +#include <pci_ids.h> /* The sandbox driver always permits an I2C device with this address */ #define SANDBOX_I2C_TEST_ADDR 0x59 @@ -17,8 +18,8 @@ #define SANDBOX_PCI_SWAP_CASE_EMUL_ID 0x5678 #define SANDBOX_PCI_PMC_EMUL_ID 0x5677 #define SANDBOX_PCI_P2SB_EMUL_ID 0x5676 -#define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM -#define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL +#define SANDBOX_PCI_CLASS_CODE (PCI_CLASS_COMMUNICATION_SERIAL >> 8) +#define SANDBOX_PCI_CLASS_SUB_CODE (PCI_CLASS_COMMUNICATION_SERIAL & 0xff) #define PCI_CAP_ID_PM_OFFSET 0x50 #define PCI_CAP_ID_EXP_OFFSET 0x60 -- 2.20.1

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[0/3] Add support for different mediatek pinctrl designs
by Sam Shih 25 Mar '22

25 Mar '22

MediaTek SoC's pinconf register usage varies by SoC, So the original code uses V0/V1 to mark different pinconf design. But actually, the real difference is the design of the "pin" itself. Different SoCs will choose specify "pin design", which we call the "io_type" of the pin. For a better understanding of mediatek pinctrl design. and make the driver clear and flexible, this patch series changes common parts of mediatek pinctrl driver to support various pinctrl controller designs. Sam Shih (3): pinctrl: mediatek: rewrite mtk_pinconf_set and related functions pinctrl: mediatek: introduce multiple memory bases support pinctrl: mediatek: add support for different types of IO pins drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 217 ++++++++++++++---- drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 79 ++++++- 2 files changed, 243 insertions(+), 53 deletions(-) -- 2.29.2

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[PATCH 01/15] Convert CONFIG_AT91_LED to Kconfig
by Tom Rini 25 Mar '22

25 Mar '22

This converts the following to Kconfig: CONFIG_AT91_LED Cc: Eugen Hristev <eugen.hristev(a)microchip.com> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- board/siemens/corvus/Kconfig | 3 +++ include/configs/corvus.h | 1 - 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/board/siemens/corvus/Kconfig b/board/siemens/corvus/Kconfig index 69fe0f072344..77974133ccf3 100644 --- a/board/siemens/corvus/Kconfig +++ b/board/siemens/corvus/Kconfig @@ -1,5 +1,8 @@ if TARGET_CORVUS +config AT91_LED + def_bool y + config SYS_BOARD default "corvus" diff --git a/include/configs/corvus.h b/include/configs/corvus.h index caadf6462614..2aabd4bbe2e4 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -32,7 +32,6 @@ #define CONFIG_USART_ID ATMEL_ID_SYS /* LED */ -#define CONFIG_AT91_LED #define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */ #define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */ -- 2.25.1

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