February 2022 - U-Boot

[PATCH] serial: remove nulldev_serial_input
by Heiko Schocher 08 Feb '22

08 Feb '22

nulldev_serial_input is static and not used in this file, so remove it. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- azure build is clean https://dev.azure.com/hs0298/hs/_build/results?buildId=78&view=results drivers/serial/serial_nulldev.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/serial/serial_nulldev.c b/drivers/serial/serial_nulldev.c index efae14dd6c..f3ca7f5255 100644 --- a/drivers/serial/serial_nulldev.c +++ b/drivers/serial/serial_nulldev.c @@ -22,11 +22,6 @@ static int nulldev_serial_pending(struct udevice *dev, bool input) return 0; } -static int nulldev_serial_input(struct udevice *dev) -{ - return 0; -} - static int nulldev_serial_putc(struct udevice *dev, const char ch) { return 0; -- 2.34.1

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[PATCH] serial-uclass: fix build warning
by Heiko Schocher 08 Feb '22

08 Feb '22

if CONFIG_DM_STDIO is defined but SERIAL_PRESENT not, gcc drops warnings for serial_stub_* functions that they are defined but not used. Fix it. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- azure build is clean https://dev.azure.com/hs0298/hs/_build/results?buildId=78&view=results drivers/serial/serial-uclass.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 96a1cb65ba..362cedd955 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -357,7 +357,6 @@ static void serial_stub_putc(struct stdio_dev *sdev, const char ch) { _serial_putc(sdev->priv, ch); } -#endif static void serial_stub_puts(struct stdio_dev *sdev, const char *str) { @@ -374,6 +373,7 @@ static int serial_stub_tstc(struct stdio_dev *sdev) return _serial_tstc(sdev->priv); } #endif +#endif /** * on_baudrate() - Update the actual baudrate when the env var changes -- 2.34.1

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[PATCH 1/2] arch: x86: lib: acpi_table: Fix MCFG entries
by Moritz Fischer 08 Feb '22

08 Feb '22

Commit d953137526cc ("x86: Move SSDT table to a writer function") introduced a bug where the actual MCFG entries are no longer generated. Cc: Simon Glass <sjg(a)chromium.org> Fixes: d953137526cc ("x86: Move SSDT table to a writer function") Signed-off-by: Moritz Fischer <moritzf(a)google.com> --- Hi Simon, Andriy, it looks like this got dropped when moving stuff around, I don't have HW to test this, but it seemed off. - Moritz --- arch/x86/lib/acpi_table.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index c0534343f1..753bf39619 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -499,6 +499,8 @@ int acpi_write_mcfg(struct acpi_ctx *ctx, const struct acpi_writer *entry) header->length = sizeof(struct acpi_mcfg); header->revision = 1; + current = acpi_fill_mcfg(current); + /* (Re)calculate length and checksum */ header->length = current - (u32)mcfg; header->checksum = table_compute_checksum(mcfg, header->length); -- 2.35.0.263.gb82422642f-goog

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k210 spi flash regression
by Niklas Cassel 08 Feb '22

08 Feb '22

Hello Pratyush, I upgraded u-boot on my k210 maix bit board, and the SPI flash is no longer detected. I bisected the problem to commit: d15de623013c ("spi: spi-mem: allow specifying a command's extension") Before the commit in question, the following was printed: Loading Environment from SPIFlash... SF: Detected gd25lq128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB *** Warning - bad CRC, using default environment After the commit in question, the following is printed: Loading Environment from SPIFlash... jedec_spi_nor spi-flash@0: unrecognized JEDEC id bytes: 60, 18, c8 *** Warning - spi_flash_probe_bus_cs() failed, using default environment Looking at spi-nor-ids.c, the flash is defined like this: INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) So it appears that after your patch, the bytes are coming in the wrong order. Any suggestions? Kind regards, Niklas

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[PATCH] boot: Update default on USE_SPL_FIT_GENERATOR
by Tom Rini 08 Feb '22

08 Feb '22

The use of CONFIG_SPL_FIT_GENERATOR is deprecated and should not be used. Start by changing the current default option from enabled to only enabled for the platforms still using it. Cc: Simon Glass <sjg(a)chromium.org> Signed-off-by: Tom Rini <trini(a)konsulko.com> --- This change completes the migration for a number of platforms that were tripping the warning before but not actually using a generator. --- boot/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boot/Kconfig b/boot/Kconfig index c8d5906cd304..38fc64595ca7 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -275,7 +275,7 @@ config SPL_FIT_SOURCE config USE_SPL_FIT_GENERATOR bool "Use a script to generate the .its script" - default y if SPL_FIT && (!ARCH_SUNXI && !RISCV) + default y if SPL_FIT && SPL_LOAD_FIT && (ARCH_ROCKCHIP || ARCH_ZYNQMP) config SPL_FIT_GENERATOR string ".its file generator script for U-Boot FIT image" -- 2.25.1

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[PATCH] common: spl: spl_mmc: Add full FIT image support for kernel/OS loading during Falcon boot mode while booting via MMC
by Nathan Barrett-Morrison 08 Feb '22

08 Feb '22

Hi Tom, This patch adds support for Falcon mode boot via MMC flash boot devices with full FIT images. While attempting to use Falcon boot mode with FIT images on MMC flash boot devices, I've found the following additional code to be required. Patch attached and also added inline below: Sincerely, Nathan >From a3d066656df60856950c9cbb28914d02d57c9364 Mon Sep 17 00:00:00 2001 From: Nathan Barrett-Morrison <nathan.morrison(a)timesys.com> Date: Tue, 8 Feb 2022 13:16:24 -0500 Subject: [PATCH] common: spl: spl_mmc: Add full FIT image support for kernel/OS loading during Falcon boot mode while booting via MMC Signed-off-by: Nathan Barrett-Morrison <nathan.morrison(a)timesys.com> Cc: Tom Rini <trini(a)konsulko.com> --- common/spl/spl_mmc.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index e1a7d25bd0..7fb2505c33 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -94,7 +94,19 @@ int mmc_load_image_raw_sector(struct spl_image_info *spl_image, goto end; } - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL) && + image_get_magic(header) == FDT_MAGIC) { + u32 image_size_sectors; + + debug("Found FIT\n"); + + image_size_sectors = (roundup(fdt_totalsize(header), 4) + mmc->read_bl_len - 1) / + mmc->read_bl_len; + count = blk_dread(bd, sector, image_size_sectors, CONFIG_SYS_LOAD_ADDR); + debug("hdr read sector %lx, count=%lu\n", sector, count); + + ret = spl_parse_image_header(spl_image, CONFIG_SYS_LOAD_ADDR); + } else if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && image_get_magic(header) == FDT_MAGIC) { struct spl_load_info load; -- 2.30.2

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[PATCH] common: spl: spl_spi: Add in FIT image support for kernel/OS loading during Falcon boot mode while booting via SPI
by Nathan Barrett-Morrison 08 Feb '22

08 Feb '22

Hi Tom, This patch adds support for Falcon mode boot via SPI flash boot devices with FIT images. While attempting to use Falcon boot mode with FIT images on SPI flash boot devices, I've found the following additional code to be required. Patch attached and also added inline below: Sincerely, Nathan >From b93c9122114ee701f13a62af63d74a0644fcef92 Mon Sep 17 00:00:00 2001 From: Nathan Barrett-Morrison <nathan.morrison(a)timesys.com> Date: Tue, 8 Feb 2022 13:05:34 -0500 Subject: [PATCH] common: spl: spl_spi: Add in FIT image support for kernel/OS loading during Falcon boot mode while booting via SPI Signed-off-by: Nathan Barrett-Morrison <nathan.morrison(a)timesys.com> Cc: Tom Rini <trini(a)konsulko.com> --- common/spl/spl_spi.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index 4e20a23dea..82b396fc62 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -29,6 +29,18 @@ static int spi_load_image_os(struct spl_image_info *spl_image, { int err; +#if CONFIG_IS_ENABLED(LOAD_FIT_FULL) || CONFIG_IS_ENABLED(LOAD_FIT) + spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, sizeof(struct fdt_header), + (void *)header); + + if (image_get_magic(header) == FDT_MAGIC) + spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, + roundup(fdt_totalsize(header), 4), CONFIG_SYS_LOAD_ADDR); + + err = spl_parse_image_header(spl_image, CONFIG_SYS_LOAD_ADDR); + if (err) + return err; +#else /* Read for a header, parse or error out. */ spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, sizeof(*header), (void *)header); @@ -47,6 +59,7 @@ static int spi_load_image_os(struct spl_image_info *spl_image, spi_flash_read(flash, CONFIG_SYS_SPI_ARGS_OFFS, CONFIG_SYS_SPI_ARGS_SIZE, (void *)CONFIG_SYS_SPL_ARGS_ADDR); +#endif return 0; } -- 2.30.2

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[PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration
by Aswath Govindraju 08 Feb '22

08 Feb '22

The following series of patches add support for PCIe + QSGMII multilink configuration on J721e EVM. The PHY lanes are configured in U-Boot and, PCIe driver in Kernel and QSGMII driver in the ethernet firmware use them. Notes: - Patches 1 -8 and 13 - 22 are ported from upstream kernel v5.17-rc1 - Patch 24, syncs with linux kernel dt, with the following patch https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=608996 Changes since v1: - Fixed the logic for skipping multilink configuration in patch 23 - Fixed the offset calcualation for SIERRA_PHY_PCS_LANE_CDB_OFFSET and SIERRA_PHY_PMA_LANE_CDB_OFFSET in patches 18 and 21. Aswath Govindraju (8): phy: cadence: Sierra: Add a UCLASS_PHY device for links phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE board: ti: j721e: evm.c: Add support for probing SerDes0 arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0 phy: cadence: Sierra: Add support for skipping configuration arm: dts: k3-j721e: Add support for multilink PCIe + QSGMII include: configs: j721e_evm: Add support to boot ethfw core in j721e Kishon Vijay Abraham I (6): phy: cadence: Sierra: Fix PHY power_on sequence phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodes phy: cadence: Sierra: Move all clk_get_*() to a separate function phy: cadence: Sierra: Move all reset_control_get*() to a separate function phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy" phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callback Sanket Parmar (1): phy: cadence: sierra: Fix for USB3 U1/U2 state Swapnil Jakhade (10): phy: cadence: Sierra: Prepare driver to add support for multilink configurations dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode phy: cadence: Sierra: Add support to get SSC type from device tree. phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation phy: cadence: Sierra: Add PHY PCS common register configurations phy: cadence: Sierra: Check cmn_ready assertion during PHY power on phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation phy: cadence: Sierra: Update single link PCIe register configuration phy: cadence: Sierra: Add support for PHY multilink configurations phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration .../k3-j721e-common-proc-board-u-boot.dtsi | 15 + arch/arm/dts/k3-j721e-common-proc-board.dts | 14 +- .../arm/dts/k3-j721e-r5-common-proc-board.dts | 32 + board/ti/j721e/evm.c | 37 + configs/j721e_evm_a72_defconfig | 2 +- drivers/phy/cadence/phy-cadence-sierra.c | 1537 +++++++++++++++-- drivers/phy/ti/phy-j721e-wiz.c | 2 +- include/configs/j721e_evm.h | 19 +- include/dt-bindings/phy/phy-cadence.h | 4 + 9 files changed, 1494 insertions(+), 168 deletions(-) -- 2.17.1

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[PATCH] soc: soc_ti_k3: update j721e revision numbering
by Bryan Brattlof 08 Feb '22

08 Feb '22

There is a 4 bit VARIANT number inside the JTAGID register that TI increments any time a new variant for a chip is produced. Each family of TI's SoCs uses a different versioning scheme based off that VARIANT number. CC: Dave Gerlach <d-gerlach(a)ti.com> Signed-off-by: Bryan Brattlof <bb(a)ti.com> --- drivers/soc/soc_ti_k3.c | 40 +++++++++++++++++++++++++++------------- 1 file changed, 27 insertions(+), 13 deletions(-) diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c index 9abed7d490a2c..7a126857cd709 100644 --- a/drivers/soc/soc_ti_k3.c +++ b/drivers/soc/soc_ti_k3.c @@ -15,9 +15,6 @@ #define J7200 0xbb6d #define AM64X 0xbb38 -#define REV_SR1_0 0 -#define REV_SR2_0 1 - #define JTAG_ID_VARIANT_SHIFT 28 #define JTAG_ID_VARIANT_MASK (0xf << 28) #define JTAG_ID_PARTNO_SHIFT 12 @@ -55,25 +52,42 @@ static const char *get_family_string(u32 idreg) return family; } +static char *j721e_rev_string_map[] = { + "1.0", "1.1", +}; + +static char *am65x_rev_string_map[] = { + "1.0", "2.0", +}; + static const char *get_rev_string(u32 idreg) { - const char *revision; u32 rev; + u32 soc; rev = (idreg & JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT; + soc = (idreg & JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT; - switch (rev) { - case REV_SR1_0: - revision = "1.0"; - break; - case REV_SR2_0: - revision = "2.0"; - break; + switch (soc) { + case J721E: + if (rev > ARRAY_SIZE(j721e_rev_string_map)) + goto bail; + return j721e_rev_string_map[rev]; + + case AM65X: + if (rev > ARRAY_SIZE(am65x_rev_string_map)) + goto bail; + return am65x_rev_string_map[rev]; + + case AM64X: + case J7200: default: - revision = "Unknown Revision"; + if (!rev) + return "1.0"; }; - return revision; +bail: + return "Unknown Revision"; } static int soc_ti_k3_get_family(struct udevice *dev, char *buf, int size) -- 2.17.1

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[PATCH v4 00/20] J721S2: Add initial support
by Aswath Govindraju 08 Feb '22

08 Feb '22

The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. * Chips and Media Wave521CL H.264/H.265 encode/decode engine See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 bootlog: - https://pastebin.ubuntu.com/p/NkwRvJH5Gg/ Notes: - Patches 12, 13, 14, 15 and 16 are synced from upstream kernel v5.17-rc1 tag Changes since v3: - Fixed the MMU mapping to standard in patch 5 based on the comments received from Suman. Changes since v2: - Removed the redundant config K3_J721S2_DDRSS and instead used K3_J721E_DDRSS - Formatted the Kconfig files to remove extra lines - Added dts files in the MAINTAINERS baord folder Changes since v1: - Removed unused serial aliases - Assigned serial2 alias for main uart8 instance - Moved aliases to respective board files Aswath Govindraju (10): ram: k3-ddrss: lpddr4_structs_if.h: Add a pointer to ddr instance ram: k3-ddrss: Add support for multiple instances of DDR subsystems ram: k3-ddrss: Add support for configuring MSMC subsystem in case of Multiple DDR subsystems dt-bindings: ti-serdes-mux: Add defines for J721S2 SoC dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721S2 arm: dts: Add initial support for J721S2 SoC arm: dts: Add initial support for J721S2 System on Module arm: dts: Add support for A72 specific J721S2 Common Processor Board arm: dts: k3-j721s2: Add r5 specific dt support arm: dts: k3-j721s2-ddr: Add DDR support David Huang (9): arm: K3: Add basic support for J721S2 SoC definition drivers: dma: Add support for J721S2 clk: clk-k3: Add support for J721S2 SoC power: domain: ti: Add support for J721S2 SoC ram: k3-ddrss: Add support for J721S2 SoC soc: ti: k3-socinfo: Add entry for J721S2 SoC board: ti: j721s2: Add board support for J721S2 configs: j721s2_evm_r5_defconfig: Add R5 SPL specific defconfig configs: j721s2_evm_a72_defconfig: Add A72 specific defconfig Nishanth Menon (1): remoteproc: k3_system_controller: Support optional boot_notification channel arch/arm/dts/Makefile | 2 + .../k3-j721s2-common-proc-board-u-boot.dtsi | 149 + arch/arm/dts/k3-j721s2-common-proc-board.dts | 430 ++ arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi | 4387 ++++++++++++++++ arch/arm/dts/k3-j721s2-ddr.dtsi | 4440 +++++++++++++++++ arch/arm/dts/k3-j721s2-main.dtsi | 937 ++++ arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi | 302 ++ .../dts/k3-j721s2-r5-common-proc-board.dts | 198 + arch/arm/dts/k3-j721s2-som-p0.dtsi | 173 + arch/arm/dts/k3-j721s2.dtsi | 167 + arch/arm/mach-k3/Kconfig | 15 +- arch/arm/mach-k3/Makefile | 1 + arch/arm/mach-k3/arm64-mmu.c | 41 + arch/arm/mach-k3/include/mach/hardware.h | 4 + .../mach-k3/include/mach/j721s2_hardware.h | 60 + arch/arm/mach-k3/include/mach/j721s2_spl.h | 46 + arch/arm/mach-k3/include/mach/spl.h | 4 + arch/arm/mach-k3/j721s2/Makefile | 5 + arch/arm/mach-k3/j721s2/clk-data.c | 403 ++ arch/arm/mach-k3/j721s2/dev-data.c | 85 + arch/arm/mach-k3/j721s2_init.c | 312 ++ board/ti/j721s2/Kconfig | 63 + board/ti/j721s2/MAINTAINERS | 16 + board/ti/j721s2/Makefile | 8 + board/ti/j721s2/evm.c | 180 + configs/j721s2_evm_a72_defconfig | 207 + configs/j721s2_evm_r5_defconfig | 171 + .../remoteproc/k3-system-controller.txt | 3 + drivers/clk/ti/clk-k3.c | 5 + drivers/dma/ti/Makefile | 1 + drivers/dma/ti/k3-psil-j721s2.c | 167 + drivers/dma/ti/k3-psil-priv.h | 1 + drivers/dma/ti/k3-psil.c | 2 + drivers/firmware/ti_sci_static_data.h | 40 +- drivers/power/domain/ti-power-domain.c | 5 + drivers/ram/Kconfig | 2 +- drivers/ram/k3-ddrss/k3-ddrss.c | 296 +- drivers/ram/k3-ddrss/lpddr4_structs_if.h | 1 + drivers/remoteproc/k3_system_controller.c | 20 +- drivers/soc/soc_ti_k3.c | 4 + include/configs/j721s2_evm.h | 191 + include/dt-bindings/mux/ti-serdes.h | 22 + include/dt-bindings/pinctrl/k3.h | 3 + include/k3-clk.h | 1 + include/k3-dev.h | 1 + 45 files changed, 13510 insertions(+), 61 deletions(-) create mode 100644 arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi create mode 100644 arch/arm/dts/k3-j721s2-common-proc-board.dts create mode 100644 arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi create mode 100644 arch/arm/dts/k3-j721s2-ddr.dtsi create mode 100644 arch/arm/dts/k3-j721s2-main.dtsi create mode 100644 arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi create mode 100644 arch/arm/dts/k3-j721s2-r5-common-proc-board.dts create mode 100644 arch/arm/dts/k3-j721s2-som-p0.dtsi create mode 100644 arch/arm/dts/k3-j721s2.dtsi create mode 100644 arch/arm/mach-k3/include/mach/j721s2_hardware.h create mode 100644 arch/arm/mach-k3/include/mach/j721s2_spl.h create mode 100644 arch/arm/mach-k3/j721s2/Makefile create mode 100644 arch/arm/mach-k3/j721s2/clk-data.c create mode 100644 arch/arm/mach-k3/j721s2/dev-data.c create mode 100644 arch/arm/mach-k3/j721s2_init.c create mode 100644 board/ti/j721s2/Kconfig create mode 100644 board/ti/j721s2/MAINTAINERS create mode 100644 board/ti/j721s2/Makefile create mode 100644 board/ti/j721s2/evm.c create mode 100644 configs/j721s2_evm_a72_defconfig create mode 100644 configs/j721s2_evm_r5_defconfig create mode 100644 drivers/dma/ti/k3-psil-j721s2.c create mode 100644 include/configs/j721s2_evm.h -- 2.17.1

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