February 2022 - U-Boot

[PATCH] arm: dts: k3-j7200: Fix up MAIN R5FSS cluster mode back to Split-mode
by Suman Anna 21 Feb '22

21 Feb '22

The default U-Boot environment variables and design are all set up for the MAIN R5FSS cluster to be in Split-mode. This is the setting used when the dts nodes were originally added in v2021.01 U-Boot and the dt nodes are synched with the kernel binding property names in commit 468ec2f3ef8f ("remoteproc: k3_r5: Sync to upstreamed kernel DT property names") merged in v2021.04-rc2. The modes for the MAIN R5FSS cluster got switched back to LockStep mode by mistake in commit fa09b12dc5f6 ("arm: ti: k3: Resync dts files and bindings with Linux Kernel v5.14") in v2022.01-rc1. This throws the following warning messages when early-booting the cores using default env variables, k3_r5f_rproc r5f@5d00000: Invalid op: Trying to start secondary core 7 in lockstep mode Load Remote Processor 3 with data@addr=0x82000000 83148 bytes: Failed! Fix this by switching back both the clusters to the expected Split-mode. Make this mode change in the u-boot specific dtsi file to avoid such sync overrides in the future until the kernel dts is also switched to Split-mode by default. Fixes: fa09b12dc5f6 ("arm: ti: k3: Resync dts files and bindings with Linux Kernel v5.14") Signed-off-by: Suman Anna <s-anna(a)ti.com> --- arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index 1544c2e51bde..ce52ffcf96af 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -192,3 +192,7 @@ &serdes0 { u-boot,dm-spl; }; + +&main_r5fss0 { + ti,cluster-mode = <0>; +}; -- 2.32.0

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[PATCH 1/2] arm: omap3: Cleanup sys_info to fit OMAP3 booting with LTO
by Adam Ford 21 Feb '22

21 Feb '22

With LTO enabled, some functions appear to be optimized in a way that causes hanging on some OMAP3 boards after some unrelated patches were applied. The solution appears to make several functions __used. There also appears be to be some dead code, so remove it while cleaning this up. This has been tested on a general purpose OMAP3530, DM3730, and AM3517. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index a6e9ff84aa..e7078a32db 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -45,16 +45,12 @@ void gpmc_init(void); void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, u32 base, u32 size); void set_gpmc_cs0(int flash_type); - void watchdog_init(void); void set_muxconf_regs(void); - u32 get_cpu_family(void); u32 get_cpu_rev(void); -u32 get_sku_id(void); u32 is_gpmc_muxed(void); u32 get_gpmc0_type(void); -u32 get_gpmc0_width(void); u32 is_running_in_sdram(void); u32 is_running_in_sram(void); u32 is_running_in_flash(void); diff --git a/arch/arm/mach-omap2/omap3/sys_info.c b/arch/arm/mach-omap2/omap3/sys_info.c index ac72633c20..5f535e2782 100644 --- a/arch/arm/mach-omap2/omap3/sys_info.c +++ b/arch/arm/mach-omap2/omap3/sys_info.c @@ -55,7 +55,7 @@ void omap_die_id(unsigned int *die_id) /****************************************** * get_cpu_type(void) - extract cpu info ******************************************/ -u32 get_cpu_type(void) +static u32 get_cpu_type(void) { return readl(&ctrl_base->ctrl_omap_stat); } @@ -64,7 +64,7 @@ u32 get_cpu_type(void) * get_cpu_id(void) - extract cpu id * returns 0 for ES1.0, cpuid otherwise ******************************************/ -u32 get_cpu_id(void) +static u32 get_cpu_id(void) { struct ctrl_id *id_base; u32 cpuid = 0; @@ -89,7 +89,7 @@ u32 get_cpu_id(void) /****************************************** * get_cpu_family(void) - extract cpu info ******************************************/ -u32 get_cpu_family(void) +__used u32 get_cpu_family(void) { u16 hawkeye; u32 cpu_family; @@ -119,7 +119,7 @@ u32 get_cpu_family(void) /****************************************** * get_cpu_rev(void) - extract version info ******************************************/ -u32 get_cpu_rev(void) +__used u32 get_cpu_rev(void) { u32 cpuid = get_cpu_id(); @@ -132,41 +132,12 @@ u32 get_cpu_rev(void) /***************************************************************** * get_sku_id(void) - read sku_id to get info on max clock rate *****************************************************************/ -u32 get_sku_id(void) +static u32 get_sku_id(void) { struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE; return readl(&id_base->sku_id) & SKUID_CLK_MASK; } -/*************************************************************************** - * get_gpmc0_base() - Return current address hardware will be - * fetching from. The below effectively gives what is correct, its a bit - * mis-leading compared to the TRM. For the most general case the mask - * needs to be also taken into account this does work in practice. - * - for u-boot we currently map: - * -- 0 to nothing, - * -- 4 to flash - * -- 8 to enent - * -- c to wifi - ****************************************************************************/ -u32 get_gpmc0_base(void) -{ - u32 b; - - b = readl(&gpmc_cfg->cs[0].config7); - b &= 0x1F; /* keep base [5:0] */ - b = b << 24; /* ret 0x0b000000 */ - return b; -} - -/******************************************************************* - * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) - *******************************************************************/ -u32 get_gpmc0_width(void) -{ - return WIDTH_16BIT; -} - /************************************************************************* * get_board_rev() - setup to pass kernel board revision information * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) -- 2.32.0

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[PATCH] arm: dts: k3-j721e-r5-common-proc-board: tps659413: Correct the min/max voltages of VDD_CPU
by Keerthy 21 Feb '22

21 Feb '22

Correct the min/max voltages of VDD_CPU. As per data sheet the VDD_CPU minimum voltage is .6V & maximum voltage is .9V. Correct the same. While at it fix the comment to reflect VDD_CPU instead of VDD_MPU. Data Sheet Link: https://www.ti.com/lit/gpn/dra829v Signed-off-by: Keerthy <j-keerthy(a)ti.com> --- arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 5362c52870..1507109892 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -259,10 +259,10 @@ regulators: regulators { u-boot,dm-spl; buck12_reg: buck12 { - /*VDD_MPU*/ + /*VDD_CPU*/ regulator-name = "buck12"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1250000>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <900000>; regulator-always-on; regulator-boot-on; u-boot,dm-spl; -- 2.17.1

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[PATCH 1/1] iommu: Add M1 Pro/Max support to Apple DART driver
by Janne Grunau 21 Feb '22

21 Feb '22

For the purpose of this driver (activating bypass mode) t6000-dart and t8103-dart are fully compatible. Signed-off-by: Janne Grunau <j(a)jannau.net> Reviewed-by: Mark Kettenis <kettenis(a)openbsd.org> --- drivers/iommu/apple_dart.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/apple_dart.c b/drivers/iommu/apple_dart.c index ff8c5fa62c..f2e1700960 100644 --- a/drivers/iommu/apple_dart.c +++ b/drivers/iommu/apple_dart.c @@ -48,6 +48,7 @@ static int apple_dart_probe(struct udevice *dev) static const struct udevice_id apple_dart_ids[] = { { .compatible = "apple,t8103-dart" }, + { .compatible = "apple,t6000-dart" }, { /* sentinel */ } }; -- 2.35.1

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[PATCH] arm: apple: Add M1 Pro/Max support
by Mark Kettenis 21 Feb '22

21 Feb '22

Choose the memory map based on the compatible property from the device tree passed to us by m1n1. Since DRAM on the M1 Pro/Max starts at a different address avoid hardcoding the top of usable memory. Also make sure that the addresses entered into the memory map are page aligned such that we don't crash in dcache_enable(). Signed-off-by: Mark Kettenis <kettenis(a)openbsd.org> Tested on: Macbook M1 Max Tested-by: Janne Grunau <j(a)jannau.net> --- arch/arm/mach-apple/board.c | 207 +++++++++++++++++++++++++++++------- 1 file changed, 168 insertions(+), 39 deletions(-) diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index b7e8d212f1..f9f8a2f278 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -14,12 +14,22 @@ DECLARE_GLOBAL_DATA_PTR; -static struct mm_region apple_mem_map[] = { +/* Apple M1 */ + +static struct mm_region t8103_mem_map[] = { { /* I/O */ .virt = 0x200000000, .phys = 0x200000000, - .size = 8UL * SZ_1G, + .size = 2UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x380000000, + .phys = 0x380000000, + .size = SZ_1G, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN @@ -27,7 +37,7 @@ static struct mm_region apple_mem_map[] = { /* I/O */ .virt = 0x500000000, .phys = 0x500000000, - .size = 2UL * SZ_1G, + .size = SZ_1G, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN @@ -63,15 +73,110 @@ static struct mm_region apple_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { - /* Empty entry for framebuffer */ + /* Framebuffer */ + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ 0, + } +}; + +/* Apple M1 Pro/Max */ + +static struct mm_region t6000_mem_map[] = { + { + /* I/O */ + .virt = 0x280000000, + .phys = 0x280000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x380000000, + .phys = 0x380000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x580000000, + .phys = 0x580000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x5a0000000, + .phys = 0x5a0000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x5c0000000, + .phys = 0x5c0000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x700000000, + .phys = 0x700000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0xb00000000, + .phys = 0xb00000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0xf00000000, + .phys = 0xf00000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x1300000000, + .phys = 0x1300000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* RAM */ + .virt = 0x10000000000, + .phys = 0x10000000000, + .size = 16UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* Framebuffer */ + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { /* List terminator */ 0, } }; -struct mm_region *mem_map = apple_mem_map; +struct mm_region *mem_map; int board_init(void) { @@ -79,60 +184,84 @@ int board_init(void) } int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +extern long fw_dtb_pointer; + +void *board_fdt_blob_setup(int *err) +{ + /* Return DTB pointer passed by m1n1 */ + *err = 0; + return (void *)fw_dtb_pointer; +} + +void build_mem_map(void) { ofnode node; - int index, ret; fdt_addr_t base; fdt_size_t size; + int i; + + if (of_machine_is_compatible("apple,t8103")) + mem_map = t8103_mem_map; + else if (of_machine_is_compatible("apple,t6000")) + mem_map = t6000_mem_map; + else if (of_machine_is_compatible("apple,t6001")) + mem_map = t6000_mem_map; + else + panic("Unsupported SoC\n"); - ret = fdtdec_setup_mem_size_base(); - if (ret) - return ret; + /* Find list terminator. */ + for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) + ; + + /* Align RAM mapping to page boundaries */ + base = gd->bd->bi_dram[0].start; + size = gd->bd->bi_dram[0].size; + size += (base - ALIGN_DOWN(base, SZ_4K)); + base = ALIGN_DOWN(base, SZ_4K); + size = ALIGN(size, SZ_4K); /* Update RAM mapping */ - index = ARRAY_SIZE(apple_mem_map) - 3; - apple_mem_map[index].virt = gd->ram_base; - apple_mem_map[index].phys = gd->ram_base; - apple_mem_map[index].size = gd->ram_size; + mem_map[i - 2].virt = base; + mem_map[i - 2].phys = base; + mem_map[i - 2].size = size; node = ofnode_path("/chosen/framebuffer"); if (!ofnode_valid(node)) - return 0; + return; base = ofnode_get_addr_size(node, "reg", &size); if (base == FDT_ADDR_T_NONE) - return 0; + return; - /* Add framebuffer mapping */ - index = ARRAY_SIZE(apple_mem_map) - 2; - apple_mem_map[index].virt = base; - apple_mem_map[index].phys = base; - apple_mem_map[index].size = size; - apple_mem_map[index].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_INNER_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; + /* Align framebuffer mapping to page boundaries */ + size += (base - ALIGN_DOWN(base, SZ_4K)); + base = ALIGN_DOWN(base, SZ_4K); + size = ALIGN(size, SZ_4K); - return 0; + /* Add framebuffer mapping */ + mem_map[i - 1].virt = base; + mem_map[i - 1].phys = base; + mem_map[i - 1].size = size; } -int dram_init_banksize(void) +void enable_caches(void) { - return fdtdec_setup_memory_banksize(); -} + build_mem_map(); -extern long fw_dtb_pointer; - -void *board_fdt_blob_setup(int *err) -{ - /* Return DTB pointer passed by m1n1 */ - *err = 0; - return (void *)fw_dtb_pointer; + icache_enable(); + dcache_enable(); } -ulong board_get_usable_ram_top(ulong total_size) +u64 get_page_table_size(void) { - /* - * Top part of RAM is used by firmware for things like the - * framebuffer. This gives us plenty of room to play with. - */ - return 0x980000000; + return SZ_256K; } -- 2.34.1

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[PATCH] arm64: zynqmp: Remove additional gpio header from dlc21
by Michal Simek 21 Feb '22

21 Feb '22

This header shouldn't be in this file and there is already pointer to dt-bindings/gpio/gpio.h. Fixes: d2d14383bae4 ("arm64: zynqmp: Add support for DLC21 (Smartlynq+) board") Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- arch/arm/dts/zynqmp-dlc21-revA.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts index cf0aadf03ca4..0461219ca3e7 100644 --- a/arch/arm/dts/zynqmp-dlc21-revA.dts +++ b/arch/arm/dts/zynqmp-dlc21-revA.dts @@ -12,7 +12,6 @@ #include "zynqmp-clk-ccf.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/phy/phy.h> -#include <include/dt-bindings/gpio/gpio.h> / { model = "Smartlynq+ DLC21 RevA"; -- 2.35.0

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[PATCH 0/5] xilinx: Fix issues in v2022.04-rc1/2
by Michal Simek 21 Feb '22

21 Feb '22

Hi, I found that two commits which were recently merged to u-boot are breaking especially Xilinx ZynqMP boards. The commit 985503439762 ("fdt: Don't call board_fdt_blob_setup() and commit 0dba45864b2a ("arm: Init the debug UART") requires changes in platform to get u-boot work as worked before. Thanks, Michal Michal Simek (5): xilinx: Enable OF_BOARD for zynq and zynqmp boards arm64: zynqmp: Build psu_spl_init for SPL all the time arm64: zynqmp: Fix dependencies around ZYNQMP_PSU_INIT_ENABLED ARM: zynq: Fix debug uart initialization arm64: zynqmp: Fix debug uart initialization arch/arm/Kconfig | 2 ++ arch/arm/mach-zynq/spl.c | 15 +++++---- arch/arm/mach-zynqmp/Kconfig | 1 + arch/arm/mach-zynqmp/Makefile | 2 +- .../mach-zynqmp/include/mach/psu_init_gpl.h | 1 + arch/arm/mach-zynqmp/spl.c | 12 ++++++- board/xilinx/common/board.c | 3 +- board/xilinx/zynq/board.c | 7 ++++ board/xilinx/zynqmp/zynqmp.c | 32 +++++++++++++------ configs/xilinx_zynq_virt_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 3 +- 11 files changed, 59 insertions(+), 20 deletions(-) -- 2.35.0

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[PATCH v1] imx: imx8qm: cgtqmx8: switch to binman
by Oliver Graute 21 Feb '22

21 Feb '22

Switch to use binman to pack images Signed-off-by: Oliver Graute <oliver.graute(a)kococonnector.com> --- arch/arm/dts/imx8qm-cgtqmx8.dts | 1 + arch/arm/mach-imx/imx8/Kconfig | 1 + board/congatec/cgtqmx8/imximage.cfg | 4 ++-- configs/cgtqmx8_defconfig | 2 +- doc/board/congatec/cgtqmx8.rst | 3 +-- 5 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/arm/dts/imx8qm-cgtqmx8.dts b/arch/arm/dts/imx8qm-cgtqmx8.dts index 555c357f6f..919d00644f 100644 --- a/arch/arm/dts/imx8qm-cgtqmx8.dts +++ b/arch/arm/dts/imx8qm-cgtqmx8.dts @@ -12,6 +12,7 @@ /memreserve/ 0x80000000 0x00020000; #include "fsl-imx8qm.dtsi" +#include "imx8qm-u-boot.dtsi" / { model = "Congatec QMX8 Qseven series"; diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 6cd321fbb6..6e4b25961f 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -75,6 +75,7 @@ config TARGET_IMX8QM_MEK config TARGET_CONGA_QMX8 bool "Support congatec conga-QMX8 board" + select BINMAN select BOARD_LATE_INIT select SUPPORT_SPL select IMX8QM diff --git a/board/congatec/cgtqmx8/imximage.cfg b/board/congatec/cgtqmx8/imximage.cfg index e324c7ca37..58eeef54f6 100644 --- a/board/congatec/cgtqmx8/imximage.cfg +++ b/board/congatec/cgtqmx8/imximage.cfg @@ -5,8 +5,8 @@ #define __ASSEMBLY__ -/* Boot from SD, sector size 0x400 */ -BOOT_FROM SD 0x400 +BOOT_FROM sd + /* SoC type IMX8QM */ SOC_TYPE IMX8QM /* Append seco container image */ diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig index 34aca6ea85..48433bdef9 100644 --- a/configs/cgtqmx8_defconfig +++ b/configs/cgtqmx8_defconfig @@ -18,7 +18,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +# CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx8/imximage.cfg" CONFIG_BOOTDELAY=3 CONFIG_LOG=y diff --git a/doc/board/congatec/cgtqmx8.rst b/doc/board/congatec/cgtqmx8.rst index bccdef2f16..16711a844d 100644 --- a/doc/board/congatec/cgtqmx8.rst +++ b/doc/board/congatec/cgtqmx8.rst @@ -57,8 +57,7 @@ Build U-Boot $ export ATF_LOAD_ADDR=0x80000000 $ export BL33_LOAD_ADDR=0x80020000 $ make cgtqmx8_defconfig - $ make u-boot.bin - $ make flash.bin + $ make Flash the binary into the SD card --------------------------------- -- 2.17.1

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[RFC PATCH v2 0/8] FWU: Add FWU Multi Bank Update for DeveloerBox
by Masami Hiramatsu 21 Feb '22

21 Feb '22

Hi, Here is the 2nd version of RFC series of patches for the FWU Multi Bank Update support for the DeveloperBox platform. This series depends on Sughosh's Multi Bank Update v4 [1]. [1] https://lore.kernel.org/all/20220207182001.31270-1-sughosh.ganu@linaro.org/… Unlike the STM32MP board, DeveloperBox (SynQuacer) loads the firmware from SPI NOR flash. Thus it doesn't use GPT partitions to store the firmware banks and the FWU metadata. Instead, it stores those data at fixed address areas on SPI NOR flash. I carefully chose the areas which doesn't overlap the previous firmware and EDK2. This adds FWU metadata SF driver for this FWU multi bank support on SPI flash without GPT. This is identified by "u-boot,fwu-mdata-sf". The last patch adds the DT bindings in YAML. Since there is no GPT, the location GUID for images and the image GUID for banks are Null GUID. I will fix this with uuid property for fixed-partition devicetree afterwards. And the SynQuacer also does not have any non-volatile register. Thus this allocates the platform defined boot index on the SPI flash too. NOTE: To use this series, you also need to update SCP firmware[2] and TF-A[3] on the DeveloperBox. Those are under cleaning up. [2] https://git.linaro.org/people/masami.hiramatsu/SCP-firmware.git/ [3] https://git.linaro.org/people/masami.hiramatsu/arm-trusted-firmware.git/ Thank you, --- Masami Hiramatsu (8): FWU: Calculate CRC32 in fwu_update_mdata() FWU: Free metadata copy if gpt_get_mdata() failed synquacer: Update for TBBR based new FIP layout dt/bindings: firmware: Add FWU metadata on SPI flash binding FWU: Add FWU metadata access driver for SPI flash FWU: synquacer: Add FWU Multi bank update support for DeveloperBox FWU: synquacer: Initialize broken metadata configs: synquacer: Add FWU support for DeveloperBox .../dts/synquacer-sc2a11-developerbox-u-boot.dtsi | 33 ++ board/socionext/developerbox/Kconfig | 24 ++ board/socionext/developerbox/Makefile | 1 board/socionext/developerbox/fwu_plat.c | 238 ++++++++++++++++ configs/synquacer_developerbox_defconfig | 12 + .../firmware/fwu-mdata-sf.yaml | 38 +++ drivers/fwu-mdata/Kconfig | 9 + drivers/fwu-mdata/Makefile | 1 drivers/fwu-mdata/fwu-mdata-uclass.c | 57 +--- drivers/fwu-mdata/fwu_mdata_gpt_blk.c | 49 ++- drivers/fwu-mdata/fwu_mdata_sf.c | 294 ++++++++++++++++++++ include/configs/synquacer.h | 14 + include/fwu.h | 2 13 files changed, 698 insertions(+), 74 deletions(-) create mode 100644 board/socionext/developerbox/fwu_plat.c create mode 100644 doc/device-tree-bindings/firmware/fwu-mdata-sf.yaml create mode 100644 drivers/fwu-mdata/fwu_mdata_sf.c -- Masami Hiramatsu <masami.hiramatsu(a)linaro.org>

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[PATCH] arm: socfpga: vining: Fix mtdparts for 2x256 MiB SF variant
by Marek Vasut 21 Feb '22

21 Feb '22

The 2x256 MiB SF variant of this system has 192 MiB rootfs MTD partition containing UBI on SF0, use the correct size in U-Boot environment, else U-Boot cannot mount UBI and boot on this variant. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim(a)intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> Cc: Tien Fong Chee <tien.fong.chee(a)intel.com> Cc: Tom Rini <trini(a)konsulko.com> --- include/configs/socfpga_vining_fpga.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index d9d0a4af5ac..abf774449ba 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -61,7 +61,7 @@ "256k(softing1)," \ "256k(softing2)," \ "14720k(rcvrfs)," /* Recovery */ \ - "64m(rootfs)," /* Root */ \ + "192m(rootfs)," /* Root */ \ "-(userfs)\0" /* User */ \ "mtdparts_1_128m=ff705000.spi.1:" /* 16MiB+128MiB SF config */ \ "64m(rootfs)," \ -- 2.34.1

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