February 2022 - U-Boot

[PATCH 1/2] net: ravb: Add tx/rx delay flag checks and support for rgmii-rxid
by Adam Ford 25 Feb '22

25 Feb '22

Some boards like the Beacon RZ/G2 SOM use either flags for tx-internal-delay-ps, rx-internal-delay-ps or rgmii-rxid. In Linux the APSR_RDM flag is set when either rx-internal-delay-ps is set or the mode is rgmii-rxid, and the APSR_TDM is set when tx-internal-delay-ps is found or rgmii-txid is set, and both are set if rgmii-id is set. The ravb driver in U-Boot driver was missing rgmii-rxid support, so add that support in a similar fashion to what is done in Linux. Signed-off-by: Adam Ford <aford173(a)gmail.com> diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index 1d1118c341..9e09e998e3 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -52,6 +52,7 @@ #define CSR_OPS 0x0000000F #define CSR_OPS_CONFIG BIT(1) +#define APSR_RDM BIT(13) #define APSR_TDM BIT(14) #define TCCR_TSRQ0 BIT(0) @@ -376,6 +377,8 @@ static int ravb_dmac_init(struct udevice *dev) struct ravb_priv *eth = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); int ret = 0; + int mode = 0; + unsigned int delay; /* Set CONFIG mode */ ret = ravb_reset(dev); @@ -402,9 +405,25 @@ static int ravb_dmac_init(struct udevice *dev) (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995)) return 0; - if ((pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) || - (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)) - writel(APSR_TDM, eth->iobase + RAVB_REG_APSR); + if (!dev_read_u32(dev, "tx-internal-delay-ps", &delay)) { + if (delay) + mode |= APSR_TDM; + } + + if (!dev_read_u32(dev, "rx-internal-delay-ps", &delay)) { + if (delay) + mode |= APSR_RDM; + } + + if (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || + pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) + mode |= APSR_RDM; + + if (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || + pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) + mode |= APSR_TDM; + + writel(mode, eth->iobase + RAVB_REG_APSR); return 0; } -- 2.32.0

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[RFC PATCH v2 0/4] enable menu-driven boot device selection
by Masahisa Kojima 25 Feb '22

25 Feb '22

This patch series adds the menu-driven boot device selection. This menu also provides the functionality to add and delete Boot#### variable, and edit the BootOrder variable. This menu appears with the command "bootefi bootmgr", the menu structure is as follows. * Menu structure [Boot Manager] -> select Boot#### to boot [Boot Manager Maintenance] - [Add Boot Option] -> add new Boot#### variable - [Delete Boot Option] -> delete existing Boot#### variable - [Change Boot Order] -> update BootOrder variable * Things to consider - eliminate EFI_CALLs - replacement of ANSI_CLEAR_CONSOLE * Remaining items - Support of adding Boot#### other than block device(e.g. network) - error notification Masahisa Kojima (4): efi_loader: add menu-driven boot device selection lib/charset: add u16_strlcat() function test: unit test for u16_strlcat() efi_loader: add menu-driven UEFI Boot Variable maintenance cmd/bootmenu.c | 145 ----- common/menu.c | 137 ++++ include/charset.h | 15 + include/efi_loader.h | 27 + include/menu.h | 20 + lib/charset.c | 20 + lib/efi_loader/Kconfig | 20 + lib/efi_loader/efi_bootmgr.c | 1105 ++++++++++++++++++++++++++++++++- lib/efi_loader/efi_boottime.c | 55 +- lib/efi_loader/efi_console.c | 81 +++ lib/efi_loader/efi_file.c | 74 ++- test/unicode_ut.c | 45 ++ 12 files changed, 1548 insertions(+), 196 deletions(-) -- 2.17.1

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[PATCH] arm: am33xx: Fix early debug UART initialization
by Felix Brack 25 Feb '22

25 Feb '22

The changes from commit 0dba45864b2a ("arm: Init the debug UART") prevent the early debug UART from being initialized correctly. By adding a new SoC specific early UART initialization function this patch provides a generic location to add the required code. This code has to be SoC and not board specific. For the am33xx SoCs the fix consist of configuring early clocks. Signed-off-by: Felix Brack <fb(a)ltec.ch> --- arch/arm/mach-omap2/am33xx/board.c | 7 +++++++ drivers/serial/Kconfig | 13 +++++++++++++ include/debug_uart.h | 15 +++++++++++++++ 3 files changed, 35 insertions(+) diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index c44667668e..a7f0445b93 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -604,3 +604,10 @@ int arch_cpu_init_dm(void) #endif return 0; } + +#if IS_ENABLED(CONFIG_DEBUG_UART_SOC_INIT) +void soc_debug_uart_init(void) +{ + setup_early_clocks(); +} +#endif diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 345d1881f5..3da4064d35 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -490,6 +490,19 @@ config DEBUG_UART_SHIFT value. Use this value to specify the shift to use, where 0=byte registers, 2=32-bit word registers, etc. +config DEBUG_UART_SOC_INIT + bool "Enable SoC-specific debug UART init" + depends on DEBUG_UART + help + Boards using the same SoC might require some common settings before + the debug UART can be used. The board specific board_debug_uart_init() + is not the right place for such common settings as they would apply + to a specific board only instead of all boards using the same SoC. + When this option is enabled, the SoC specific function + soc_debug_uart_init() will be called when debug_uart_init() is called. + You can put any code here that is needed to set up the UART ready for + use. + config DEBUG_UART_BOARD_INIT bool "Enable board-specific debug UART init" depends on DEBUG_UART diff --git a/include/debug_uart.h b/include/debug_uart.h index 714b369e6f..ebc84c44cd 100644 --- a/include/debug_uart.h +++ b/include/debug_uart.h @@ -42,6 +42,12 @@ * - Immediately afterwards, add DEBUG_UART_FUNCS to define the rest of the * functionality (printch(), etc.) * + * If your SoC needs additional init for the UART to work, enable + * CONFIG_DEBUG_UART_SOC_INIT and write a function called + * soc_debug_uart_init() to perform that init. When debug_uart_init() is + * called, the init will happen automatically. Board specific code does not + * go here, see board_debug_uart_init() below. + * * If your board needs additional init for the UART to work, enable * CONFIG_DEBUG_UART_BOARD_INIT and write a function called * board_debug_uart_init() to perform that init. When debug_uart_init() is @@ -61,6 +67,14 @@ */ void debug_uart_init(void); +#ifdef CONFIG_DEBUG_UART_SOC_INIT +void soc_debug_uart_init(void); +#else +static inline void soc_debug_uart_init(void) +{ +} +#endif + #ifdef CONFIG_DEBUG_UART_BOARD_INIT void board_debug_uart_init(void); #else @@ -192,6 +206,7 @@ void printdec(unsigned int value); \ void debug_uart_init(void) \ { \ + soc_debug_uart_init(); \ board_debug_uart_init(); \ _debug_uart_init(); \ _DEBUG_UART_ANNOUNCE \ -- 2.25.1

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[PATCH v2 1/2] ram: stm32mp1: Unconditionally enable ASR
by Marek Vasut 25 Feb '22

25 Feb '22

Enable DRAM ASR, auto self-refresh, unconditionally. This saves non-trivial amount of power both at runtime and in suspend (on 2x W632GU6NB-15 ~150mW). Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> --- V2: Rebase on latest changes in this driver past v2022.01 --- drivers/ram/stm32mp1/stm32mp1_ddr.c | 25 ++++++++++++++++++++++++ drivers/ram/stm32mp1/stm32mp1_ddr_regs.h | 6 ++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c index 4d78aa5cb13..04fc8eab909 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr.c +++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c @@ -27,6 +27,8 @@ #define RCC_DDRITFCR_DPHYAPBRST (BIT(17)) #define RCC_DDRITFCR_DPHYRST (BIT(18)) #define RCC_DDRITFCR_DPHYCTLRST (BIT(19)) +#define RCC_DDRITFCR_DDRCKMOD_MASK (0x7 << 20) +#define RCC_DDRITFCR_DDRCKMOD_ASR (0x1 << 20) struct reg_desc { const char *name; @@ -651,6 +653,26 @@ static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl, wait_sw_done_ack(ctl); } +static void stm32mp1_asr_enable(struct ddr_info *priv) +{ + struct stm32mp1_ddrctl *ctl = priv->ctl; + + clrsetbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCKMOD_MASK, + RCC_DDRITFCR_DDRCKMOD_ASR); + + start_sw_done(ctl); + + setbits_le32(&ctl->hwlpctl, DDRCTRL_HWLPCTL_HW_LP_EN); + writel(DDRCTRL_PWRTMG_POWERDOWN_TO_X32(0x10) | + DDRCTRL_PWRTMG_SELFREF_TO_X32(0x01), + &ctl->pwrtmg); + setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE); + setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN); + + setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); + wait_sw_done_ack(ctl); +} + /* board-specific DDR power initializations. */ __weak int board_ddr_power_init(enum ddr_type ddr_type) { @@ -822,6 +844,9 @@ start: stm32mp1_refresh_restore(priv->ctl, config->c_reg.rfshctl3, config->c_reg.pwrctl); +/* Enable auto-self-refresh, which saves a bit of power at runtime. */ + stm32mp1_asr_enable(priv); + /* enable uMCTL2 AXI port 0 and 1 */ setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN); setbits_le32(&priv->ctl->pctrl_1, DDRCTRL_PCTRL_N_PORT_EN); diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h index f1a26e31f6c..42be1ba57c7 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h +++ b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h @@ -265,8 +265,14 @@ struct stm32mp1_ddrphy { #define DDRCTRL_PWRCTL_SELFREF_EN BIT(0) #define DDRCTRL_PWRCTL_POWERDOWN_EN BIT(1) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3) #define DDRCTRL_PWRCTL_SELFREF_SW BIT(5) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32(n) (((n) & 0xff) << 16) +#define DDRCTRL_PWRTMG_POWERDOWN_TO_X32(n) ((n) & 0x1f) + +#define DDRCTRL_HWLPCTL_HW_LP_EN BIT(0) + #define DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH BIT(0) #define DDRCTRL_RFSHTMG_T_RFC_NOM_X1_X32_MASK GENMASK(27, 16) -- 2.34.1

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[PATCH 1/2] ARM: imx: imx8mn-evk: generate a single bootable flash.bin
by Heiko Thiery 24 Feb '22

24 Feb '22

To have a flash.bin file that also contains the U-Boot and TF-A/ATF create this like already done for other imx8 boards. Signed-off-by: Heiko Thiery <heiko.thiery(a)gmail.com> --- arch/arm/dts/imx8mn-evk-u-boot.dtsi | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/imx8mn-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-evk-u-boot.dtsi index 3db46d4cbc..d1427941eb 100644 --- a/arch/arm/dts/imx8mn-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-evk-u-boot.dtsi @@ -58,7 +58,9 @@ }; - flash { + spl { + filename = "spl.bin"; + mkimage { args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000"; @@ -125,4 +127,19 @@ }; }; }; + + imx-boot { + filename = "flash.bin"; + pad-byte = <0x00>; + + spl: blob-ext@1 { + offset = <0x0>; + filename = "spl.bin"; + }; + + uboot: blob-ext@2 { + offset = <0x58000>; + filename = "u-boot.itb"; + }; + }; }; -- 2.30.2

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RE:Re: [PATCH 1/2] fsl-layerscape: add dtb overlay feature
by Sahil Malhotra (OSS) 24 Feb '22

24 Feb '22

Hi Michael, > -----Original Message----- > From: Michael Walle <michael(a)walle.cc> > Sent: Thursday, December 23, 2021 3:05 PM > To: Sahil Malhotra (OSS) <sahil.malhotra(a)oss.nxp.com> > Cc: ZHIZHIKIN Andrey <andrey.zhizhikin(a)leica-geosystems.com>; Clément Faure > <clement.faure(a)nxp.com>; Gaurav Jain <gaurav.jain(a)nxp.com>; Pankaj Gupta > <pankaj.gupta(a)nxp.com>; Priyanka Jain <priyanka.jain(a)nxp.com>; u- > boot(a)lists.denx.de; Varun Sethi <V.Sethi(a)nxp.com>; Ye Li <ye.li(a)nxp.com> > Subject: Re: [EXT] Re: [PATCH 1/2] fsl-layerscape: add dtb overlay feature > > Hi Sahil, > > Am 2021-12-23 09:46, schrieb Sahil Malhotra (OSS): > >> -----Original Message----- > >> From: U-Boot <u-boot-bounces(a)lists.denx.de> On Behalf Of Michael > >> Walle > >> Sent: Monday, December 20, 2021 6:23 PM > >> To: Sahil Malhotra (OSS) <sahil.malhotra(a)oss.nxp.com> > >> Cc: ZHIZHIKIN Andrey <andrey.zhizhikin(a)leica-geosystems.com>; Clément > >> Faure <clement.faure(a)nxp.com>; Gaurav Jain <gaurav.jain(a)nxp.com>; > >> Pankaj Gupta <pankaj.gupta(a)nxp.com>; Priyanka Jain > >> <priyanka.jain(a)nxp.com>; u-boot(a)lists.denx.de; Varun Sethi > >> <V.Sethi(a)nxp.com>; Ye Li <ye.li(a)nxp.com> > >> Subject: [EXT] Re: [PATCH 1/2] fsl-layerscape: add dtb overlay > >> feature > >> > >> Caution: EXT Email > >> > >> Hi Sahil, > >> > >> Am 2021-12-10 07:33, schrieb Sahil Malhotra (OSS): > >> >> DT nodes can be statically disabled if we know that they are held > >> >> by HAB and are not released to NS World. > >> >> > >> >> OP-TEE does set the status itself via dt_enable_secure_status(), > >> >> which should present the properly configured FDT when U-Boot takes > >> over. > >> > Yes, OP-TEE set the status by dt_enable_secure_status() in DTB > >> > overlay which gets merged with DTB provided for Linux bootup and > >> > then Linux boots with merged DTB. > >> > But u-boot uses the DTB embedded in its image. How can we modify > >> > that DTB or merge DTB overlay passed by OP-TEE with uboot DTB ? > >> > >> But then u-boot has the "wrong" dtb. What is the reason, there is an > >> overlay instead of a whole dtb? what if the overlay doesn't match the > >> dtb? > > "wrong" dtb means that uboot will not be aware of CAAM job ring which > > is taken by OP-TEE and uboot on LS platforms currently use JR0, which > > is not being used by any other entity in LS bootflow. > > I don't know I follow. u-boot and linux should have the same device tree; > regardless if that device is used or not. So applying the overlay just for linux isn't > enough here. Ok, I don't think that as of now, in all platforms uboot and linux have same devie tree. But I will try to address your concern, but I don’t know how to apply overlay to dtb which is embedded in u-boot binary, Can you please point me to one reference which is doing this thing, I will take reference from there. > > We don't use DTB in OP-TEE, but when we use CAAM in OP-TEE, OP-TEE > > reserves One Job Ring for its use and that is communicated to Kernel > > using DTB overlay. > > > >> what if the overlay doesn't match the dtb? > > I didn't get this point, can you please elaborate a little. > > You are merging a dtb fragment with an unknown dtb, right? Who says they > match? you might have an old dtb where the supplied dtb fragment doesn't > make any sense. > > I might be missing something here. Eg. where is the linux dtb supposed to come > from? This patchset is really missing an example and a description how things > should work. If supplied DTB does not match with DTB overlay fragment. then overlay will not get applied. We don't have any control on where user picks the DTB, but we can only make sure DTB overlay feature must work with DTBs which are upstreamed If user makes its own customized DTB, we cannot make sure that things will work. Regards, Sahil Malhotra

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[PATCH] ARM: imx: imx8mn-evk: change environment address variables
by Heiko Thiery 24 Feb '22

24 Feb '22

Currently the space between kernel_addr_r and the fdt_addr_r is only 32MB. To have enought space to load kernel images bigger than 32MB change the variables to a feasible value. The new environment variables layout is based on the scheme from "include/configs/ti_armv7_common.h". The CONFIG_SYS_LOAD_ADDR value is set to 0x42000000. With that we have the same value as for the kernel_addr_r. Signed-off-by: Heiko Thiery <heiko.thiery(a)gmail.com> --- configs/imx8mn_ddr4_evk_defconfig | 2 +- configs/imx8mn_evk_defconfig | 2 +- include/configs/imx8mn_evk.h | 18 ++++++++++++++---- 3 files changed, 16 insertions(+), 6 deletions(-) diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 27bf5ec05a..c13885ab5e 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -18,7 +18,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig index 807d126b21..95ac6f85fa 100644 --- a/configs/imx8mn_evk_defconfig +++ b/configs/imx8mn_evk_defconfig @@ -20,7 +20,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 142fc3e4ff..d51f87f57d 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -38,20 +38,30 @@ #include <config_distro_bootcmd.h> #endif + + /* Initial environment variables */ +/* see include/configs/ti_armv7_common.h */ +#define ENV_MEM_LAYOUT_SETTINGS \ + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_addr_r=0x42000000\0" \ + "fdt_addr_r=0x48000000\0" \ + "fdtoverlay_addr_r=0x49000000\0" \ + "ramdisk_addr_r=0x48080000\0" \ + "initrd_addr=0x48080000\0" \ + "scriptaddr=0x40000000\0" \ + "pxefile_addr_r=0x40100000\0" + #define CONFIG_EXTRA_ENV_SETTINGS \ "image=Image\0" \ BOOTENV \ - "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "console=ttymxc1,115200\0" \ - "fdt_addr_r=0x43000000\0" \ "boot_fit=no\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "initrd_addr=0x43800000\0" \ "bootm_size=0x10000000\0" \ "mmcpart=1\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + ENV_MEM_LAYOUT_SETTINGS /* Link Definitions */ -- 2.30.2

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[PATCH] gpio: rgpio2p: Enhance reading of GPIO pin value
by Christoph Fritz 24 Feb '22

24 Feb '22

Add support for reading GPIO pin value when function is output. With this patch applied, gpio toggle command is working. Signed-off-by: Christoph Fritz <chf.fritz(a)googlemail.com> --- drivers/gpio/imx_rgpio2p.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/imx_rgpio2p.c b/drivers/gpio/imx_rgpio2p.c index 0e2874ca95c..175e460aff5 100644 --- a/drivers/gpio/imx_rgpio2p.c +++ b/drivers/gpio/imx_rgpio2p.c @@ -39,6 +39,14 @@ static int imx_rgpio2p_is_output(struct gpio_regs *regs, int offset) return val & (1 << offset) ? 1 : 0; } +static int imx_rgpio2p_bank_get_direction(struct gpio_regs *regs, int offset) +{ + if ((readl(&regs->gpio_pddr) >> offset) & 0x01) + return IMX_RGPIO2P_DIRECTION_OUT; + + return IMX_RGPIO2P_DIRECTION_IN; +} + static void imx_rgpio2p_bank_direction(struct gpio_regs *regs, int offset, enum imx_rgpio2p_direction direction) { @@ -67,7 +75,11 @@ static void imx_rgpio2p_bank_set_value(struct gpio_regs *regs, int offset, static int imx_rgpio2p_bank_get_value(struct gpio_regs *regs, int offset) { - return (readl(&regs->gpio_pdir) >> offset) & 0x01; + if (imx_rgpio2p_bank_get_direction(regs, offset) == + IMX_RGPIO2P_DIRECTION_IN) + return (readl(&regs->gpio_pdir) >> offset) & 0x01; + + return (readl(&regs->gpio_pdor) >> offset) & 0x01; } static int imx_rgpio2p_direction_input(struct udevice *dev, unsigned offset) -- 2.30.2

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[PATCH 1/2] ARM: imx: imx8mn-*-evk: use reset-gpios in phy node
by Heiko Thiery 24 Feb '22

24 Feb '22

To be in sync with the linux devicetree change the 'phy-reset-gpios' in the fec node to 'reset-gpios' in the phy node. The PHY reset will be done by the eth-phy-uclass driver while probing the PHY. This is ok since it is done before probing the fec. Signed-off-by: Heiko Thiery <heiko.thiery(a)gmail.com> --- arch/arm/dts/imx8mn-evk.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi index fc2c7f1d44..ed865444da 100644 --- a/arch/arm/dts/imx8mn-evk.dtsi +++ b/arch/arm/dts/imx8mn-evk.dtsi @@ -53,7 +53,6 @@ pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <&ethphy0>; - phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; fsl,magic-packet; status = "okay"; @@ -64,6 +63,8 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; vddio-supply = <&vddio>; vddio: vddio-regulator { -- 2.30.2

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[PATCH v3] ARM: imx: imx8mn-*-evk: use DM settings for PHY configuration
by Heiko Thiery 24 Feb '22

24 Feb '22

With the correct settings described in the device-tree the PHY settings in the board init are no longer required. The values are taken from the linux device tree. The PHY latency settings are derived from the phy-mode property and the voltage seetings are done via the regulator. Suggested-by: Michael Walle <michael(a)walle.cc> Signed-off-by: Heiko Thiery <heiko.thiery(a)gmail.com> --- v2: - remove phy-reset-gpios node (thanks to Michael) When using DM_ETH_PHY the reset-gpios from the phy is used v3: - Only change remove/replace the voltage settings and the delay settings. The pyh-reset-gpios vs. reset-gpios settings has to be discussed arch/arm/dts/imx8mn-evk.dtsi | 6 ++++++ board/freescale/imx8mn_evk/imx8mn_evk.c | 16 ---------------- 2 files changed, 6 insertions(+), 16 deletions(-) diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi index 416fadb22b..fc2c7f1d44 100644 --- a/arch/arm/dts/imx8mn-evk.dtsi +++ b/arch/arm/dts/imx8mn-evk.dtsi @@ -64,6 +64,12 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + vddio-supply = <&vddio>; + + vddio: vddio-regulator { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; }; }; diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.c b/board/freescale/imx8mn_evk/imx8mn_evk.c index b24342fd5c..e35d505aea 100644 --- a/board/freescale/imx8mn_evk/imx8mn_evk.c +++ b/board/freescale/imx8mn_evk/imx8mn_evk.c @@ -27,22 +27,6 @@ static void setup_fec(void) clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); } -int board_phy_config(struct phy_device *phydev) -{ - /* enable rgmii rxc skew and phy mode select to RGMII copper */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); - - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); - - if (phydev->drv->config) - phydev->drv->config(phydev); - return 0; -} - int board_init(void) { setup_fec(); -- 2.30.2

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