November 2022 - U-Boot

[PATCH] riscv: use imply instead of select for SPL_SEPARATE_BSS
by Zong Li 29 Nov '22

29 Nov '22

Use imply instead of select, then it can still be disabled by board-specific defconfig, or be set to n manually. Signed-off-by: Zong Li <zong.li(a)sifive.com> --- arch/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/Kconfig b/arch/Kconfig index ae39716697..102956d24c 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -111,7 +111,7 @@ config RISCV select SUPPORT_OF_CONTROL select OF_CONTROL select DM - select SPL_SEPARATE_BSS if SPL + imply SPL_SEPARATE_BSS if SPL imply DM_SERIAL imply DM_ETH imply DM_EVENT -- 2.17.1

3 4

[PATCH v20 0/4] add TCP and HTTP for downloading images
by Ying-Chun Liu (PaulLiu) 29 Nov '22

29 Nov '22

From: "Ying-Chun Liu (PaulLiu)" <paul.liu(a)linaro.org> This patch is a refresh from previous patches made by Duncan Hare <DuncanCHare at yahoo.com>. I've contacted him and continue to work on this patch. This patch introduce a TCP stack with SACK. And a simple wget command to download images from http server. v1-v12: Made by Duncan, didn't tracked. v13: Fix some issues which is reviewed by Christian v14: Add options to enable/disable SACK. v15: Fix various syntax errors reviewed by Michal. Remove magic numbers. Use kernel-doc format. v16: Add more kernel-doc. Fix more double spaces. v17: Fix wget with address timeout issue reported by Ramon. v18: Add documentation for wget command. v19: Add unit test for wget command. v20: Rebase to latest master and resolve conflict. Ying-Chun Liu (PaulLiu) (4): net: Add TCP protocol net: Add wget application doc: cmd: wget: add documentation test: cmd: add test for wget command. cmd/Kconfig | 7 + cmd/net.c | 13 + doc/usage/cmd/wget.rst | 61 ++++ doc/usage/index.rst | 1 + include/net.h | 38 ++- include/net/tcp.h | 299 +++++++++++++++++ include/net/wget.h | 22 ++ net/Kconfig | 16 + net/Makefile | 2 + net/net.c | 36 +++ net/tcp.c | 720 +++++++++++++++++++++++++++++++++++++++++ net/wget.c | 438 +++++++++++++++++++++++++ test/cmd/Makefile | 1 + test/cmd/wget.c | 206 ++++++++++++ 14 files changed, 1850 insertions(+), 10 deletions(-) create mode 100644 doc/usage/cmd/wget.rst create mode 100644 include/net/tcp.h create mode 100644 include/net/wget.h create mode 100644 net/tcp.c create mode 100644 net/wget.c create mode 100644 test/cmd/wget.c -- 2.35.1

7 18

[PATCH] phy: add driver for Intel XWAY PHY
by Tim Harvey 28 Nov '22

28 Nov '22

Add a driver for the Intel XWAY GbE PHY: - configure RGMII using dt phy-mode and standard delay properties - use genphy_config Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- drivers/net/phy/Kconfig | 5 ++++ drivers/net/phy/Makefile | 1 + drivers/net/phy/intel_xway.c | 48 ++++++++++++++++++++++++++++++++++++ drivers/net/phy/phy.c | 3 +++ include/phy.h | 1 + 5 files changed, 58 insertions(+) create mode 100644 drivers/net/phy/intel_xway.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 52ce08b3b384..86e698190f81 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -321,6 +321,11 @@ config PHY_XILINX_GMII2RGMII as bridge between MAC connected over GMII and external phy that is connected over RGMII interface. +config PHY_XWAY + bool "Intel XWAY PHY support" + help + This adds support for the Intel XWAY (formerly Lantiq) Gbe PHYs. + config PHY_ETHERNET_ID bool "Read ethernet PHY id" depends on DM_GPIO diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 9d87eb212c7c..d38e99e71716 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_PHY_TI_DP83867) += dp83867.o obj-$(CONFIG_PHY_TI_DP83869) += dp83869.o obj-$(CONFIG_PHY_XILINX) += xilinx_phy.o obj-$(CONFIG_PHY_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o +obj-$(CONFIG_PHY_XWAY) += intel_xway.o obj-$(CONFIG_PHY_ETHERNET_ID) += ethernet_id.o obj-$(CONFIG_PHY_VITESSE) += vitesse.o obj-$(CONFIG_PHY_MSCC) += mscc.o diff --git a/drivers/net/phy/intel_xway.c b/drivers/net/phy/intel_xway.c new file mode 100644 index 000000000000..dfce3f8332e9 --- /dev/null +++ b/drivers/net/phy/intel_xway.c @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <common.h> +#include <phy.h> +#include <linux/bitfield.h> + +#define XWAY_MDIO_MIICTRL 0x17 /* mii control */ + +#define XWAY_MDIO_MIICTRL_RXSKEW_MASK GENMASK(14, 12) +#define XWAY_MDIO_MIICTRL_TXSKEW_MASK GENMASK(10, 8) + +static int xway_config(struct phy_device *phydev) +{ + ofnode node = phy_get_ofnode(phydev); + u32 val = 0; + + if (ofnode_valid(node)) { + u32 rx_delay, tx_delay; + + rx_delay = ofnode_read_u32_default(node, "rx-internal-delay-ps", 2000); + tx_delay = ofnode_read_u32_default(node, "tx-internal-delay-ps", 2000); + val |= FIELD_PREP(XWAY_MDIO_MIICTRL_TXSKEW_MASK, rx_delay / 500); + val |= FIELD_PREP(XWAY_MDIO_MIICTRL_RXSKEW_MASK, tx_delay / 500); + phy_modify(phydev, MDIO_DEVAD_NONE, XWAY_MDIO_MIICTRL, + XWAY_MDIO_MIICTRL_TXSKEW_MASK | + XWAY_MDIO_MIICTRL_RXSKEW_MASK, val); + } + + genphy_config_aneg(phydev); + + return 0; +} + +static struct phy_driver XWAY_driver = { + .name = "XWAY", + .uid = 0xD565A400, + .mask = 0xffffff00, + .features = PHY_GBIT_FEATURES, + .config = xway_config, + .startup = genphy_startup, + .shutdown = genphy_shutdown, +}; + +int phy_xway_init(void) +{ + phy_register(&XWAY_driver); + + return 0; +} diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 90876630533e..92143cf23691 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -556,6 +556,9 @@ int phy_init(void) #ifdef CONFIG_PHY_XILINX phy_xilinx_init(); #endif +#ifdef CONFIG_PHY_XWAY + phy_xway_init(); +#endif #ifdef CONFIG_PHY_MSCC phy_mscc_init(); #endif diff --git a/include/phy.h b/include/phy.h index 0737c4e8f9ae..ff69536fca75 100644 --- a/include/phy.h +++ b/include/phy.h @@ -380,6 +380,7 @@ int phy_teranetics_init(void); int phy_ti_init(void); int phy_vitesse_init(void); int phy_xilinx_init(void); +int phy_xway_init(void); int phy_mscc_init(void); int phy_fixed_init(void); int phy_ncsi_init(void); -- 2.25.1

2 1

[PATCH] net: macb: Fix race caused by flushing unwanted descriptors
by Yaron Micher 28 Nov '22

28 Nov '22

The rx descriptor list is in cached memory, and there may be multiple descriptors per cache-line. After reclaim_rx_buffers marks a descriptor as unused it does a cache flush, which causes the entire cache-line to be written to memory, which may override other descriptors in the same cache-line that the controller may have written to. The fix skips freeing descriptors that are not the last in a cache-line, and if the freed descriptor is the last one in a cache-line, it marks all the descriptors in the cache-line as unused. This is similarly to what is done in drivers/net/fec_mxc.c In my case this bug caused tftpboot to fail some times when other packets are sent to u-boot in addition to the ongoing tftp (e.g. ping). The driver would stop receiving new packets because it is waiting on a descriptor that is marked unused, when in reality the descriptor contains a new unprocessed packet but while freeing the previous buffer descriptor & flushing the cache, the driver accidentally marked the descriptor as unused. Signed-off-by: Yaron Micher <yaronm(a)hailo.ai> --- drivers/net/macb.c | 51 +++++++++++++++++++++++++++++++++++----------- 1 file changed, 39 insertions(+), 12 deletions(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index e02a57b411..65ec1f24ad 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -98,6 +98,9 @@ struct macb_dma_desc_64 { #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE)) #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1)) +#define DESC_PER_CACHELINE_32 (ARCH_DMA_MINALIGN/sizeof(struct macb_dma_desc)) +#define DESC_PER_CACHELINE_64 (ARCH_DMA_MINALIGN/DMA_DESC_SIZE) + #define RXBUF_FRMLEN_MASK 0x00000fff #define TXBUF_FRMLEN_MASK 0x000007ff @@ -401,32 +404,56 @@ static int _macb_send(struct macb_device *macb, const char *name, void *packet, return 0; } +static void reclaim_rx_buffer(struct macb_device *macb, + unsigned int idx) +{ + unsigned int mask; + unsigned int shift; + unsigned int i; + + /* + * There may be multiple descriptors per CPU cacheline, + * so a cache flush would flush the whole line, meaning the content of other descriptors + * in the cacheline would also flush. If one of the other descriptors had been + * written to by the controller, the flush would cause those changes to be lost. + * + * To circumvent this issue, we do the actual freeing only when we need to free + * the last descriptor in the current cacheline. When the current descriptor is the + * last in the cacheline, we free all the descriptors that belong to that cacheline. + */ + if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) { + mask = DESC_PER_CACHELINE_64 - 1; + shift = 1; + } else { + mask = DESC_PER_CACHELINE_32 - 1; + shift = 0; + } + + /* we exit without freeing if idx is not the last descriptor in the cacheline */ + if ((idx & mask) != mask) + return; + + for (i = idx & (~mask); i <= idx; i++) + macb->rx_ring[i << shift].addr &= ~MACB_BIT(RX_USED); +} + static void reclaim_rx_buffers(struct macb_device *macb, unsigned int new_tail) { unsigned int i; - unsigned int count; i = macb->rx_tail; macb_invalidate_ring_desc(macb, RX); while (i > new_tail) { - if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) - count = i * 2; - else - count = i; - macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED); + reclaim_rx_buffer(macb, i); i++; - if (i > MACB_RX_RING_SIZE) + if (i >= MACB_RX_RING_SIZE) i = 0; } while (i < new_tail) { - if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) - count = i * 2; - else - count = i; - macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED); + reclaim_rx_buffer(macb, i); i++; } -- 2.17.1

2 1

[PATCH] drivers: net: aquantia: fix typos
by Tim Harvey 28 Nov '22

28 Nov '22

Fix a couple of typos: - s/Acquantia/Aquantia/ - s/firmare/firmware/ Signed-off-by: Tim Harvey <tharvey(a)gateworks.com> --- drivers/net/phy/aquantia.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index 7e950fe0c2fe..79fbc115368a 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -136,7 +136,7 @@ static int aquantia_read_fw(u8 **fw_addr, size_t *fw_length) *fw_addr = NULL; *fw_length = 0; - debug("Loading Acquantia microcode from %s %s\n", + debug("Loading Aquantia microcode from %s %s\n", CONFIG_PHY_AQUANTIA_FW_PART, CONFIG_PHY_AQUANTIA_FW_NAME); ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY); if (ret < 0) @@ -163,7 +163,7 @@ static int aquantia_read_fw(u8 **fw_addr, size_t *fw_length) *fw_addr = addr; *fw_length = length; - debug("Found Acquantia microcode.\n"); + debug("Found Aquantia microcode.\n"); cleanup: if (ret < 0) { @@ -257,7 +257,7 @@ static int aquantia_upload_firmware(struct phy_device *phydev) strlcpy(version, (char *)&addr[dram_offset + VERSION_STRING_OFFSET], VERSION_STRING_SIZE); - printf("%s loading firmare version '%s'\n", phydev->dev->name, version); + printf("%s loading firmware version '%s'\n", phydev->dev->name, version); /* stall the microcprocessor */ phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, @@ -288,7 +288,7 @@ static int aquantia_upload_firmware(struct phy_device *phydev) phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, UP_RUN_STALL_OVERRIDE); - printf("%s firmare loading done.\n", phydev->dev->name); + printf("%s firmware loading done.\n", phydev->dev->name); done: free(addr); return ret; -- 2.25.1

3 2

[PATCH 0/6] broken CVE fix (b85d130ea0ca)
by Rasmus Villemoes 28 Nov '22

28 Nov '22

tl;dr: b85d130ea0ca didn't fix the CVE(s), but did break tftp of certain file sizes - which is somewhat lucky, since that's how I noticed in the first place. What I at first hoped would be a one-liner trivial fix turned out to be much more complicated and led me down a rabbit hole of related fixes. And this isn't even complete, I'm afraid. Details in 3/6. 1 and 4 are independent of all the others. 5 is a trivial preparation for 6; otherwise those are also independent of the others. Finally, 2 and 3 are my attempts at actually fixing CVE-2022-{30790,30552}, with 2 essentially lifting the "ensure the payload has non-negative size" to the first place we can check that instead of relying on that check to happen in several places. Rasmus Villemoes (6): net: improve check for no IP options net: compare received length to sizeof(ip_hdr), not sizeof(ip_udp_hdr) net: (actually/better) deal with CVE-2022-{30790,30552} net: fix ip_len in reassembled IP datagram net: tftp: use IS_ENABLED(CONFIG_NET_TFTP_VARS) instead of #if net: tftp: sanitize tftp block size, especially for TX net/net.c | 24 +++++++++---- net/tftp.c | 102 ++++++++++++++++++++++++++++++++++++++--------------- 2 files changed, 92 insertions(+), 34 deletions(-) -- 2.37.2

4 23

[PATCH 1/2] net: dwc_eth_qos: Split TX and RX DMA rings
by Marek Vasut 28 Nov '22

28 Nov '22

Separate TX and RX DMA rings to make their handling slightly clearer. This is a preparatory patch for bulk RX descriptor flushing. Signed-off-by: Marek Vasut <marex(a)denx.de> --- Cc: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Patrice Chotard <patrice.chotard(a)foss.st.com> Cc: Patrick Delaunay <patrick.delaunay(a)foss.st.com> Cc: Ramon Fried <rfried.dev(a)gmail.com> Cc: Stephen Warren <swarren(a)nvidia.com> --- drivers/net/dwc_eth_qos.c | 33 ++++++++++++++++++++++----------- drivers/net/dwc_eth_qos.h | 3 ++- 2 files changed, 24 insertions(+), 12 deletions(-) diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 001b028fa13..dde2c183b06 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -75,9 +75,6 @@ */ static void *eqos_alloc_descs(struct eqos_priv *eqos, unsigned int num) { - eqos->desc_size = ALIGN(sizeof(struct eqos_desc), - (unsigned int)ARCH_DMA_MINALIGN); - return memalign(eqos->desc_size, num * eqos->desc_size); } @@ -89,8 +86,8 @@ static void eqos_free_descs(void *descs) static struct eqos_desc *eqos_get_desc(struct eqos_priv *eqos, unsigned int num, bool rx) { - return eqos->descs + - ((rx ? EQOS_DESCRIPTORS_TX : 0) + num) * eqos->desc_size; + return (rx ? eqos->rx_descs : eqos->tx_descs) + + (num * eqos->desc_size); } void eqos_inval_desc_generic(void *desc) @@ -1001,7 +998,8 @@ static int eqos_start(struct udevice *dev) /* Set up descriptors */ - memset(eqos->descs, 0, eqos->desc_size * EQOS_DESCRIPTORS_NUM); + memset(eqos->tx_descs, 0, eqos->desc_size * EQOS_DESCRIPTORS_TX); + memset(eqos->rx_descs, 0, eqos->desc_size * EQOS_DESCRIPTORS_RX); for (i = 0; i < EQOS_DESCRIPTORS_TX; i++) { struct eqos_desc *tx_desc = eqos_get_desc(eqos, i, false); @@ -1234,13 +1232,23 @@ static int eqos_probe_resources_core(struct udevice *dev) debug("%s(dev=%p):\n", __func__, dev); - eqos->descs = eqos_alloc_descs(eqos, EQOS_DESCRIPTORS_NUM); - if (!eqos->descs) { - debug("%s: eqos_alloc_descs() failed\n", __func__); + eqos->desc_size = ALIGN(sizeof(struct eqos_desc), + (unsigned int)ARCH_DMA_MINALIGN); + + eqos->tx_descs = eqos_alloc_descs(eqos, EQOS_DESCRIPTORS_TX); + if (!eqos->tx_descs) { + debug("%s: eqos_alloc_descs(tx) failed\n", __func__); ret = -ENOMEM; goto err; } + eqos->rx_descs = eqos_alloc_descs(eqos, EQOS_DESCRIPTORS_RX); + if (!eqos->rx_descs) { + debug("%s: eqos_alloc_descs(rx) failed\n", __func__); + ret = -ENOMEM; + goto err_free_tx_descs; + } + eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE); if (!eqos->tx_dma_buf) { debug("%s: memalign(tx_dma_buf) failed\n", __func__); @@ -1276,7 +1284,9 @@ err_free_rx_dma_buf: err_free_tx_dma_buf: free(eqos->tx_dma_buf); err_free_descs: - eqos_free_descs(eqos->descs); + eqos_free_descs(eqos->rx_descs); +err_free_tx_descs: + eqos_free_descs(eqos->tx_descs); err: debug("%s: returns %d\n", __func__, ret); @@ -1292,7 +1302,8 @@ static int eqos_remove_resources_core(struct udevice *dev) free(eqos->rx_pkt); free(eqos->rx_dma_buf); free(eqos->tx_dma_buf); - eqos_free_descs(eqos->descs); + eqos_free_descs(eqos->rx_descs); + eqos_free_descs(eqos->tx_descs); debug("%s: OK\n", __func__); return 0; diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h index b35e7742634..e3e43c86d11 100644 --- a/drivers/net/dwc_eth_qos.h +++ b/drivers/net/dwc_eth_qos.h @@ -264,7 +264,8 @@ struct eqos_priv { struct phy_device *phy; ofnode phy_of_node; u32 max_speed; - void *descs; + void *tx_descs; + void *rx_descs; int tx_desc_idx, rx_desc_idx; unsigned int desc_size; void *tx_dma_buf; -- 2.35.1

4 7

[PATCH v2] liteeth: LiteX Ethernet device
by Joel Stanley 28 Nov '22

28 Nov '22

LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic network device that is commonly used in LiteX designs. Signed-off-by: Joel Stanley <joel(a)jms.id.au> Reviewed-by: Ramon Fried <rfried.dev(a)gmail.com> --- v2: Fixed some return values Add asm/byteorder.h to fix building v1: https://lore.kernel.org/r/20220810042954.153280-1-joel@jms.id.au --- include/linux/litex.h | 84 +++++++++++++++++ drivers/net/liteeth.c | 214 ++++++++++++++++++++++++++++++++++++++++++ drivers/net/Kconfig | 5 + drivers/net/Makefile | 1 + 4 files changed, 304 insertions(+) create mode 100644 include/linux/litex.h create mode 100644 drivers/net/liteeth.c diff --git a/include/linux/litex.h b/include/linux/litex.h new file mode 100644 index 000000000000..5e91db41fdcb --- /dev/null +++ b/include/linux/litex.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Common LiteX header providing + * helper functions for accessing CSRs. + * + * Copyright (C) 2019-2020 Antmicro <www.antmicro.com> + */ + +#ifndef _LINUX_LITEX_H +#define _LINUX_LITEX_H + +#include <linux/io.h> +#include <asm/byteorder.h> + +static inline void _write_litex_subregister(u32 val, void __iomem *addr) +{ + writel((u32 __force)cpu_to_le32(val), addr); +} + +static inline u32 _read_litex_subregister(void __iomem *addr) +{ + return le32_to_cpu((__le32 __force)readl(addr)); +} + +/* + * LiteX SoC Generator, depending on the configuration, can split a single + * logical CSR (Control&Status Register) into a series of consecutive physical + * registers. + * + * For example, in the configuration with 8-bit CSR Bus, a 32-bit aligned, + * 32-bit wide logical CSR will be laid out as four 32-bit physical + * subregisters, each one containing one byte of meaningful data. + * + * For Linux support, upstream LiteX enforces a 32-bit wide CSR bus, which + * means that only larger-than-32-bit CSRs will be split across multiple + * subregisters (e.g., a 64-bit CSR will be spread across two consecutive + * 32-bit subregisters). + * + * For details see: https://github.com/enjoy-digital/litex/wiki/CSR-Bus + */ + +static inline void litex_write8(void __iomem *reg, u8 val) +{ + _write_litex_subregister(val, reg); +} + +static inline void litex_write16(void __iomem *reg, u16 val) +{ + _write_litex_subregister(val, reg); +} + +static inline void litex_write32(void __iomem *reg, u32 val) +{ + _write_litex_subregister(val, reg); +} + +static inline void litex_write64(void __iomem *reg, u64 val) +{ + _write_litex_subregister(val >> 32, reg); + _write_litex_subregister(val, reg + 4); +} + +static inline u8 litex_read8(void __iomem *reg) +{ + return _read_litex_subregister(reg); +} + +static inline u16 litex_read16(void __iomem *reg) +{ + return _read_litex_subregister(reg); +} + +static inline u32 litex_read32(void __iomem *reg) +{ + return _read_litex_subregister(reg); +} + +static inline u64 litex_read64(void __iomem *reg) +{ + return ((u64)_read_litex_subregister(reg) << 32) | + _read_litex_subregister(reg + 4); +} + +#endif /* _LINUX_LITEX_H */ diff --git a/drivers/net/liteeth.c b/drivers/net/liteeth.c new file mode 100644 index 000000000000..84d3852723e2 --- /dev/null +++ b/drivers/net/liteeth.c @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * LiteX Liteeth Ethernet + * + * Copyright 2021 Joel Stanley <joel(a)jms.id.au>, IBM Corp. + */ + +#include <linux/litex.h> + +#include <dm.h> +#include <dm/device_compat.h> +#include <net.h> + +#define LITEETH_WRITER_SLOT 0x00 +#define LITEETH_WRITER_LENGTH 0x04 +#define LITEETH_WRITER_ERRORS 0x08 +#define LITEETH_WRITER_EV_STATUS 0x0C +#define LITEETH_WRITER_EV_PENDING 0x10 +#define LITEETH_WRITER_EV_ENABLE 0x14 +#define LITEETH_READER_START 0x18 +#define LITEETH_READER_READY 0x1C +#define LITEETH_READER_LEVEL 0x20 +#define LITEETH_READER_SLOT 0x24 +#define LITEETH_READER_LENGTH 0x28 +#define LITEETH_READER_EV_STATUS 0x2C +#define LITEETH_READER_EV_PENDING 0x30 +#define LITEETH_READER_EV_ENABLE 0x34 +#define LITEETH_PREAMBLE_CRC 0x38 +#define LITEETH_PREAMBLE_ERRORS 0x3C +#define LITEETH_CRC_ERRORS 0x40 + +struct liteeth { + struct udevice *dev; + + void __iomem *base; + u32 slot_size; + + /* Tx */ + u32 tx_slot; + u32 num_tx_slots; + void __iomem *tx_base; + + /* Rx */ + u32 rx_slot; + u32 num_rx_slots; + void __iomem *rx_base; +}; + +static int liteeth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct liteeth *priv = dev_get_priv(dev); + u8 rx_slot; + int len; + + if (!litex_read8(priv->base + LITEETH_WRITER_EV_PENDING)) { + debug("liteeth: No packet ready\n"); + return -EAGAIN; + } + + rx_slot = litex_read8(priv->base + LITEETH_WRITER_SLOT); + len = litex_read32(priv->base + LITEETH_WRITER_LENGTH); + + debug("%s: slot %d len 0x%x\n", __func__, rx_slot, len); + + *packetp = priv->rx_base + rx_slot * priv->slot_size; + + return len; +} + +static int liteeth_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct liteeth *priv = dev_get_priv(dev); + + litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, 1); + + return 0; +} + +static int liteeth_start(struct udevice *dev) +{ + struct liteeth *priv = dev_get_priv(dev); + + /* Clear pending events */ + litex_write8(priv->base + LITEETH_WRITER_EV_PENDING, 1); + litex_write8(priv->base + LITEETH_READER_EV_PENDING, 1); + + /* Enable events */ + litex_write8(priv->base + LITEETH_WRITER_EV_ENABLE, 1); + litex_write8(priv->base + LITEETH_READER_EV_ENABLE, 1); + + return 0; +} + +static void liteeth_stop(struct udevice *dev) +{ + struct liteeth *priv = dev_get_priv(dev); + + litex_write8(priv->base + LITEETH_WRITER_EV_ENABLE, 0); + litex_write8(priv->base + LITEETH_READER_EV_ENABLE, 0); +} + +static int liteeth_send(struct udevice *dev, void *packet, int len) +{ + struct liteeth *priv = dev_get_priv(dev); + void __iomem *txbuffer; + + if (!litex_read8(priv->base + LITEETH_READER_READY)) { + printf("liteeth: reader not ready\n"); + return -EAGAIN; + } + + /* Reject oversize packets */ + if (unlikely(len > priv->slot_size)) + return -EMSGSIZE; + + txbuffer = priv->tx_base + priv->tx_slot * priv->slot_size; + memcpy_toio(txbuffer, packet, len); + litex_write8(priv->base + LITEETH_READER_SLOT, priv->tx_slot); + litex_write16(priv->base + LITEETH_READER_LENGTH, len); + litex_write8(priv->base + LITEETH_READER_START, 1); + + priv->tx_slot = (priv->tx_slot + 1) % priv->num_tx_slots; + + return 0; +} + +static void liteeth_setup_slots(struct liteeth *priv) +{ + int err; + + err = ofnode_read_u32(dev_ofnode(priv->dev), "litex,rx-slots", &priv->num_rx_slots); + if (err) { + dev_dbg(priv->dev, "unable to get litex,rx-slots, using 2\n"); + priv->num_rx_slots = 2; + } + + err = ofnode_read_u32(dev_ofnode(priv->dev), "litex,tx-slots", &priv->num_tx_slots); + if (err) { + dev_dbg(priv->dev, "unable to get litex,tx-slots, using 2\n"); + priv->num_tx_slots = 2; + } + + err = ofnode_read_u32(dev_ofnode(priv->dev), "litex,slot-size", &priv->slot_size); + if (err) { + dev_dbg(priv->dev, "unable to get litex,slot-size, using 0x800\n"); + priv->slot_size = 0x800; + } +} + +static int liteeth_remove(struct udevice *dev) +{ + liteeth_stop(dev); + + return 0; +} + +static const struct eth_ops liteeth_ops = { + .start = liteeth_start, + .stop = liteeth_stop, + .send = liteeth_send, + .recv = liteeth_recv, + .free_pkt = liteeth_free_pkt, +}; + +static int liteeth_of_to_plat(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct liteeth *priv = dev_get_priv(dev); + void __iomem *buf_base; + + pdata->iobase = dev_read_addr(dev); + + priv->dev = dev; + + priv->base = dev_remap_addr_name(dev, "mac"); + if (!priv->base) { + dev_err(dev, "failed to map registers\n"); + return -EINVAL; + } + + buf_base = dev_remap_addr_name(dev, "buffer"); + if (!buf_base) { + dev_err(dev, "failed to map buffer\n"); + return -EINVAL; + } + + liteeth_setup_slots(priv); + + /* Rx slots */ + priv->rx_base = buf_base; + priv->rx_slot = 0; + + /* Tx slots come after Rx slots */ + priv->tx_base = buf_base + priv->num_rx_slots * priv->slot_size; + priv->tx_slot = 0; + + return 0; +} + +static const struct udevice_id liteeth_ids[] = { + { .compatible = "litex,liteeth" }, + {} +}; + +U_BOOT_DRIVER(liteeth) = { + .name = "liteeth", + .id = UCLASS_ETH, + .of_match = liteeth_ids, + .of_to_plat = liteeth_of_to_plat, + .plat_auto = sizeof(struct eth_pdata), + .remove = liteeth_remove, + .ops = &liteeth_ops, + .priv_auto = sizeof(struct liteeth), +}; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 6bbbadc5eef3..961ae19ff335 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -438,6 +438,11 @@ config KSZ9477 This driver implements a DSA switch driver for the KSZ9477 family of GbE switches using the I2C interface. +config LITEETH + bool "LiteX LiteEth Ethernet MAC" + help + Driver for the LiteEth Ethernet MAC from LiteX. + config MVGBE bool "Marvell Orion5x/Kirkwood network interface support" depends on ARCH_KIRKWOOD || ARCH_ORION5X diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 96b7678e9882..d3fc6b7d3ee4 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o obj-$(CONFIG_HIGMACV300_ETH) += higmacv300.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_KSZ9477) += ksz9477.o +obj-$(CONFIG_LITEETH) += liteeth.o obj-$(CONFIG_MACB) += macb.o obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o obj-$(CONFIG_MDIO_IPQ4019) += mdio-ipq4019.o -- 2.35.1

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[PULL] u-boot-usb/master
by Marek Vasut 28 Nov '22

28 Nov '22

The following changes since commit 27c415ae8b743710e412ef408b52894af68141c6: Merge branch '2022-11-23-assorted-fixes' (2022-11-24 16:31:02 -0500) are available in the Git repository at: git://source.denx.de/u-boot-usb.git master for you to fetch changes up to db5bace4f6cb37251a5863efe4c0c1547d1334bd: usb: dwc3: Drop support for "snps, ref-clock-period-ns" DT property (2022-11-27 15:34:56 +0100) ---------------------------------------------------------------- Balaji Prakash J (1): usb: dwc3: reference clock period configuration Marek Vasut (3): usb: Expand buffer size in usb_find_and_bind_driver() usb: dwc3: Cache ref_clk pointer in struct dwc3 usb: dwc3: Drop support for "snps, ref-clock-period-ns" DT property Sean Anderson (2): usb: dwc3: Calculate REFCLKPER based on reference clock usb: dwc3: Program GFLADJ drivers/usb/dwc3/core.c | 75 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 12 ++++++++++++ drivers/usb/dwc3/dwc3-generic.c | 9 +++++++++ drivers/usb/host/usb-uclass.c | 2 +- 4 files changed, 97 insertions(+), 1 deletion(-)

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[RESEND PATCH v2 0/3] net: fm: Add support for loading firmware from filesystem
by Sean Anderson 28 Nov '22

28 Nov '22

This adds support for loading Fman firmware from a filesystem using the firmware loader subsystem. It was originally part of [1], but has been split off because it is conceptually separate. [1] https://lore.kernel.org/u-boot/20220324182306.2037094-1-sean.anderson@seco.… Changes in v2: - Split series into two Sean Anderson (3): misc: fs_loader: Add function to get the chosen loader net: fm: Add firmware name parameter net: fm: Support loading firmware from a filesystem arch/arm/mach-k3/common.c | 2 +- arch/arm/mach-omap2/boot-common.c | 2 +- drivers/fpga/socfpga_arria10.c | 24 ++----------------- drivers/misc/fs_loader.c | 27 +++++++++++++++++++++ drivers/net/fm/fm.c | 40 +++++++++++++++++++++++++++---- drivers/net/fm/fm.h | 2 +- drivers/net/fm/init.c | 4 ++-- drivers/qe/Kconfig | 4 ++++ include/fs_loader.h | 12 ++++++++++ 9 files changed, 86 insertions(+), 31 deletions(-) -- 2.35.1.1320.gc452695387.dirty

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