October 2022 - U-Boot

[PATCH] i2c: i2c-gpio: add newline
by Sergei Antonov 14 Nov '22

14 Nov '22

Add newline at the end of the printed string. Signed-off-by: Sergei Antonov <saproj(a)gmail.com> --- drivers/i2c/i2c-gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/i2c-gpio.c b/drivers/i2c/i2c-gpio.c index 1aedad5c8ede..4ed9e9e7cddd 100644 --- a/drivers/i2c/i2c-gpio.c +++ b/drivers/i2c/i2c-gpio.c @@ -362,7 +362,7 @@ static int i2c_gpio_of_to_plat(struct udevice *dev) return 0; error: - pr_err("Can't get %s gpios! Error: %d", dev->name, ret); + pr_err("Can't get %s gpios! Error: %d\n", dev->name, ret); return ret; } -- 2.34.1

3 3

[PATCH 1/2] mach-snapdragon/mach-ipq40xx: fix, merge and refactoring
by Andrey Volkov 12 Nov '22

12 Nov '22

SoC: qcom: Add missing Qualcomm's SOCs definitions to the arch KConfig From: Andrey VOLKOV <andrey(a)volkov.fr> Add APQ8016/APQ8096/QCS40X decls to the KConfig, convert SDM845 declaration to the hidden one (selected by target), and update mach-snapdragon/Makefile accordingly. Also move 'CONFIG_ARM64' choice to the new declarations, since 'Snapdragon' contains Cortex A7A members too. Signed-off-by: Andrey VOLKOV <andrey(a)volkov.fr> --- arch/arm/Kconfig | 1 - arch/arm/mach-snapdragon/Kconfig | 23 +++++++++++++++++-- arch/arm/mach-snapdragon/Makefile | 31 ++++++++++++++----------- arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 2 +- drivers/reset/reset-qcom.c | 2 +- 5 files changed, 40 insertions(+), 19 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2e83394052..a25b7f6d99 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1098,7 +1098,6 @@ config ARCH_RMOBILE config ARCH_SNAPDRAGON bool "Qualcomm Snapdragon SoCs" - select ARM64 select DM select DM_GPIO select DM_SERIAL diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index 0927333306..83dd2c07a1 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -9,10 +9,27 @@ config SYS_MALLOC_F_LEN config SPL_SYS_MALLOC_F_LEN default 0x2000 +config APQ8016 + bool + select ARM64 + default n + +config APQ8096 + bool + select ARM64 + default n + config SDM845 - bool "Qualcomm Snapdragon 845 SoC" + bool + select ARM64 + select LINUX_KERNEL_IMAGE_HEADER default n + +config QCS40X + bool + select ARM64 select LINUX_KERNEL_IMAGE_HEADER + default n config LNX_KRNL_IMG_TEXT_OFFSET_BASE default 0x80000000 @@ -23,6 +40,7 @@ choice config TARGET_DRAGONBOARD410C bool "96Boards Dragonboard 410C" select BOARD_LATE_INIT + select APQ8016 select ENABLE_ARM_SOC_BOOT0_HOOK help Support for 96Boards Dragonboard 410C. This board complies with @@ -37,6 +55,7 @@ config TARGET_DRAGONBOARD410C config TARGET_DRAGONBOARD820C bool "96Boards Dragonboard 820C" + select APQ8096 help Support for 96Boards Dragonboard 820C. This board complies with 96Board Open Platform Specifications. Features: @@ -71,7 +90,7 @@ config TARGET_STARQLTECHN config TARGET_QCS404EVB bool "Qualcomm Technologies, Inc. QCS404 EVB" - select LINUX_KERNEL_IMAGE_HEADER + select QCS40X help Support for Qualcomm Technologies, Inc. QCS404 evaluation board. Features: diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index cbaaf23f6b..00997196ab 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -2,20 +2,23 @@ # # (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski(a)gmail.com> +obj-y += clock-snapdragon.o +obj-y += pinctrl-snapdragon.o + obj-$(CONFIG_SDM845) += clock-sdm845.o obj-$(CONFIG_SDM845) += sysmap-sdm845.o obj-$(CONFIG_SDM845) += init_sdm845.o -obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o -obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o -obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o -obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o -obj-y += misc.o -obj-y += clock-snapdragon.o -obj-y += dram.o -obj-y += pinctrl-snapdragon.o -obj-y += pinctrl-apq8016.o -obj-y += pinctrl-apq8096.o -obj-y += pinctrl-qcs404.o -obj-y += pinctrl-sdm845.o -obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o -obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o +obj-$(CONFIG_SDM845) += pinctrl-sdm845.o + +obj-$(CONFIG_APQ8096) += clock-apq8096.o +obj-$(CONFIG_APQ8096) += sysmap-apq8096.o +obj-$(CONFIG_APQ8096) += pinctrl-apq8096.o + +obj-$(CONFIG_APQ8016) += clock-apq8016.o +obj-$(CONFIG_APQ8016) += sysmap-apq8016.o +obj-$(CONFIG_APQ8016) += pinctrl-apq8016.o +obj-$(CONFIG_APQ8016) += misc.o dram.o + +obj-$(CONFIG_QCS40X) += clock-qcs404.o +obj-$(CONFIG_QCS40X) += sysmap-qcs404.o +obj-$(CONFIG_QCS40X) += pinctrl-qcs404.o diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c index ab884ab6bf..4ed4ab4d4c 100644 --- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c +++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c @@ -149,7 +149,7 @@ static const struct udevice_id msm_pinctrl_ids[] = { { } }; -U_BOOT_DRIVER(pinctrl_snapdraon) = { +U_BOOT_DRIVER(pinctrl_snapdragon) = { .name = "pinctrl_msm", .id = UCLASS_PINCTRL, .of_match = msm_pinctrl_ids, diff --git a/drivers/reset/reset-qcom.c b/drivers/reset/reset-qcom.c index 94315e76d5..2c61d6a6dc 100644 --- a/drivers/reset/reset-qcom.c +++ b/drivers/reset/reset-qcom.c @@ -102,7 +102,7 @@ static const struct qcom_reset_map gcc_qcom_resets[] = { }; #endif -#ifdef CONFIG_TARGET_QCS404EVB +#ifdef CONFIG_QCS40X #include <dt-bindings/clock/qcom,gcc-qcs404.h> static const struct qcom_reset_map gcc_qcom_resets[] = { [GCC_GENI_IR_BCR] = { 0x0F000 },

4 11

[PATCH v2] spi: spi-mem: ease checks in dtr_supports_op()
by Dhruva Gole 11 Nov '22

11 Nov '22

Remove the extra conditions that cause some cases to fail prematurely like if the data number of bytes is odd. The controller can handle odd number of bytes data read in DTR Mode. Don't fail supports op for this condition. This change can also be justified by taking a look at the equivalent code in the linux kernel (v6.0.3), in drivers/spi/spi-mem.c, where such an even number of data bytes check is absent as well. The presence of this even byte check causes supports op failure even if the controller can indeed work in case of odd bytes data reads in DTR (Dual Transfer Rate) mode in xSPI. There have not been any sort of major bugs in the absence of this particular supports_op check, so it is safe to discard this check from here. Signed-off-by: Dhruva Gole <d-gole(a)ti.com> --- v1 of the patch had a relatively shorter commit body that did not sufficiently describe and justify this patch. link to v1: https://lore.kernel.org/u-boot/20221020083424.86848-1-d-gole@ti.com/ v2 has just updated the commit body while preserving the code changes from earlier v1 patch. This tries to address the changes requested from Jagan Teki. drivers/spi/spi-mem.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 8e8995fc537f..eecc13bec90d 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -181,10 +181,6 @@ bool spi_mem_dtr_supports_op(struct spi_slave *slave, if (op->dummy.nbytes && op->dummy.buswidth == 8 && op->dummy.nbytes % 2) return false; - if (op->data.dir != SPI_MEM_NO_DATA && - op->dummy.buswidth == 8 && op->data.nbytes % 2) - return false; - return spi_mem_check_buswidth(slave, op); } EXPORT_SYMBOL_GPL(spi_mem_dtr_supports_op); -- 2.25.1

3 4

[PATCH] nvmem: u-boot-env: add Broadcom format support
by Rafał Miłecki 11 Nov '22

11 Nov '22

From: Rafał Miłecki <rafal(a)milecki.pl> Broadcom uses U-Boot for a lot of their bcmbca familiy chipsets. They decided to store U-Boot environment data inside U-Boot partition and to use a custom header (with "uEnv" magic and env data length). Add support for Broadcom's specific binding and their custom format. Ref: c34f9f5499278 ("dt-bindings: nvmem: u-boot,env: add Broadcom's variant binding") Signed-off-by: Rafał Miłecki <rafal(a)milecki.pl> --- drivers/nvmem/u-boot-env.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/nvmem/u-boot-env.c b/drivers/nvmem/u-boot-env.c index 8e72d1bbd649..049330660fd7 100644 --- a/drivers/nvmem/u-boot-env.c +++ b/drivers/nvmem/u-boot-env.c @@ -16,6 +16,7 @@ enum u_boot_env_format { U_BOOT_FORMAT_SINGLE, U_BOOT_FORMAT_REDUNDANT, + U_BOOT_FORMAT_BROADCOM, }; struct u_boot_env { @@ -40,6 +41,13 @@ struct u_boot_env_image_redundant { uint8_t data[]; } __packed; +struct u_boot_env_image_broadcom { + __le32 magic; + __le32 len; + __le32 crc32; + uint8_t data[0]; +} __packed; + static int u_boot_env_read(void *context, unsigned int offset, void *val, size_t bytes) { @@ -138,6 +146,11 @@ static int u_boot_env_parse(struct u_boot_env *priv) crc32_data_offset = offsetof(struct u_boot_env_image_redundant, mark); data_offset = offsetof(struct u_boot_env_image_redundant, data); break; + case U_BOOT_FORMAT_BROADCOM: + crc32_offset = offsetof(struct u_boot_env_image_broadcom, crc32); + crc32_data_offset = offsetof(struct u_boot_env_image_broadcom, data); + data_offset = offsetof(struct u_boot_env_image_broadcom, data); + break; } crc32 = le32_to_cpu(*(__le32 *)(buf + crc32_offset)); crc32_data_len = priv->mtd->size - crc32_data_offset; @@ -202,6 +215,7 @@ static const struct of_device_id u_boot_env_of_match_table[] = { { .compatible = "u-boot,env", .data = (void *)U_BOOT_FORMAT_SINGLE, }, { .compatible = "u-boot,env-redundant-bool", .data = (void *)U_BOOT_FORMAT_REDUNDANT, }, { .compatible = "u-boot,env-redundant-count", .data = (void *)U_BOOT_FORMAT_REDUNDANT, }, + { .compatible = "brcm,env", .data = (void *)U_BOOT_FORMAT_BROADCOM, }, {}, }; -- 2.34.1

2 2

[RFC 1/1] tools: Dockerfile for armv7
by Heinrich Schuchardt 11 Nov '22

11 Nov '22

Provide an armv7 docker environment to build and test the sandbox. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt(a)canonical.com> --- I have been discussing with Simon, if we can test sandbox_defconfig build on arm in a docker container. This RFC is just a small step on the path to it. --- tools/docker.arm/Dockerfile | 104 ++++++++++++++++++++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 tools/docker.arm/Dockerfile diff --git a/tools/docker.arm/Dockerfile b/tools/docker.arm/Dockerfile new file mode 100644 index 0000000000..9d754da353 --- /dev/null +++ b/tools/docker.arm/Dockerfile @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: GPL-2.0+ +# This Dockerfile is used to build an image for runing the U-Boot sandbox on +# the armv7 architecture. + +FROM ubuntu:jammy-20221003@sha256:60c321f2700325103a0c185adeadfd5a93dbb3cd67dfbdd5b79a8aafa38325c2 + +ENV DEBIAN_FRONTEND=noninteractive + +# Update and install things from apt now +RUN apt-get update && apt-get install -y \ + automake \ + autopoint \ + bc \ + binutils-dev \ + bison \ + build-essential \ + clang-13 \ + coreutils \ + cpio \ + cppcheck \ + curl \ + device-tree-compiler \ + dosfstools \ + e2fsprogs \ + efitools \ + erofs-utils \ + expect \ + fakeroot \ + flex \ + gawk \ + gdisk \ + git \ + gnu-efi \ + gnutls-dev \ + graphviz \ + grub-efi-arm-bin \ + help2man \ + iasl \ + imagemagick \ + iputils-ping \ + libconfuse-dev \ + libgit2-dev \ + libjson-glib-dev \ + libguestfs-tools \ + libgnutls28-dev \ + libgnutls30 \ + liblz4-tool \ + libpixman-1-dev \ + libpython3-dev \ + libsdl1.2-dev \ + libsdl2-dev \ + libseccomp-dev \ + libssl-dev \ + libtool \ + libudev-dev \ + libusb-1.0-0-dev \ + linux-image-generic \ + lzma-alone \ + lzop \ + mount \ + mtd-utils \ + mtools \ + net-tools \ + ninja-build \ + openssl \ + picocom \ + parted \ + pkg-config \ + python-is-python3 \ + python2.7 \ + python3 \ + python3-dev \ + python3-pip \ + python3-sphinx \ + python3-virtualenv \ + rpm2cpio \ + sbsigntool \ + sloccount \ + socat \ + softhsm2 \ + sparse \ + srecord \ + sudo \ + swig \ + util-linux \ + uuid-dev \ + virtualenv \ + xxd \ + zip \ + && rm -rf /var/lib/apt/lists/* + +# Make kernels readable for libguestfs tools to work correctly +RUN chmod +r /boot/vmlinu* + +# Create our user/group +RUN echo uboot ALL=NOPASSWD: ALL > /etc/sudoers.d/uboot +RUN useradd -m -U uboot +USER uboot:uboot + +# Create the buildman config file +RUN /bin/echo -e "[toolchain]\nroot = /usr" > ~/.buildman +RUN /bin/echo -e "\n[toolchain-prefix]" >> ~/.buildman +RUN /bin/echo -e "\n[toolchain-alias]" >> ~/.buildman +RUN /bin/echo -e "\nsandbox = arm" >> ~/.buildman -- 2.37.2

3 6

[PATCH 01/21] Convert CONFIG_SYS_I2C_INIT_BOARD to Kconfig
by Tom Rini 10 Nov '22

10 Nov '22

This converts the following to Kconfig: CONFIG_SYS_I2C_INIT_BOARD Signed-off-by: Tom Rini <trini(a)konsulko.com> --- README | 11 ----------- board/keymile/Kconfig | 3 +++ board/samsung/common/board.c | 4 ---- board/samsung/goni/goni.c | 10 ---------- drivers/i2c/fsl_i2c.c | 7 ------- drivers/i2c/mv_i2c.c | 24 ------------------------ include/configs/km/pg-wcom-ls102xa.h | 1 - 7 files changed, 3 insertions(+), 57 deletions(-) diff --git a/README b/README index 186f1f9a5ffb..92ad191ae76d 100644 --- a/README +++ b/README @@ -1126,17 +1126,6 @@ The following options need to be configured: You should define these to the GPIO value as given directly to the generic GPIO functions. - CONFIG_SYS_I2C_INIT_BOARD - - When a board is reset during an i2c bus transfer - chips might think that the current transfer is still - in progress. On some boards it is possible to access - the i2c SCLK line directly, either by using the - processor pin as a GPIO or by having a second pin - connected to the bus. If this option is defined a - custom i2c_init_board() routine in boards/xxx/board.c - is run early in the boot sequence. - CONFIG_I2C_MULTI_BUS This option allows the use of multiple I2C buses, each of which diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index 9f784430b1d5..b8f0578a286f 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -11,6 +11,9 @@ if VENDOR_KM menu "KM Board Setup" +config SYS_I2C_INIT_BOARD + def_bool y if ARM + config HUSH_INIT_VAR def_bool y diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index ff178b7fe677..e476400ecdc8 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -177,10 +177,6 @@ int board_early_init_f(void) return err; } -#ifdef CONFIG_SYS_I2C_INIT_BOARD - board_i2c_init(gd->fdt_blob); -#endif - return exynos_early_init_f(); } #endif diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index ba25ba27b863..535f8e1e0129 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -33,16 +33,6 @@ int board_init(void) return 0; } -#ifdef CONFIG_SYS_I2C_INIT_BOARD -void i2c_init_board(void) -{ - gpio_request(S5PC110_GPIO_J43, "i2c_clk"); - gpio_request(S5PC110_GPIO_J40, "i2c_data"); - gpio_direction_output(S5PC110_GPIO_J43, 1); - gpio_direction_output(S5PC110_GPIO_J40, 1); -} -#endif - int dram_init(void) { gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE + diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 9a3c8241bc64..edbcd83b6469 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -271,13 +271,6 @@ static void __i2c_init(const struct fsl_i2c_base *base, int speed, int const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT); unsigned long long timeval; -#ifdef CONFIG_SYS_I2C_INIT_BOARD - /* Call board specific i2c bus reset routine before accessing the - * environment, which might be in a chip on that bus. For details - * about this problem see doc/I2C_Edge_Conditions. - */ - i2c_init_board(); -#endif writeb(0, &base->cr); /* stop I2C controller */ udelay(5); /* let it shutdown in peace */ set_i2c_bus_speed(base, i2c_clk, speed); diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c index 0eff3531618c..8ee17f0a4501 100644 --- a/drivers/i2c/mv_i2c.c +++ b/drivers/i2c/mv_i2c.c @@ -374,27 +374,6 @@ static int __i2c_write(struct mv_i2c *base, uchar chip, u8 *addr, int alen, static struct mv_i2c *base_glob; -static void i2c_board_init(struct mv_i2c *base) -{ -#ifdef CONFIG_SYS_I2C_INIT_BOARD - u32 icr; - /* - * call board specific i2c bus reset routine before accessing the - * environment, which might be in a chip on that bus. For details - * about this problem see doc/I2C_Edge_Conditions. - * - * disable I2C controller first, otherwhise it thinks we want to - * talk to the slave port... - */ - icr = readl(&base->icr); - writel(readl(&base->icr) & ~(ICR_SCLE | ICR_IUE), &base->icr); - - i2c_init_board(); - - writel(icr, &base->icr); -#endif -} - #ifdef CONFIG_I2C_MULTI_BUS static unsigned long i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG; static unsigned int bus_initialized[CONFIG_MV_I2C_NUM]; @@ -411,7 +390,6 @@ int i2c_set_bus_num(unsigned int bus) current_bus = bus; if (!bus_initialized[current_bus]) { - i2c_board_init(base_glob); bus_initialized[current_bus] = 1; } @@ -441,8 +419,6 @@ void i2c_init(int speed, int slaveaddr) else val = ICR_SM; clrsetbits_le32(&base_glob->icr, ICR_MODE_MASK, val); - - i2c_board_init(base_glob); } static int __i2c_probe_chip(struct mv_i2c *base, uchar chip) diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 43471e08d604..9565cea083e0 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -155,7 +155,6 @@ /* * I2C */ -#define CONFIG_SYS_I2C_INIT_BOARD #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_I2C_MAX_HOPS 1 -- 2.25.1

3 46

[PATCH] dm: core: Do not stop uclass iteration on error.
by Michal Suchanek 10 Nov '22

10 Nov '22

When probing a device fails NULL pointer is returned, and other devices cannot be iterated. Skip to next device on error instead. Fixes: 6494d708bf ("dm: Add base driver model support") Signed-off-by: Michal Suchanek <msuchanek(a)suse.de> --- drivers/core/uclass.c | 30 +++++++++++++++++++++--------- 1 file changed, 21 insertions(+), 9 deletions(-) diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index 08d9ed82de..ccf7d59141 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -574,16 +574,31 @@ int uclass_get_device_by_phandle(enum uclass_id id, struct udevice *parent, } #endif +/* Starting from the given device return first device in the uclass that probes successfully */ +static int __uclass_next_device(struct udevice *dev, int ret, struct udevice **devp) +{ + if (!dev) { + *devp = dev; + return 0; + } + while ((ret = uclass_get_device_tail(dev, ret, devp))) { + ret = uclass_find_next_device(&dev); + if (!dev) { + *devp = dev; + return 0; + } + } + + return ret; +} + int uclass_first_device(enum uclass_id id, struct udevice **devp) { - struct udevice *dev; + struct udevice *dev = NULL; int ret; - *devp = NULL; ret = uclass_find_first_device(id, &dev); - if (!dev) - return 0; - return uclass_get_device_tail(dev, ret, devp); + return __uclass_next_device(dev, ret, devp); } int uclass_first_device_err(enum uclass_id id, struct udevice **devp) @@ -604,11 +619,8 @@ int uclass_next_device(struct udevice **devp) struct udevice *dev = *devp; int ret; - *devp = NULL; ret = uclass_find_next_device(&dev); - if (!dev) - return 0; - return uclass_get_device_tail(dev, ret, devp); + return __uclass_next_device(dev, ret, devp); } int uclass_next_device_err(struct udevice **devp) -- 2.37.1

3 132

[PATCH] doc: board: j721e_evm: Add DM firmware steps
by Andrew Davis 09 Nov '22

09 Nov '22

J721e needs DM firmware when using updated SYSFW. Add steps to fetch, build, and deploy the same. Signed-off-by: Andrew Davis <afd(a)ti.com> --- doc/board/ti/j721e_evm.rst | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/doc/board/ti/j721e_evm.rst b/doc/board/ti/j721e_evm.rst index 44dc316afd..a7d7229722 100644 --- a/doc/board/ti/j721e_evm.rst +++ b/doc/board/ti/j721e_evm.rst @@ -142,7 +142,11 @@ Sources: Tree: https://github.com/OP-TEE/optee_os.git Branch: master -4. U-Boot: +4. DM: + Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git + Branch: ti-linux-firmware + +5. U-Boot: Tree: https://source.denx.de/u-boot/u-boot Branch: master @@ -152,7 +156,7 @@ Build procedure: .. code-block:: text - $ make CROSS_COMPILE=arm-linux-gnueabihf- + $ make CROSS_COMPILE=arm-linux-gnueabihf- SOC=j721e 2. ATF: @@ -172,15 +176,15 @@ Build procedure: .. code-block:: text - $ make CROSS_COMPILE=arm-linux-gnueabihf- j721e_evm_r5_defconfig O=/tmp/r5 - $ make CROSS_COMPILE=arm-linux-gnueabihf- O=/tmp/r5 + $ make CROSS_COMPILE=arm-linux-gnueabihf- j721e_evm_r5_defconfig O=build/r5 + $ make CROSS_COMPILE=arm-linux-gnueabihf- O=build/r5 * 4.2 A72: .. code-block:: text - $ make CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=/tmp/a72 - $ make CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin DM=<path to DM firmware image> O=/tmp/a72 + $ make CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=build/a72 + $ make CROSS_COMPILE=aarch64-linux-gnu- ATF=<ATF dir>/build/k3/generic/release/bl31.bin TEE=<OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin DM=DM=<DM firmware>/ti-dm/j721e/ipc_echo_testb_mcu1_0_release_strip.xer5f O=build/a72 Target Images -------------- -- 2.37.3

2 4

[PATCH v2 1/2] spl: enable regulator-boot-on and disable regulator-force-boot-off
by Quentin Schulz 09 Nov '22

09 Nov '22

From: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> This makes sure regulators that need to be turned on or off at boot are turned on or off in the SPL. This may be required for the SPL to do some operations, such as finding possible loading media for U-Boot proper. Cc: Quentin Schulz <foss+uboot(a)0leil.net> Tested-by: Xavier Drudis Ferran <xdrudis(a)tinet.cat> Signed-off-by: Quentin Schulz <quentin.schulz(a)theobroma-systems.com> --- v2: - added Tested-by, - fixed build for boards with SPL_DM_REGULATOR disabled by always included power/regulator.h and defining a dummy implementation for regulators_enable_boot_off, common/spl/spl.c | 10 ++++++++++ include/power/regulator.h | 5 +++++ 2 files changed, 15 insertions(+) diff --git a/common/spl/spl.c b/common/spl/spl.c index 29e0898f03..6ab997279d 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -39,6 +39,7 @@ #include <fdt_support.h> #include <bootcount.h> #include <wdt.h> +#include <power/regulator.h> DECLARE_GLOBAL_DATA_PTR; DECLARE_BINMAN_MAGIC_SYM; @@ -773,6 +774,15 @@ void board_init_r(gd_t *dummy1, ulong dummy2) if (CONFIG_IS_ENABLED(GPIO_HOG)) gpio_hog_probe_all(); + if (CONFIG_IS_ENABLED(DM_REGULATOR)) { + if (regulators_enable_boot_on(false)) + debug("%s: Cannot enable boot on regulator\n", + __func__); + if (regulators_enable_boot_off(false)) + debug("%s: Cannot enable boot off regulator\n", + __func__); + } + #if CONFIG_IS_ENABLED(BOARD_INIT) spl_board_init(); #endif diff --git a/include/power/regulator.h b/include/power/regulator.h index ff1bfc2435..4bce61dd9f 100644 --- a/include/power/regulator.h +++ b/include/power/regulator.h @@ -631,6 +631,11 @@ static inline int regulators_enable_boot_on(bool verbose) return -ENOSYS; } +static inline int regulators_enable_boot_off(bool verbose) +{ + return -ENOSYS; +} + static inline int regulator_autoset(struct udevice *dev) { return -ENOSYS; -- 2.37.1

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[PATCH 1/2] spi: fsl_qspi: Add support for i.MX7ULP
by Ye Li 09 Nov '22

09 Nov '22

Add compatible string and driver data for i.MX7ULP. Meanwhile, the address set to SFA1AD/SFA2AD/SFB1AD/SFB2AD should align with 1KB, because the lowest 10 bits are reserved by the registers definition. For i.MX7ULP which has only 128Bytes AHB buffer, must align it when setting the registers and selecting cs. Signed-off-by: Ye Li <ye.li(a)nxp.com> Reviewed-by: Ashish Kumar <Ashish.Kumar(a)nxp.com> Reviewed-by: Kuldeep Singh <kuldeep.singh(a)nxp.com> --- drivers/spi/fsl_qspi.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index e715f98..d9f531a 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -231,6 +231,15 @@ static const struct fsl_qspi_devtype_data imx6ul_data = { .little_endian = true, }; +static const struct fsl_qspi_devtype_data imx7ulp_data = { + .rxfifo = SZ_64, + .txfifo = SZ_64, + .ahb_buf_size = SZ_128, + .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_4X_INT_CLK | + QUADSPI_QUIRK_USE_TDH_SETTING, + .little_endian = true, +}; + static const struct fsl_qspi_devtype_data ls1021a_data = { .rxfifo = SZ_128, .txfifo = SZ_64, @@ -485,7 +494,7 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_slave *slave) static void fsl_qspi_read_ahb(struct fsl_qspi *q, const struct spi_mem_op *op) { memcpy_fromio(op->data.buf.in, - q->ahb_addr + q->selected * q->devtype_data->ahb_buf_size, + q->ahb_addr + q->selected * ALIGN(q->devtype_data->ahb_buf_size, 0x400), op->data.nbytes); } @@ -589,7 +598,7 @@ static int fsl_qspi_exec_op(struct spi_slave *slave, addr_offset = q->memmap_phy; qspi_writel(q, - q->selected * q->devtype_data->ahb_buf_size + addr_offset, + q->selected * ALIGN(q->devtype_data->ahb_buf_size, 0x400) + addr_offset, base + QUADSPI_SFAR); qspi_writel(q, qspi_readl(q, base + QUADSPI_MCR) | @@ -695,13 +704,13 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q) * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD, * SFB2AD accordingly. */ - qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset, + qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) + addr_offset, base + QUADSPI_SFA1AD); - qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset, + qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) * 2 + addr_offset, base + QUADSPI_SFA2AD); - qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset, + qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) * 3 + addr_offset, base + QUADSPI_SFB1AD); - qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset, + qspi_writel(q, ALIGN(q->devtype_data->ahb_buf_size, 0x400) * 4 + addr_offset, base + QUADSPI_SFB2AD); q->selected = -1; @@ -799,6 +808,7 @@ static const struct udevice_id fsl_qspi_ids[] = { { .compatible = "fsl,imx6sx-qspi", .data = (ulong)&imx6sx_data, }, { .compatible = "fsl,imx6ul-qspi", .data = (ulong)&imx6ul_data, }, { .compatible = "fsl,imx7d-qspi", .data = (ulong)&imx7d_data, }, + { .compatible = "fsl,imx7ulp-qspi", .data = (ulong)&imx7ulp_data, }, { .compatible = "fsl,ls1021a-qspi", .data = (ulong)&ls1021a_data, }, { .compatible = "fsl,ls1088a-qspi", .data = (ulong)&ls1088a_data, }, { .compatible = "fsl,ls2080a-qspi", .data = (ulong)&ls2080a_data, }, -- 2.7.4

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