September 2021 - U-Boot

[PATCH 0/7] xyz-modem: Fix cancelling and closing transfers
by Pali Rohár 03 Sep '21

03 Sep '21

This patch series fixes U-Boot crash during cancellation of x/y-modem transfers and contains other various fixes related to finishing transfers. Pali Rohár (7): xyz-modem: Fix crash after cancelling transfer xyz-modem: Fix x-modem "xyzModem_eof error" at the end of file xyz-modem: Put xyzModem_stream_close debug diagnostic message into ZM_DEBUG() xyz-modem: Close stream after processing/sending terminate sequence xyz-modem: Properly abort/terminate transfer on error xyz-modem: Show information about finished transfer xyz-modem: Allow to cancel transfer also by CTRL+C cmd/load.c | 32 ++++++++++++++++++++++++++++++-- common/xyzModem.c | 12 ++++++++---- 2 files changed, 38 insertions(+), 6 deletions(-) -- 2.20.1

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[BUG] USB boot issue on ROCKPro64 with UEFI
by Vincent Stehlé 03 Sep '21

03 Sep '21

Hi U-Boot folks, Hopefully this is the right way to report bugs. If not, please do not hesitate to let me know. I am hitting an issue with U-Boot v2021.07 on the ROCKPro64, when booting Linux with UEFI from USB. The kernel EFI stub will hang: EFI stub: Booting Linux Kernel... EFI stub: Using DTB from configuration table EFI stub: Exiting boot services and installing virtual address map... After tracking it down, it appears efi_exit_boot_services() is ultimately calling OHCI hc_reset(), which hangs at this line: 1804 if (ohci_readl(&ohci->regs->control) & OHCI_CTRL_IR) { This seems to indicate reading the OHCI hardware control register cannot complete, which hints at a clocking issue. Looking in more details at the clocks changes performed on the efi_exit_boot_services() path, a workaround is indeed to prevent the USB2PHY clocks from being disabled (see the patch following this e-mail). I don't know enough about the RK3399 clock tree to fully understand what is going on here, and what would be a proper fix. Hopefully others will be able to continue from there. Best regards, Vincent Stehlé System Architect - Arm Vincent Stehlé (1): clk: rk3399: do not disable the USB2PHY clk drivers/clk/rockchip/clk_rk3399.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.30.2

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[GIT PULL] xilinx patches for v2021.10-rc4
by Michal Simek 03 Sep '21

03 Sep '21

Hi Tom, please pull these 3 fixes to your tree. It is one uefi dox fix. And 2 spi patches are fixing single mode for zynqmp boards. Thanks, Michal The following changes since commit 94509b79b13e69c209199af0757afbde8d2ebd6d: btrfs: Use default subvolume as filesystem root (2021-09-01 10:11:24 -0400) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-microblaze.git tags/xilinx-for-v2021.10-rc4 for you to fetch changes up to 020b353be9e6c12ebf49333a81e02d582578f560: spi: zynqmp_gqspi: Fix dma alignment issue (2021-09-03 09:15:01 +0200) ---------------------------------------------------------------- Xilinx changes for v2021.10-rc4 doc: - Fix uefi documentation spi: - Fix gqspi driver for single configuration ---------------------------------------------------------------- Ashok Reddy Soma (2): spi: zynqmp_gqspi: Switch genfifo start to manual mode spi: zynqmp_gqspi: Fix dma alignment issue Michal Simek (1): doc: Remove information about CAPSULE_FMP_HEADER doc/develop/uefi/uefi.rst | 1 - drivers/spi/zynqmp_gqspi.c | 30 ++++++++++++++---------------- 2 files changed, 14 insertions(+), 17 deletions(-) -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs

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[PATCH v2 0/6] Armv8r64 + BASER_FVP board support
by Peter Hoyes 03 Sep '21

03 Sep '21

From: Peter Hoyes <Peter.Hoyes(a)arm.com> Add support for the Armv8r64 architecture and the BASER_FVP, which uses the Armv8r64 architecture. The Armv8r64 architecture has the following features: * No non-secure exception levels * Highest exception level is always S-EL2 * There is only a PMSA at S-EL2, which requires new MPU initialization logic * The VMSA at S-EL1 may not be enabled by default * We boot Linux at S-EL1, so a mechanism is required to boot other systems (e.g. Xen) at S-EL2 The BASER_FVP board config is implemented on top of the BASE_FVP and Juno "VExpress" board configs. The Armv8-R64 architecture reference manual supplement can be found at https://developer.arm.com/documentation/ddi0600/latest/ Peter Hoyes (6): armv8: Disable pointer authentication traps for EL1 armv8: Ensure EL1&0 VMSA is enabled armv8: Add ARMv8 MPU configuration logic vexpress64: Add BASER_FVP vexpress board variant arm: Use armv8_switch_to_el1 env to switch to EL1 doc: Add documentation for the Arm vexpress board configs arch/arm/Kconfig | 7 ++ arch/arm/cpu/armv8/cache_v8.c | 96 ++++++++++++++++++- arch/arm/cpu/armv8/fsl-layerscape/spintable.S | 2 +- arch/arm/cpu/armv8/transition.S | 2 +- arch/arm/include/asm/armv8/mpu.h | 61 ++++++++++++ arch/arm/include/asm/macro.h | 28 +++++- arch/arm/include/asm/system.h | 39 ++++++++ arch/arm/lib/bootm.c | 40 +++++--- board/armltd/vexpress64/Kconfig | 5 +- board/armltd/vexpress64/vexpress64.c | 22 +++++ configs/vexpress_aemv8r_defconfig | 18 ++++ doc/README.semihosting | 2 +- doc/arch/arm64.rst | 3 +- doc/board/armltd/index.rst | 9 ++ doc/board/armltd/vexpress64.rst | 57 +++++++++++ doc/board/index.rst | 1 + .../{vexpress_aemv8a.h => vexpress_aemv8.h} | 63 ++++++++---- 17 files changed, 408 insertions(+), 47 deletions(-) create mode 100644 arch/arm/include/asm/armv8/mpu.h create mode 100644 configs/vexpress_aemv8r_defconfig create mode 100644 doc/board/armltd/index.rst create mode 100644 doc/board/armltd/vexpress64.rst rename include/configs/{vexpress_aemv8a.h => vexpress_aemv8.h} (83%) -- 2.25.1

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[PATCH v5] arm: add initial support for the Phytium Pomelo Board
by nicholas_zheng＠outlook.com 03 Sep '21

03 Sep '21

From: weichangzheng <nicholas_zheng(a)outlook.com> This adds platform code and the device tree for the Phytium Pomelo Board. The initial support comprises the UART and the PCIE. Signed-off-by: weichangzheng <nicholas_zheng(a)outlook.com> Changes since v1: updated to DT Changes since v2: Modify some explicit types and macro Changes since v3: Modify some SDRAM related macro definitions and distro_bootcmd Changes since v4: Modify distro_bootcmd --- arch/arm/Kconfig | 20 ++++ arch/arm/dts/Makefile | 1 + arch/arm/dts/phytium-pomelo.dts | 113 ++++++++++++++++++++++ board/phytium/pomelo/Kconfig | 12 +++ board/phytium/pomelo/MAINTAINERS | 8 ++ board/phytium/pomelo/Makefile | 14 +++ board/phytium/pomelo/cpu.h | 73 ++++++++++++++ board/phytium/pomelo/ddr.c | 161 +++++++++++++++++++++++++++++++ board/phytium/pomelo/pcie.c | 60 ++++++++++++ board/phytium/pomelo/pll.c | 73 ++++++++++++++ board/phytium/pomelo/pomelo.c | 118 ++++++++++++++++++++++ board/phytium/pomelo/sec.c | 37 +++++++ configs/pomelo_defconfig | 18 ++++ include/configs/pomelo.h | 44 +++++++++ 14 files changed, 752 insertions(+) create mode 100644 arch/arm/dts/phytium-pomelo.dts create mode 100644 board/phytium/pomelo/Kconfig create mode 100644 board/phytium/pomelo/MAINTAINERS create mode 100644 board/phytium/pomelo/Makefile create mode 100644 board/phytium/pomelo/cpu.h create mode 100644 board/phytium/pomelo/ddr.c create mode 100644 board/phytium/pomelo/pcie.c create mode 100644 board/phytium/pomelo/pll.c create mode 100644 board/phytium/pomelo/pomelo.c create mode 100644 board/phytium/pomelo/sec.c create mode 100644 configs/pomelo_defconfig create mode 100644 include/configs/pomelo.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0448787b8b..029af85fcb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1818,6 +1818,25 @@ config TARGET_DURIAN Support for durian platform. It has 2GB Sdram, uart and pcie. +config TARGET_POMELO + bool "Support Phytium Pomelo Platform" + select ARM64 + select DM + select AHCI + select SCSI_AHCI + select AHCI_PCI + select BLK + select PCI + select DM_PCI + select SCSI + select DM_SCSI + select DM_SERIAL + select DM_ETH if NET + imply CMD_PCI + help + Support for pomelo platform. + It has 8GB Sdram, uart and pcie. + config TARGET_PRESIDIO_ASIC bool "Support Cortina Presidio ASIC Platform" select ARM64 @@ -2038,6 +2057,7 @@ source "board/toradex/colibri_pxa270/Kconfig" source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" source "board/phytium/durian/Kconfig" +source "board/phytium/pomelo/Kconfig" source "board/xen/xenguest_arm64/Kconfig" source "board/keymile/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9fb38682e6..45d0340bd3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1107,6 +1107,7 @@ dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb +dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb diff --git a/arch/arm/dts/phytium-pomelo.dts b/arch/arm/dts/phytium-pomelo.dts new file mode 100644 index 0000000000..3869475902 --- /dev/null +++ b/arch/arm/dts/phytium-pomelo.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Phytium Pomelo board + * Copyright (C) 2021, Phytium Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ +/dts-v1/; + +/ { + model = "Phytium Pomelo"; + compatible = "phytium,pomelo"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu2: cpu@4 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu3: cpu@5 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu4: cpu@8 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x200>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu5: cpu@9 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x201>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu6: cpu@12 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x300>; + enable-method = "psci"; + numa-node-id = <0>; + }; + + cpu7: cpu@13 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x301>; + enable-method = "psci"; + numa-node-id = <0>; + }; + }; + + pcie-controller@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x40000000 0x0 0x10000000>; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00F00000>, + <0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>; + }; + + sysclk_48mhz: clk48mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <48000000>; + clock-output-names = "sysclk_48mhz"; + }; + + uart0: uart@28001000 { + compatible = "arm,pl011"; + reg = <0x0 0x28001000 0x0 0x1000>; + clocks = <&sysclk_48mhz>; + }; +}; diff --git a/board/phytium/pomelo/Kconfig b/board/phytium/pomelo/Kconfig new file mode 100644 index 0000000000..281aa8feff --- /dev/null +++ b/board/phytium/pomelo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_POMELO + +config SYS_BOARD + default "pomelo" + +config SYS_VENDOR + default "phytium" + +config SYS_CONFIG_NAME + default "pomelo" + +endif diff --git a/board/phytium/pomelo/MAINTAINERS b/board/phytium/pomelo/MAINTAINERS new file mode 100644 index 0000000000..d76a4a026e --- /dev/null +++ b/board/phytium/pomelo/MAINTAINERS @@ -0,0 +1,8 @@ +POMELO BOARD +M: lixinde <lixinde(a)phytium.com.cn> +M: weichangzheng <weichangzheng(a)phytium.com.cn> +S: Maintained +F: board/phytium/pomelo/* +F: include/configs/pomelo.h +F: configs/pomelo_defconfig +F: arch/arm/dts/phytium-pomelo.dts diff --git a/board/phytium/pomelo/Makefile b/board/phytium/pomelo/Makefile new file mode 100644 index 0000000000..b9cb3609bd --- /dev/null +++ b/board/phytium/pomelo/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 +# lixinde <lixinde(a)phytium.com.cn> +# weichangzheng <weichangzheng(a)phytium.com.cn> +# + +obj-y += pomelo.o +obj-y += pll.o +obj-y += pcie.o +obj-y += ddr.o +obj-y += sec.o + + diff --git a/board/phytium/pomelo/cpu.h b/board/phytium/pomelo/cpu.h new file mode 100644 index 0000000000..005ea5982b --- /dev/null +++ b/board/phytium/pomelo/cpu.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 + * Phytium Technology Ltd <www.phytium.com> + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef _FT_POMELO_H +#define _FT_POMELO_H + +/* SMCCC ID */ +#define CPU_SVC_VERSION 0xC2000F00 +#define CPU_GET_RST_SOURCE 0xC2000F01 +#define CPU_INIT_PLL 0xC2000F02 +#define CPU_INIT_PCIE 0xC2000F03 +#define CPU_INIT_MEM 0xC2000F04 +#define CPU_INIT_SEC_SVC 0xC2000F05 + +/*CPU RESET*/ +#define CPU_RESET_POWER_ON 0x1 +#define CPU_RESET_PLL 0x4 +#define CPU_RESET_WATCH_DOG 0x8 + +/* PLL */ +#define PARAMETER_PLL_MAGIC 0x54460010 + +/* PCIE */ +#define PARAMETER_PCIE_MAGIC 0x54460011 +#define CFG_INDEPENDENT_TREE 0x0 +#define PCI_PEU0 0x1 +#define PCI_PEU1 0x1 +#define PEU1_OFFSET 16 +#define PEU_C_OFFSET_MODE 16 +#define PEU_C_OFFSET_SPEED 0 +#define RC_MODE 0x1 +#define X8X8 0x1 +#define GEN3 3 + +/* DDR */ +#define PARAMETER_MCU_MAGIC 0x54460014 +#define PARAM_MCU_VERSION 0x1 +#define PARAM_MCU_SIZE 0x100 +#define PARAM_CH_ENABLE 0x3 +#define PARAM_ECC_ENABLE 0x3 +#define PARAM_FORCE_SPD_DISABLE 0x0 +#define PARAM_MCU_MISC_ENABLE 0x0 + +#define UDIMM_TYPE 0x2 +#define DIMM_X8 0x1 +#define NO_MIRROR 0x0 +#define NO_ECC_TYPE 0 +#define DDR4_TYPE 0xC + +/* SEC */ +#define PARAMETER_COMMON_MAGIC 0x54460013 + +/* FLUSH L3 CASHE */ +#define HNF_COUNT 0x8 +#define HNF_PSTATE_REQ (HNF_BASE + 0x10) +#define HNF_PSTATE_STAT (HNF_BASE + 0x18) +#define HNF_PSTATE_OFF 0x0 +#define HNF_PSTATE_SFONLY 0x1 +#define HNF_PSTATE_HALF 0x2 +#define HNF_PSTATE_FULL 0x3 +#define HNF_STRIDE 0x10000 +#define HNF_BASE (unsigned long)(0x3A200000) +void ddr_init(void); +void sec_init(void); +void check_reset(void); +void pcie_init(void); + +#endif /* _FT_POMELO_H */ diff --git a/board/phytium/pomelo/ddr.c b/board/phytium/pomelo/ddr.c new file mode 100644 index 0000000000..c6dbed9639 --- /dev/null +++ b/board/phytium/pomelo/ddr.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct ddr_spd { + /******************* read from spd *****************/ + u8 dimm_type; /* 1: RDIMM;2: UDIMM;3: SODIMM;4: LRDIMM */ + u8 data_width; /* 0: x4; 1: x8; 2: x16 */ + u8 mirror_type;/* 0: stardard; 1: mirror */ + u8 ecc_type; /* 0: no-ecc; 1:ecc */ + u8 dram_type; /* 0xB: DDR3; 0xC: DDR4 */ + u8 rank_num; + u8 row_num; + u8 col_num; + + u8 bg_num; /*only DDR4*/ + u8 bank_num; + u16 module_manufacturer_id; + u16 taamin; + u16 trcdmin; + + u16 trpmin; + u16 trasmin; + u16 trcmin; + u16 tfawmin; + + u16 trrd_smin; /*only DDR4*/ + u16 trrd_lmin; /*only DDR4*/ + u16 tccd_lmin; /*only DDR4*/ + u16 twrmin; + + u16 twtr_smin; /*only DDR4*/ + u16 twtr_lmin; /*only DDR4*/ + u16 twtrmin; /*only DDR3*/ + u16 trrdmin; /*only DDR3*/ + + /******************* RCD control words *****************/ + u8 f0rc03; /*bit[3:2]:CS bit[1:0]:CA */ + u8 f0rc04; /*bit[3:2]:ODT bit[1:0]:CKE */ + u8 f0rc05; /*bit[3:2]:CLK-A side bit[1:0]:CLK-B side */ + u8 bc00; + u8 bc01; + u8 bc02; + u8 bc03; + u8 bc04; + + u8 bc05; + u8 f5bc5x; + u8 f5bc6x; + /******************* LRDIMM special *****************/ + u8 vrefdq_pr0; + u8 vrefdq_mdram; + u8 rtt_mdram_1866; + u8 rtt_mdram_2400; + u8 rtt_mdram_3200; + + u8 drive_dram; + u8 odt_dram_1866; + u8 odt_dram_2400; + u8 odt_dram_3200; + u8 park_dram_1866; + u8 park_dram_2400; + u8 park_dram_3200; + u8 rcd_num; +} __attribute((aligned(4))); + +struct mcu_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + + u8 ch_enable; + u8 misc1_enable; + u8 misc2_enable; + u8 force_spd_enable; + u8 misc3_enable; + u8 train_debug; + u8 train_recover; + u8 rev2[9]; + + struct ddr_spd ddr_spd_info[2]; +} __attribute((aligned(4))); + +static void get_mcu_up_info_default(struct mcu_config *pm) +{ + pm->magic = PARAMETER_MCU_MAGIC; + pm->version = PARAM_MCU_VERSION; + pm->size = PARAM_MCU_SIZE; + pm->ch_enable = PARAM_CH_ENABLE; + pm->misc1_enable = PARAM_ECC_ENABLE; + pm->force_spd_enable = PARAM_FORCE_SPD_DISABLE; + pm->misc3_enable = PARAM_MCU_MISC_ENABLE; + pm->train_recover = 0x0; +} + +static u8 init_dimm_param(u8 ch, struct mcu_config *pm) +{ + debug("manual config dimm info...\n"); + pm->ddr_spd_info[ch].dimm_type = UDIMM_TYPE; + pm->ddr_spd_info[ch].data_width = DIMM_X8; + pm->ddr_spd_info[ch].mirror_type = NO_MIRROR; + pm->ddr_spd_info[ch].ecc_type = NO_ECC_TYPE; + pm->ddr_spd_info[ch].dram_type = DDR4_TYPE; + pm->ddr_spd_info[ch].rank_num = 1; + pm->ddr_spd_info[ch].row_num = 16; + pm->ddr_spd_info[ch].col_num = 10; + pm->ddr_spd_info[ch].bg_num = 4; + pm->ddr_spd_info[ch].bank_num = 4; + pm->ddr_spd_info[ch].taamin = 13750; + pm->ddr_spd_info[ch].trcdmin = 13750; + + pm->ddr_spd_info[ch].trpmin = 13750; + pm->ddr_spd_info[ch].trasmin = 32000; + pm->ddr_spd_info[ch].trcmin = 45750; + pm->ddr_spd_info[ch].tfawmin = 21000; + + pm->ddr_spd_info[ch].trrd_smin = 3000; + pm->ddr_spd_info[ch].trrd_lmin = 4900; + pm->ddr_spd_info[ch].tccd_lmin = 5000; + pm->ddr_spd_info[ch].twrmin = 15000; + + pm->ddr_spd_info[ch].twtr_smin = 2500; + pm->ddr_spd_info[ch].twtr_lmin = 7500; + + return 0; +} + +void get_default_mcu_info(u8 *data) +{ + get_mcu_up_info_default((struct mcu_config *)data); +} + +void fix_mcu_info(u8 *data) +{ + struct mcu_config *mcu_info = (struct mcu_config *)data; + + for (int ch = 0; ch < 2; ch++) + init_dimm_param(ch, mcu_info); +} + +void ddr_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + get_default_mcu_info(buffer); + fix_mcu_info(buffer); + + arm_smccc_smc(CPU_INIT_MEM, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("DRAM init failed :0x%lx\n", res.a0); +} diff --git a/board/phytium/pomelo/pcie.c b/board/phytium/pomelo/pcie.c new file mode 100644 index 0000000000..698d82fd8d --- /dev/null +++ b/board/phytium/pomelo/pcie.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct pcu_ctr { + u32 base_config[3]; + u32 equalization[3]; + u8 rev[80]; +} __attribute((aligned(4))); + +struct pcu_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u32 independent_tree; + u32 base_cfg; + u8 rev2[16]; + struct pcu_ctr ctr_cfg[2]; +} __attribute((aligned(4))); + +struct pcu_config const peu_base_info = { + .magic = PARAMETER_PCIE_MAGIC, + .version = 0x2, + .size = 0x100, + .independent_tree = CFG_INDEPENDENT_TREE, + .base_cfg = ((PCI_PEU1 | (X8X8 << 1)) << PEU1_OFFSET | (PCI_PEU0 | (X8X8 << 1))), + .ctr_cfg[0].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].equalization[0] = 0x7, + .ctr_cfg[0].equalization[1] = 0x7, + .ctr_cfg[0].equalization[2] = 0x7, + .ctr_cfg[1].equalization[0] = 0x7, + .ctr_cfg[1].equalization[1] = 0x7, + .ctr_cfg[1].equalization[2] = 0x7, +}; + +void pcie_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &peu_base_info, sizeof(peu_base_info)); + arm_smccc_smc(CPU_INIT_PCIE, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("PCIE init failed :0x%lx\n", res.a0); +} diff --git a/board/phytium/pomelo/pll.c b/board/phytium/pomelo/pll.c new file mode 100644 index 0000000000..a66ffddf09 --- /dev/null +++ b/board/phytium/pomelo/pll.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct pll_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u32 core_pll; + u32 res1; + u32 lmu_pll; + u32 res2; + u32 res3; + u32 res4; + u32 res5; +} __attribute((aligned(4))); + +struct pll_config const pll_base_info = { + .magic = PARAMETER_PLL_MAGIC, + .version = 0x1, + .size = 0x30, + .core_pll = 2300, /*MHz*/ + .lmu_pll = 667, /*MHz*/ +}; + +u32 get_reset_source(void) +{ + struct arm_smccc_res res; + + arm_smccc_smc(CPU_GET_RST_SOURCE, 0, 0, 0, 0, 0, 0, 0, &res); + return res.a0; +} + +void pll_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &pll_base_info, sizeof(pll_base_info)); + arm_smccc_smc(CPU_INIT_PLL, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("PLL init failed :0x%lx\n", res.a0); +} + +void check_reset(void) +{ + u32 rst; + + rst = get_reset_source(); + + switch (rst) { + case CPU_RESET_POWER_ON: + pll_init(); + break; + case CPU_RESET_PLL: + break; + case CPU_RESET_WATCH_DOG: + break; + default: + panic("other reset source\n"); + } +} diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c new file mode 100644 index 0000000000..4fbe1e5835 --- /dev/null +++ b/board/phytium/pomelo/pomelo.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <command.h> +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <scsi.h> +#include <init.h> +#include <asm/u-boot.h> +#include "cpu.h" + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + debug("Phytium ddr init\n"); + ddr_init(); + + gd->mem_clk = 0; + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 0x7b000000); + + sec_init(); + debug("PBF relocate done\n"); + + return 0; +} + +int board_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ + struct arm_smccc_res res; + + debug("run in reset cpu\n"); + arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("reset cpu error, %lx\n", res.a0); +} + +int mach_cpu_init(void) +{ + check_reset(); + return 0; +} + +int board_early_init_f(void) +{ + pcie_init(); + return 0; +} + +static struct mm_region pomelo_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | + PTE_BLOCK_UXN + }, + { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x7b000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_NS | + PTE_BLOCK_INNER_SHARE + }, + { + 0, + } +}; + +struct mm_region *mem_map = pomelo_mem_map; + +int __asm_flush_l3_dcache(void) +{ + int i, pstate; + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE); + for (i = 0; i < HNF_COUNT; i++) { + do { + pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE); + } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); + } + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE); + + return 0; +} + +int last_stage_init(void) +{ + int ret; + + /* pci e */ + pci_init(); + /* scsi scan */ + ret = scsi_scan(true); + if (ret) { + printf("scsi scan failed\n"); + return CMD_RET_FAILURE; + } + return ret; +} diff --git a/board/phytium/pomelo/sec.c b/board/phytium/pomelo/sec.c new file mode 100644 index 0000000000..aeb3983f01 --- /dev/null +++ b/board/phytium/pomelo/sec.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct common_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u64 core_bit_map; +} __attribute((aligned(4))); + +struct common_config const common_base_info = { + .magic = PARAMETER_COMMON_MAGIC, + .version = 0x1, + .core_bit_map = 0x3333, +}; + +void sec_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &common_base_info, sizeof(common_base_info)); + arm_smccc_smc(CPU_INIT_SEC_SVC, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("SEC init failed :0x%lx\n", res.a0); +} diff --git a/configs/pomelo_defconfig b/configs/pomelo_defconfig new file mode 100644 index 0000000000..a963d85fbb --- /dev/null +++ b/configs/pomelo_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_TARGET_POMELO=y +CONFIG_SYS_TEXT_BASE=0x180000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="phytium-pomelo" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_LAST_STAGE_INIT=y +CONFIG_SYS_PROMPT="pomelo#" +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_PHYTIUM=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_PL01X_SERIAL=y diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h new file mode 100644 index 0000000000..01632021b1 --- /dev/null +++ b/include/configs/pomelo.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef __POMELO_CONFIG_H__ +#define __POMELO_CONFIG_H__ + +/* SDRAM Bank #1 start address */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LOAD_ADDR (0x80000000 + 0x10000000) + +/* SIZE of malloc pool */ +#define CONFIG_SYS_MALLOC_LEN (0x100000 + 0x1000) +#define CONFIG_SYS_INIT_SP_ADDR (0x29800000 + 0x1a000) + +/* PCI CONFIG */ +#define CONFIG_SYS_PCI_64BIT 1 + +/*BOOT*/ +#define CONFIG_SYS_BOOTM_LEN 0x3c00000 +#define CONFIG_BOARD_EARLY_INIT_F + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(SCSI, scsi, 0) \ + +#include <config_distro_bootcmd.h> +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "image=Image\0" \ + BOOTENV \ + "scriptaddr=0x90100000\0" \ + "kernel_addr_r=0x90100000\0" \ + "fdt_addr_r=0x95000000\0" \ + "boot_fit=no\0" \ + "fdtfile=ft-d2000.dtb\0" \ + +#endif + -- 2.17.1

2 1

[PATCH 00/10] stm32mp1: Support falcon mode with OP-TEE payloads
by Alexandru Gagniuc 03 Sep '21

03 Sep '21

My goal when I started on this project a year ago was to get to linux userspace within a second from power on. Oh, and it had to be secure! Contrast that to the two minutes it took the STLinux demo to come up. It was obvious that the accepted way of running an FSBL, then SSBL was going to blow the time budget. There really wasn't a good solution, and traditional falcon mode with "spl export" command was not secure. I chose to use SPL with a FIT payload. We have to add certain logic to SPL, as well as some FDT modifications that would be normally done in u-boot. The boot flow is SPL -> OP-TEE -> Linux Incidentally, these patches are some of the earlier ones I wrote for this project. It didn't make sense to publish them at the time, as the supporting infrastructure was not in place then I decided not to separate these patches into mini-series. Alexandru Gagniuc (10): stm32mp1: Add support for baudrates higher than 115200 stm32mp1: Add support for falcon mode boot from SD card board: stm32mp1: Implement board_fit_config_name_match() for SPL fdt_support: Implement fdt_ethernet_set_macaddr() arm: stm32mp: bsec: Do not skip .probe() for SPL arm: stm32mp: Factor out reading MAC address from OTP stm32mp1: spl: Configure MAC address when booting OP-TEE lib: Makefile: Make optee library available in SPL ARM: dts: stm32mp: Add OP-TEE "/firmware" node to SPL dtb stm32mp1: spl: Copy optee nodes to target FDT for OP-TEE payloads arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 1 + arch/arm/mach-stm32mp/bsec.c | 2 +- arch/arm/mach-stm32mp/cpu.c | 59 ++++++++++++++----- .../arm/mach-stm32mp/include/mach/sys_proto.h | 3 + arch/arm/mach-stm32mp/spl.c | 3 + board/st/stm32mp1/spl.c | 49 +++++++++++++++ common/fdt_support.c | 30 ++++++++++ include/configs/stm32mp1.h | 17 ++++++ include/fdt_support.h | 17 ++++++ lib/Makefile | 2 +- 10 files changed, 167 insertions(+), 16 deletions(-) -- 2.31.1

5 25

Usage of device-tree for blobs
by Heinrich Schuchardt 03 Sep '21

03 Sep '21

Hello Simon, some boards like qemu-riscv64_defconfig do not use any device-tree at build time. A device-tree is only supplied at runtime by the prior boot stage (CONFIG_OF_PRIOR_STAGE=y). In doc/develop/devicetree/intro.rst you suggest to put binary blobs into the device-tree. Could you, please, update the documentation to explain how adding blobs to the device-tree works in the different scenarios depending on the values of: CONFIG_OF_EMBED CONFIG_OF_SEPARATE CONFIG_OF_BOARD CONFIG_OF_HOSTFILE CONFIG_OF_PRIOR_STAGE It would be especially important to understand how one can develop a board independent feature which works for all of these settings. Please, describe CONFIG_OF_PRIOR_STAGE in doc/develop/devicetree/control.rst. Best regards Heinrich

4 14

[PATCH 1/2] arm: dts: imx8mq: Add Kontron pitx-imx8m
by Heiko Thiery 03 Sep '21

03 Sep '21

This adds the device tree for the Kontron pitx-imx8m Board. It is a copy of the device tree from the linux kernel sources. Signed-off-by: Heiko Thiery <heiko.thiery(a)gmail.com> --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts | 613 +++++++++++++++++++++ 2 files changed, 615 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index fc16a57e60..c2c6f1a953 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -887,7 +887,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-phanbell.dtb \ imx8mp-evk.dtb \ imx8mp-phyboard-pollux-rdk.dtb \ - imx8mq-pico-pi.dtb + imx8mq-pico-pi.dtb \ + imx8mq-kontron-pitx-imx8m.dtb dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ imxrt1020-evk.dtb diff --git a/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts b/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts new file mode 100644 index 0000000000..f593e4ff62 --- /dev/null +++ b/arch/arm/dts/imx8mq-kontron-pitx-imx8m.dts @@ -0,0 +1,613 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree File for the Kontron pitx-imx8m board. + * + * Copyright (C) 2021 Heiko Thiery <heiko.thiery(a)gmail.com> + */ + +/dts-v1/; + +#include "imx8mq.dtsi" +#include <dt-bindings/net/ti-dp83867.h> + +/ { + model = "Kontron pITX-imx8m"; + compatible = "kontron,pitx-imx8m", "fsl,imx8mq"; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + spi0 = &qspi0; + spi1 = &ecspi2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + pcie0_refclk: pcie0-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie1_refclk: pcie1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2>; + regulator-name = "V_3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; +}; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670"; + reg = <0>; + spi-max-frequency = <43000000>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <&ethphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + reset-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <280>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@8 { + compatible = "fsl,pfuze100"; + fsl,pfuze-support-disable-sw; + reg = <0x8>; + + regulators { + sw1a_reg: sw1ab { + regulator-name = "V_0V9_GPU"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + }; + + sw1c_reg: sw1c { + regulator-name = "V_0V9_VPU"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + }; + + sw2_reg: sw2 { + regulator-name = "V_1V1_NVCC_DRAM"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-name = "V_1V0_DRAM"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-name = "V_1V8_S0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-name = "NC"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-name = "V_0V9_SNVS"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-name = "V_0V55_VREF_DDR"; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-name = "V_1V5_CSI"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-name = "V_0V9_PHY"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <975000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-name = "V_1V8_PHY"; + regulator-min-microvolt = <1675000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-name = "V_1V8_VDDA"; + regulator-min-microvolt = <1625000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-name = "V_3V3_PHY"; + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3625000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-name = "V_2V8_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + fan-controller@1b { + compatible = "maxim,max6650"; + reg = <0x1b>; + maxim,fan-microvolt = <5000000>; + }; + + rtc@32 { + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; + + sensor@4b { + compatible = "national,lm75b"; + reg = <0x4b>; + }; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +/* M.2 B-key slot */ +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, + <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + status = "okay"; +}; + +/* Intel Ethernet Controller I210/I211 */ +&pcie1 { + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + fsl,max-link-speed = <1>; + status = "okay"; +}; + +&pgc_gpu { + power-supply = <&sw1a_reg>; +}; + +&pgc_vpu { + power-supply = <&sw1c_reg>; +}; + +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + spi-max-frequency = <50000000>; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clk IMX8MQ_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + fsl,uart-has-rtscts; + assigned-clocks = <&clk IMX8MQ_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vqmmc-supply = <&sw4_reg>; + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + vmmc-supply = <&reg_usdhc2_vmmc>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* TPM Reset */ + MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* USB2 Hub Reset */ + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* GPIO0 */ + MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 /* GPIO1 */ + MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 /* GPIO2 */ + MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* GPIO3 */ + MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* GPIO4 */ + MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* GPIO5 */ + MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* GPIO6 */ + MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x19 /* GPIO7 */ + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x16 /* PCIE_PERST */ + MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 /* W_DISABLE */ + >; + }; + + pinctrl_reg_usdhc2: regusdhc2gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 + MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x16 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19 + MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19 + MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19 + >; + }; + + pinctrl_ecspi2_cs: ecspi2csgrp { + fsl,pins = < + MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 + MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 + MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x19 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usb0: usb0grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x19 + MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; -- 2.30.0

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[PATCH] config/sifive_unmatched: add preboot commands
by Alexander von Gluck IV 03 Sep '21

03 Sep '21

* Opens up u-boot to properly search through USB media for a valid boot media * The MMC on the unmatched is slow, so a model of running the OS from USB or NVMe is a compelling one. (putting just u-boot on the sd card) --- configs/sifive_unmatched_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index 38b7acd536..0e02d46f72 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -11,6 +11,7 @@ CONFIG_TARGET_SIFIVE_UNMATCHED=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y # CONFIG_SPL_USE_ARCH_MEMMOVE is not set +CONFIG_PREBOOT="pci enum; usb start;" CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000 -- 2.32.0

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[PATCH 0/3] Miscellaneous fixes of efi_tcg2
by Masahisa Kojima 03 Sep '21

03 Sep '21

Arm is preparing the BBSR(Base Boot Security Requirement) compiance test tool. This tool covers Measured Boot, it checks TCG EFI Protocol compliance. This patch series fix the failure items detected by this BBSR compliance test tool. Masahisa Kojima (3): efi_loader: add missing parameter check for EFI_TCG2_PROTOCOL api efi_loader: fix boot_service_capability_min calculation efi_loader: fix efi_tcg2_hash_log_extend_event() parameter check include/efi_tcg2.h | 4 +++- lib/efi_loader/efi_tcg2.c | 21 ++++++++++++++++++++- 2 files changed, 23 insertions(+), 2 deletions(-) -- 2.17.1

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