September 2021 - U-Boot

[PATCH v2 0/2] PinePhone: enable LED on boot for improved
by Arnaud Ferraris 09 Sep '21

09 Sep '21

Hi, As the PinePhone doesn't provide any visual feedback when booting, these patches take advantage of the built-in RGB LED to indicate the device is indeed powered on. I've been carrying those downstream in Mobian for some time now, allowing users to see their phone is booting (otherwise it can be several seconds before the kernel is loaded and able to show a sign of life). Best regards, Arnaud -- Changes in v2: - limit the amount of #ifdef's in board.c - add a Reviewed-by record Arnaud Ferraris (2): board: sunxi: enable status LED early pinephone_defconfig: add support for early-boot status LED board/sunxi/board.c | 6 ++++++ configs/pinephone_defconfig | 6 ++++++ 2 files changed, 12 insertions(+)

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[u-boot PATCH] arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge
by Roger Quadros 08 Sep '21

08 Sep '21

NB0 is bridge to SRAM and NB1 is bridge to DDR. To ensure that SRAM transfers are not stalled due to delays during DDR refreshes, SRAM traffic should be higher priority (threadmap=2) than DDR traffic (threadmap=0). This patch does just that. This is required to fix ICSSG TX lock-ups due to delays in MSMC transfers due to incorrect Northbridge configuration. Signed-off-by: Roger Quadros <rogerq(a)ti.com> Acked-by: Andrew F. Davis <afd(a)ti.com> Acked-by: Tomi Valkeinen <tomi.valkeinen(a)ti.com> Acked-by: Benoit Parrot <bparrot(a)ti.com> --- arch/arm/mach-k3/am6_init.c | 14 ++++++++++++++ arch/arm/mach-k3/include/mach/am6_hardware.h | 7 +++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index 8d107b870b..9379b95bdb 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -86,6 +86,18 @@ static void store_boot_index_from_rom(void) bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); } +static void setup_am654_navss_northbridge(void) +{ + /* + * NB0 is bridge to SRAM and NB1 is bridge to DDR. + * To ensure that SRAM transfers are not stalled due to + * delays during DDR refreshes, SRAM traffic should be higher + * priority (threadmap=2) than DDR traffic (threadmap=0). + */ + writel(0x2, NAVSS0_NBSS_NB0_CFG_BASE + NAVSS_NBSS_THREADMAP); + writel(0x0, NAVSS0_NBSS_NB1_CFG_BASE + NAVSS_NBSS_THREADMAP); +} + void board_init_f(ulong dummy) { #if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS) @@ -101,6 +113,8 @@ void board_init_f(ulong dummy) /* Make all control module registers accessible */ ctrl_mmr_unlock(); + setup_am654_navss_northbridge(); + #ifdef CONFIG_CPU_V7R disable_linefill_optimization(); setup_k3_mpu_regions(); diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h index 6df7631545..45a5b31c52 100644 --- a/arch/arm/mach-k3/include/mach/am6_hardware.h +++ b/arch/arm/mach-k3/include/mach/am6_hardware.h @@ -47,4 +47,11 @@ /* MCU SCRATCHPAD usage */ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE +/* NAVSS Northbridge config */ +#define NAVSS0_NBSS_NB0_CFG_BASE 0x03802000 +#define NAVSS0_NBSS_NB1_CFG_BASE 0x03803000 + +#define NAVSS_NBSS_PID 0x0 +#define NAVSS_NBSS_THREADMAP 0x10 + #endif /* __ASM_ARCH_AM6_HARDWARE_H */ -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

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[PATCH v2 1/2] mmc: fsl_esdhc_imx: initialize data for imx7ulp
by Oleksandr Suvorov 08 Sep '21

08 Sep '21

From: Jorge Ramirez-Ortiz <jorge(a)foundries.io> Import data for eSDHC driver for SoC iMX7ULP from the Linux kernel. Set supported by u-boot flags only. Signed-off-by: Jorge Ramirez-Ortiz <jorge(a)foundries.io> Signed-off-by: Ricardo Salveti <ricardo(a)foundries.io> Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov(a)foundries.io> Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov(a)foundries.io> Reviewed-by: Fabio Estevam <festevam(a)gmail.com> --- Changes in v2: - add a Reviewed-by record drivers/mmc/fsl_esdhc_imx.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index aabf39535f..6c8f77f9ee 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1706,6 +1706,11 @@ static struct esdhc_soc_data usdhc_imx7d_data = { | ESDHC_FLAG_HS400, }; +static struct esdhc_soc_data usdhc_imx7ulp_data = { + .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING + | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, +}; + static struct esdhc_soc_data usdhc_imx8qm_data = { .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 | @@ -1720,7 +1725,7 @@ static const struct udevice_id fsl_esdhc_ids[] = { { .compatible = "fsl,imx6sl-usdhc", }, { .compatible = "fsl,imx6q-usdhc", }, { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,}, - { .compatible = "fsl,imx7ulp-usdhc", }, + { .compatible = "fsl,imx7ulp-usdhc", .data = (ulong)&usdhc_imx7ulp_data,}, { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,}, -- 2.31.1

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U-boot patches
by Sjöberg Andreas 08 Sep '21

08 Sep '21

Hi, We have two patch files for u-boot: Bootelf_async_abort_fix.patch: Booting a .elf files sometimes triggers an asynchronous abort error disabling the icache and dcahe before boot turned out to prevent this and this patch adds disabling of these caches as a part of the bootelf command. Tftp_next_ack_update: When running tftp without any additional options (i.e no oack gets sent) the client does not change the expected block number of the next package from 0 to tftp_windowsize preventing acknowledgement of received data. There also was no prober mreset for this counter that instead only reset upon receiveing an oack. This patch increments the value of next_ack when receiving a data packet instead of an oack and also ensures that sending a new read request or write request resets the counter to 0, indicating that the next packet should be an oack. /Andreas Sjöberg

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[PATCH] board: sl28: enable EFI_SET_TIME support
by Michael Walle 08 Sep '21

08 Sep '21

Allow EFI to set the time before ExitBootServices(). Signed-off-by: Michael Walle <michael(a)walle.cc> --- configs/kontron_sl28_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index e15928bead..8bd7d5be4b 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -92,3 +92,4 @@ CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_OF_LIBFDT_ASSUME_MASK=0x0 CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_EFI_SET_TIME=y -- 2.30.2

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Re: U-Boot Digest, Vol 158, Issue 63
by Oleksandr G Zhadan 08 Sep '21

08 Sep '21

Hello, Please see inline. On 7/26/21 9:40 AM, u-boot-request(a)lists.denx.de wrote: > Message: 13 > Date: Mon, 26 Jul 2021 07:34:06 -0600 > From: Simon Glass<sjg(a)chromium.org> > To: U-Boot Mailing List<u-boot(a)lists.denx.de> > Cc: Tom Rini<trini(a)konsulko.com>, Simon Glass<sjg(a)chromium.org>, > Albert Aribaud<albert.u.boot(a)aribaud.net>, Andy Fleming > <afleming(a)gmail.com>, Joe Hershberger<joe.hershberger(a)ni.com>, Marek > Vasut<marex(a)denx.de>, Mario Six<mario.six(a)gdsys.cc>, Oleksandr > Zhadan and Michael Durrant<arcsupport(a)arcturusnetworks.com>, Pavel > Herrmann<morpheus.ibis(a)gmail.com>, Priyanka Jain > <priyanka.jain(a)nxp.com>, Rob Herring<rob.herring(a)calxeda.com>, Stefan > Roese<sr(a)denx.de>, Stefano Babic<sbabic(a)denx.de>, Wolfgang Denk > <wd(a)denx.de> > Subject: [PATCH 00/33] pci: Drop all pre-driver model code > Message-ID:<20210726133440.634682-1-sjg(a)chromium.org> > > The hard work to actually enable DM_PCI everywhere was done recently. This > series attempts to drop most of the code that it no-longer needed now that > PCI has been converted to driver model. > It also drops the UCP1020 board since it has various unique build issues. What issues are we talking about?Please name it. Today's u-boot clone builds and runs fine in our module without any warnings except: > git clone https://source.denx.de/u-boot/u-boot.git u-boot-20210728 > cd u-boot-20210728 > make UCP1020_defconfig > CROSS_COMPILE=powerpc-linux- make 2>222 > cat 222 ===================== WARNING ====================== This board does not use CONFIG_DM. CONFIG_DM will be compulsory starting with the v2020.01 release. Failure to update may result in board removal. See doc/driver-model/migration.rst for more info. ==================================================== ===================== WARNING ====================== This board does not use CONFIG_DM_ETH (Driver Model for Ethernet drivers). Please update the board to use CONFIG_DM_ETH before the v2020.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. =================================================== > It doesn't even support driver model so it seems reasonable to just remove > it. 1. Sure it's my fault that I didn't notice the warnings that CONFIG_DM is the only choice to build and run u-boot. 2. Why is CONFIG_DM still present in `make menuconfig` options? 3. We only use u-boot as the first stage bootloader to start the kernel. We need minimal device controllers support. We don't need anything like PCI, USB, etc. 4. At least you need to add doc/driver-model/migration.rst to the source tree from https://source.denx.de/u-boot/u-boot.git if you point to it in your warnings. And 5. I have seen NO reason to remove ANY support board without REAL reasons to do so. SUMMARY: 1. UCP1020_defconfig does not have any compiler warnings on build (at least 2021.07.28 clone). 2. If now the only choice is CONFIG_DM, then it should be removed as an option from "make menuconfig", and we will definitely fix the related warnings/errors. 3. IMPO board support can be removed if it breaks when built and/or breaks any other builds. Thank you, Oleks > > The DM_PCI option disappears and only PCI is left. -- Oleksandr Zhadan oleks(a)arcturusnetworks.com 416.621.0125 x.235 }|{/\|)/\|-|

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tools: Check for already migrated symbols in a given file
by Tom Rini 08 Sep '21

08 Sep '21

Hey all, As I look over patchwork I see (as one would expect) platforms showing up that will come in either to -next, or once v2021.10 is out. Given the number of newly migrated symbols now in -next, along with my hope to get more done soon as well has having discovered lots of already migrated symbols showing up again in board config.h files, I want to pass along this bit of shell script. It's heavily borrowed from scripts/build-whitelist.sh and basically has comm providing a different column. It's also not fool-proof as I skipped handling CONFIG_SYS_EXTRA_OPTIONS as I just want to remove that symbol entirely. What you do with this is: $ check-migrated-symbols.sh include/configs/am335x_evm.h CONFIG_SYS_I2C_EEPROM_ADDR CONFIG_SYS_I2C_EEPROM_ADDR_LEN CONFIG_SYS_NAND_BLOCK_SIZE CONFIG_SYS_NAND_OOBSIZE CONFIG_SYS_NAND_PAGE_SIZE CONFIG_SYS_NAND_U_BOOT_OFFS And see that oh, those symbols need to be moved to the defconfig. I'm not posting this to complain about existing board files (but I'll be cleaning up stuff) but rather to note that when adding new boards, it's REALLY important to catch and fix those problems. And without a script of some sort, it's also a pain. So here's the script: #!/bin/bash if [ ! -f Kconfig ]; then echo "ERROR: Must be run from root of U-Boot directory" exit 1 fi # Cleanup when done. trap "{ rm -rf ${KSYMLST} ${KUSEDLST}; }" EXIT KSYMLST=`mktemp` KUSEDLST=`mktemp` # List of existing symbols cat `find . -name "Kconfig*"` | sed -n \ -e 's/^\s*config *$[A-Za-z0-9_]*$.*$/CONFIG_\1/p' \ -e 's/^\s*menuconfig *$[A-Za-z0-9_]*$.*$/CONFIG_\1/p' \ | sort -u > $KSYMLST # Check each argument while test $# -ne 0; do # Not a file [ ! -f "$1" ] && shift 1 grep '#define[[:blank:]]CONFIG_' $1 | sed -n 's/#define.$CONFIG_[A-Za-z0-9_]*$.*/\1/p' | sort -u > ${KUSEDLST} comm -12 ${KSYMLST} ${KUSEDLST} shift 1 done rm -f ${KSYMLST} ${KUSEDLST} -- Tom

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[PATCH v6] arm: add initial support for the Phytium Pomelo Board
by nicholas_zheng＠outlook.com 08 Sep '21

08 Sep '21

From: weichangzheng <nicholas_zheng(a)outlook.com> This adds platform code and the device tree for the Phytium Pomelo Board. The initial support comprises the UART and the PCIE. Signed-off-by: weichangzheng <nicholas_zheng(a)outlook.com> Changes since v1: updated to DT Changes since v2: Modify some explicit types and macro Changes since v3: Modify some SDRAM related macro definitions and distro_bootcmd Changes since v4: Modify distro_bootcmd Changes since v5: Modify the CPU node description of the DT --- arch/arm/Kconfig | 20 ++++ arch/arm/dts/Makefile | 1 + arch/arm/dts/phytium-pomelo.dts | 105 ++++++++++++++++++++ board/phytium/pomelo/Kconfig | 12 +++ board/phytium/pomelo/MAINTAINERS | 8 ++ board/phytium/pomelo/Makefile | 14 +++ board/phytium/pomelo/cpu.h | 73 ++++++++++++++ board/phytium/pomelo/ddr.c | 161 +++++++++++++++++++++++++++++++ board/phytium/pomelo/pcie.c | 60 ++++++++++++ board/phytium/pomelo/pll.c | 73 ++++++++++++++ board/phytium/pomelo/pomelo.c | 118 ++++++++++++++++++++++ board/phytium/pomelo/sec.c | 37 +++++++ configs/pomelo_defconfig | 18 ++++ include/configs/pomelo.h | 44 +++++++++ 14 files changed, 744 insertions(+) create mode 100644 arch/arm/dts/phytium-pomelo.dts create mode 100644 board/phytium/pomelo/Kconfig create mode 100644 board/phytium/pomelo/MAINTAINERS create mode 100644 board/phytium/pomelo/Makefile create mode 100644 board/phytium/pomelo/cpu.h create mode 100644 board/phytium/pomelo/ddr.c create mode 100644 board/phytium/pomelo/pcie.c create mode 100644 board/phytium/pomelo/pll.c create mode 100644 board/phytium/pomelo/pomelo.c create mode 100644 board/phytium/pomelo/sec.c create mode 100644 configs/pomelo_defconfig create mode 100644 include/configs/pomelo.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0448787b8b..029af85fcb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1818,6 +1818,25 @@ config TARGET_DURIAN Support for durian platform. It has 2GB Sdram, uart and pcie. +config TARGET_POMELO + bool "Support Phytium Pomelo Platform" + select ARM64 + select DM + select AHCI + select SCSI_AHCI + select AHCI_PCI + select BLK + select PCI + select DM_PCI + select SCSI + select DM_SCSI + select DM_SERIAL + select DM_ETH if NET + imply CMD_PCI + help + Support for pomelo platform. + It has 8GB Sdram, uart and pcie. + config TARGET_PRESIDIO_ASIC bool "Support Cortina Presidio ASIC Platform" select ARM64 @@ -2038,6 +2057,7 @@ source "board/toradex/colibri_pxa270/Kconfig" source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" source "board/phytium/durian/Kconfig" +source "board/phytium/pomelo/Kconfig" source "board/xen/xenguest_arm64/Kconfig" source "board/keymile/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9fb38682e6..45d0340bd3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1107,6 +1107,7 @@ dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb +dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb diff --git a/arch/arm/dts/phytium-pomelo.dts b/arch/arm/dts/phytium-pomelo.dts new file mode 100644 index 0000000000..b6ed8ea360 --- /dev/null +++ b/arch/arm/dts/phytium-pomelo.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * dts file for Phytium Pomelo board + * Copyright (C) 2021, Phytium Ltd. + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ +/dts-v1/; + +/ { + model = "Phytium Pomelo"; + compatible = "phytium,pomelo", "arm,armv8"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "phytium,pomelo", "arm,armv8"; + reg = <0>; + enable-method = "psci"; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "phytium,pomelo", "arm,armv8"; + reg = <1>; + enable-method = "psci"; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "phytium,pomelo", "arm,armv8"; + reg = <2>; + enable-method = "psci"; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "phytium,pomelo", "arm,armv8"; + reg = <3>; + enable-method = "psci"; + }; + + cpu@4 { + device_type = "cpu"; + compatible = "phytium,pomelo", "arm,armv8"; + reg = <4>; + enable-method = "psci"; + }; + + cpu@5 { + device_type = "cpu"; + compatible = "phytium,pomelo", "arm,armv8"; + reg = <5>; + enable-method = "psci"; + }; + + cpu@6 { + device_type = "cpu"; + compatible = "phytium,pomelo", "arm,armv8"; + reg = <6>; + enable-method = "psci"; + }; + + cpu@7 { + device_type = "cpu"; + compatible = "phytium,pomelo", "arm,armv8"; + reg = <7>; + enable-method = "psci"; + }; + }; + + pcie@40000000 { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x0 0x40000000 0x0 0x10000000>; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00F00000>, + <0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>; + }; + + sysclk_48mhz: clk48mhz { + compatible = "fixed-clock"; + #clock-cells = <0x0>; + clock-frequency = <48000000>; + clock-output-names = "sysclk_48mhz"; + }; + + uart0: serial@28001000 { + compatible = "arm,pl011"; + reg = <0x0 0x28001000 0x0 0x1000>; + clocks = <&sysclk_48mhz>; + }; +}; diff --git a/board/phytium/pomelo/Kconfig b/board/phytium/pomelo/Kconfig new file mode 100644 index 0000000000..281aa8feff --- /dev/null +++ b/board/phytium/pomelo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_POMELO + +config SYS_BOARD + default "pomelo" + +config SYS_VENDOR + default "phytium" + +config SYS_CONFIG_NAME + default "pomelo" + +endif diff --git a/board/phytium/pomelo/MAINTAINERS b/board/phytium/pomelo/MAINTAINERS new file mode 100644 index 0000000000..d76a4a026e --- /dev/null +++ b/board/phytium/pomelo/MAINTAINERS @@ -0,0 +1,8 @@ +POMELO BOARD +M: lixinde <lixinde(a)phytium.com.cn> +M: weichangzheng <weichangzheng(a)phytium.com.cn> +S: Maintained +F: board/phytium/pomelo/* +F: include/configs/pomelo.h +F: configs/pomelo_defconfig +F: arch/arm/dts/phytium-pomelo.dts diff --git a/board/phytium/pomelo/Makefile b/board/phytium/pomelo/Makefile new file mode 100644 index 0000000000..b9cb3609bd --- /dev/null +++ b/board/phytium/pomelo/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2021 +# lixinde <lixinde(a)phytium.com.cn> +# weichangzheng <weichangzheng(a)phytium.com.cn> +# + +obj-y += pomelo.o +obj-y += pll.o +obj-y += pcie.o +obj-y += ddr.o +obj-y += sec.o + + diff --git a/board/phytium/pomelo/cpu.h b/board/phytium/pomelo/cpu.h new file mode 100644 index 0000000000..005ea5982b --- /dev/null +++ b/board/phytium/pomelo/cpu.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 + * Phytium Technology Ltd <www.phytium.com> + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef _FT_POMELO_H +#define _FT_POMELO_H + +/* SMCCC ID */ +#define CPU_SVC_VERSION 0xC2000F00 +#define CPU_GET_RST_SOURCE 0xC2000F01 +#define CPU_INIT_PLL 0xC2000F02 +#define CPU_INIT_PCIE 0xC2000F03 +#define CPU_INIT_MEM 0xC2000F04 +#define CPU_INIT_SEC_SVC 0xC2000F05 + +/*CPU RESET*/ +#define CPU_RESET_POWER_ON 0x1 +#define CPU_RESET_PLL 0x4 +#define CPU_RESET_WATCH_DOG 0x8 + +/* PLL */ +#define PARAMETER_PLL_MAGIC 0x54460010 + +/* PCIE */ +#define PARAMETER_PCIE_MAGIC 0x54460011 +#define CFG_INDEPENDENT_TREE 0x0 +#define PCI_PEU0 0x1 +#define PCI_PEU1 0x1 +#define PEU1_OFFSET 16 +#define PEU_C_OFFSET_MODE 16 +#define PEU_C_OFFSET_SPEED 0 +#define RC_MODE 0x1 +#define X8X8 0x1 +#define GEN3 3 + +/* DDR */ +#define PARAMETER_MCU_MAGIC 0x54460014 +#define PARAM_MCU_VERSION 0x1 +#define PARAM_MCU_SIZE 0x100 +#define PARAM_CH_ENABLE 0x3 +#define PARAM_ECC_ENABLE 0x3 +#define PARAM_FORCE_SPD_DISABLE 0x0 +#define PARAM_MCU_MISC_ENABLE 0x0 + +#define UDIMM_TYPE 0x2 +#define DIMM_X8 0x1 +#define NO_MIRROR 0x0 +#define NO_ECC_TYPE 0 +#define DDR4_TYPE 0xC + +/* SEC */ +#define PARAMETER_COMMON_MAGIC 0x54460013 + +/* FLUSH L3 CASHE */ +#define HNF_COUNT 0x8 +#define HNF_PSTATE_REQ (HNF_BASE + 0x10) +#define HNF_PSTATE_STAT (HNF_BASE + 0x18) +#define HNF_PSTATE_OFF 0x0 +#define HNF_PSTATE_SFONLY 0x1 +#define HNF_PSTATE_HALF 0x2 +#define HNF_PSTATE_FULL 0x3 +#define HNF_STRIDE 0x10000 +#define HNF_BASE (unsigned long)(0x3A200000) +void ddr_init(void); +void sec_init(void); +void check_reset(void); +void pcie_init(void); + +#endif /* _FT_POMELO_H */ diff --git a/board/phytium/pomelo/ddr.c b/board/phytium/pomelo/ddr.c new file mode 100644 index 0000000000..c6dbed9639 --- /dev/null +++ b/board/phytium/pomelo/ddr.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct ddr_spd { + /******************* read from spd *****************/ + u8 dimm_type; /* 1: RDIMM;2: UDIMM;3: SODIMM;4: LRDIMM */ + u8 data_width; /* 0: x4; 1: x8; 2: x16 */ + u8 mirror_type;/* 0: stardard; 1: mirror */ + u8 ecc_type; /* 0: no-ecc; 1:ecc */ + u8 dram_type; /* 0xB: DDR3; 0xC: DDR4 */ + u8 rank_num; + u8 row_num; + u8 col_num; + + u8 bg_num; /*only DDR4*/ + u8 bank_num; + u16 module_manufacturer_id; + u16 taamin; + u16 trcdmin; + + u16 trpmin; + u16 trasmin; + u16 trcmin; + u16 tfawmin; + + u16 trrd_smin; /*only DDR4*/ + u16 trrd_lmin; /*only DDR4*/ + u16 tccd_lmin; /*only DDR4*/ + u16 twrmin; + + u16 twtr_smin; /*only DDR4*/ + u16 twtr_lmin; /*only DDR4*/ + u16 twtrmin; /*only DDR3*/ + u16 trrdmin; /*only DDR3*/ + + /******************* RCD control words *****************/ + u8 f0rc03; /*bit[3:2]:CS bit[1:0]:CA */ + u8 f0rc04; /*bit[3:2]:ODT bit[1:0]:CKE */ + u8 f0rc05; /*bit[3:2]:CLK-A side bit[1:0]:CLK-B side */ + u8 bc00; + u8 bc01; + u8 bc02; + u8 bc03; + u8 bc04; + + u8 bc05; + u8 f5bc5x; + u8 f5bc6x; + /******************* LRDIMM special *****************/ + u8 vrefdq_pr0; + u8 vrefdq_mdram; + u8 rtt_mdram_1866; + u8 rtt_mdram_2400; + u8 rtt_mdram_3200; + + u8 drive_dram; + u8 odt_dram_1866; + u8 odt_dram_2400; + u8 odt_dram_3200; + u8 park_dram_1866; + u8 park_dram_2400; + u8 park_dram_3200; + u8 rcd_num; +} __attribute((aligned(4))); + +struct mcu_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + + u8 ch_enable; + u8 misc1_enable; + u8 misc2_enable; + u8 force_spd_enable; + u8 misc3_enable; + u8 train_debug; + u8 train_recover; + u8 rev2[9]; + + struct ddr_spd ddr_spd_info[2]; +} __attribute((aligned(4))); + +static void get_mcu_up_info_default(struct mcu_config *pm) +{ + pm->magic = PARAMETER_MCU_MAGIC; + pm->version = PARAM_MCU_VERSION; + pm->size = PARAM_MCU_SIZE; + pm->ch_enable = PARAM_CH_ENABLE; + pm->misc1_enable = PARAM_ECC_ENABLE; + pm->force_spd_enable = PARAM_FORCE_SPD_DISABLE; + pm->misc3_enable = PARAM_MCU_MISC_ENABLE; + pm->train_recover = 0x0; +} + +static u8 init_dimm_param(u8 ch, struct mcu_config *pm) +{ + debug("manual config dimm info...\n"); + pm->ddr_spd_info[ch].dimm_type = UDIMM_TYPE; + pm->ddr_spd_info[ch].data_width = DIMM_X8; + pm->ddr_spd_info[ch].mirror_type = NO_MIRROR; + pm->ddr_spd_info[ch].ecc_type = NO_ECC_TYPE; + pm->ddr_spd_info[ch].dram_type = DDR4_TYPE; + pm->ddr_spd_info[ch].rank_num = 1; + pm->ddr_spd_info[ch].row_num = 16; + pm->ddr_spd_info[ch].col_num = 10; + pm->ddr_spd_info[ch].bg_num = 4; + pm->ddr_spd_info[ch].bank_num = 4; + pm->ddr_spd_info[ch].taamin = 13750; + pm->ddr_spd_info[ch].trcdmin = 13750; + + pm->ddr_spd_info[ch].trpmin = 13750; + pm->ddr_spd_info[ch].trasmin = 32000; + pm->ddr_spd_info[ch].trcmin = 45750; + pm->ddr_spd_info[ch].tfawmin = 21000; + + pm->ddr_spd_info[ch].trrd_smin = 3000; + pm->ddr_spd_info[ch].trrd_lmin = 4900; + pm->ddr_spd_info[ch].tccd_lmin = 5000; + pm->ddr_spd_info[ch].twrmin = 15000; + + pm->ddr_spd_info[ch].twtr_smin = 2500; + pm->ddr_spd_info[ch].twtr_lmin = 7500; + + return 0; +} + +void get_default_mcu_info(u8 *data) +{ + get_mcu_up_info_default((struct mcu_config *)data); +} + +void fix_mcu_info(u8 *data) +{ + struct mcu_config *mcu_info = (struct mcu_config *)data; + + for (int ch = 0; ch < 2; ch++) + init_dimm_param(ch, mcu_info); +} + +void ddr_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + get_default_mcu_info(buffer); + fix_mcu_info(buffer); + + arm_smccc_smc(CPU_INIT_MEM, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("DRAM init failed :0x%lx\n", res.a0); +} diff --git a/board/phytium/pomelo/pcie.c b/board/phytium/pomelo/pcie.c new file mode 100644 index 0000000000..698d82fd8d --- /dev/null +++ b/board/phytium/pomelo/pcie.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct pcu_ctr { + u32 base_config[3]; + u32 equalization[3]; + u8 rev[80]; +} __attribute((aligned(4))); + +struct pcu_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u32 independent_tree; + u32 base_cfg; + u8 rev2[16]; + struct pcu_ctr ctr_cfg[2]; +} __attribute((aligned(4))); + +struct pcu_config const peu_base_info = { + .magic = PARAMETER_PCIE_MAGIC, + .version = 0x2, + .size = 0x100, + .independent_tree = CFG_INDEPENDENT_TREE, + .base_cfg = ((PCI_PEU1 | (X8X8 << 1)) << PEU1_OFFSET | (PCI_PEU0 | (X8X8 << 1))), + .ctr_cfg[0].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[0] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[1] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[1].base_config[2] = (RC_MODE << PEU_C_OFFSET_MODE) | (GEN3 << PEU_C_OFFSET_SPEED), + .ctr_cfg[0].equalization[0] = 0x7, + .ctr_cfg[0].equalization[1] = 0x7, + .ctr_cfg[0].equalization[2] = 0x7, + .ctr_cfg[1].equalization[0] = 0x7, + .ctr_cfg[1].equalization[1] = 0x7, + .ctr_cfg[1].equalization[2] = 0x7, +}; + +void pcie_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &peu_base_info, sizeof(peu_base_info)); + arm_smccc_smc(CPU_INIT_PCIE, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("PCIE init failed :0x%lx\n", res.a0); +} diff --git a/board/phytium/pomelo/pll.c b/board/phytium/pomelo/pll.c new file mode 100644 index 0000000000..a66ffddf09 --- /dev/null +++ b/board/phytium/pomelo/pll.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct pll_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u32 core_pll; + u32 res1; + u32 lmu_pll; + u32 res2; + u32 res3; + u32 res4; + u32 res5; +} __attribute((aligned(4))); + +struct pll_config const pll_base_info = { + .magic = PARAMETER_PLL_MAGIC, + .version = 0x1, + .size = 0x30, + .core_pll = 2300, /*MHz*/ + .lmu_pll = 667, /*MHz*/ +}; + +u32 get_reset_source(void) +{ + struct arm_smccc_res res; + + arm_smccc_smc(CPU_GET_RST_SOURCE, 0, 0, 0, 0, 0, 0, 0, &res); + return res.a0; +} + +void pll_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &pll_base_info, sizeof(pll_base_info)); + arm_smccc_smc(CPU_INIT_PLL, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("PLL init failed :0x%lx\n", res.a0); +} + +void check_reset(void) +{ + u32 rst; + + rst = get_reset_source(); + + switch (rst) { + case CPU_RESET_POWER_ON: + pll_init(); + break; + case CPU_RESET_PLL: + break; + case CPU_RESET_WATCH_DOG: + break; + default: + panic("other reset source\n"); + } +} diff --git a/board/phytium/pomelo/pomelo.c b/board/phytium/pomelo/pomelo.c new file mode 100644 index 0000000000..4fbe1e5835 --- /dev/null +++ b/board/phytium/pomelo/pomelo.c @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <command.h> +#include <init.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> +#include <linux/arm-smccc.h> +#include <scsi.h> +#include <init.h> +#include <asm/u-boot.h> +#include "cpu.h" + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + debug("Phytium ddr init\n"); + ddr_init(); + + gd->mem_clk = 0; + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, 0x7b000000); + + sec_init(); + debug("PBF relocate done\n"); + + return 0; +} + +int board_init(void) +{ + return 0; +} + +void reset_cpu(void) +{ + struct arm_smccc_res res; + + debug("run in reset cpu\n"); + arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("reset cpu error, %lx\n", res.a0); +} + +int mach_cpu_init(void) +{ + check_reset(); + return 0; +} + +int board_early_init_f(void) +{ + pcie_init(); + return 0; +} + +static struct mm_region pomelo_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | + PTE_BLOCK_UXN + }, + { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x7b000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_NS | + PTE_BLOCK_INNER_SHARE + }, + { + 0, + } +}; + +struct mm_region *mem_map = pomelo_mem_map; + +int __asm_flush_l3_dcache(void) +{ + int i, pstate; + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE); + for (i = 0; i < HNF_COUNT; i++) { + do { + pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE); + } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); + } + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE); + + return 0; +} + +int last_stage_init(void) +{ + int ret; + + /* pci e */ + pci_init(); + /* scsi scan */ + ret = scsi_scan(true); + if (ret) { + printf("scsi scan failed\n"); + return CMD_RET_FAILURE; + } + return ret; +} diff --git a/board/phytium/pomelo/sec.c b/board/phytium/pomelo/sec.c new file mode 100644 index 0000000000..aeb3983f01 --- /dev/null +++ b/board/phytium/pomelo/sec.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#include <stdio.h> +#include <string.h> +#include <linux/arm-smccc.h> +#include <init.h> +#include "cpu.h" + +struct common_config { + u32 magic; + u32 version; + u32 size; + u8 rev1[4]; + u64 core_bit_map; +} __attribute((aligned(4))); + +struct common_config const common_base_info = { + .magic = PARAMETER_COMMON_MAGIC, + .version = 0x1, + .core_bit_map = 0x3333, +}; + +void sec_init(void) +{ + u8 buffer[0x100]; + struct arm_smccc_res res; + + memcpy(buffer, &common_base_info, sizeof(common_base_info)); + arm_smccc_smc(CPU_INIT_SEC_SVC, 0, (u64)buffer, 0, 0, 0, 0, 0, &res); + if (res.a0 != 0) + panic("SEC init failed :0x%lx\n", res.a0); +} diff --git a/configs/pomelo_defconfig b/configs/pomelo_defconfig new file mode 100644 index 0000000000..a963d85fbb --- /dev/null +++ b/configs/pomelo_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_TARGET_POMELO=y +CONFIG_SYS_TEXT_BASE=0x180000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="phytium-pomelo" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 earlycon=pl011,0x28001000 root=/dev/sda2 rw" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_LAST_STAGE_INIT=y +CONFIG_SYS_PROMPT="pomelo#" +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_PHYTIUM=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_PL01X_SERIAL=y diff --git a/include/configs/pomelo.h b/include/configs/pomelo.h new file mode 100644 index 0000000000..01632021b1 --- /dev/null +++ b/include/configs/pomelo.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2021 + * lixinde <lixinde(a)phytium.com.cn> + * weichangzheng <weichangzheng(a)phytium.com.cn> + */ + +#ifndef __POMELO_CONFIG_H__ +#define __POMELO_CONFIG_H__ + +/* SDRAM Bank #1 start address */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LOAD_ADDR (0x80000000 + 0x10000000) + +/* SIZE of malloc pool */ +#define CONFIG_SYS_MALLOC_LEN (0x100000 + 0x1000) +#define CONFIG_SYS_INIT_SP_ADDR (0x29800000 + 0x1a000) + +/* PCI CONFIG */ +#define CONFIG_SYS_PCI_64BIT 1 + +/*BOOT*/ +#define CONFIG_SYS_BOOTM_LEN 0x3c00000 +#define CONFIG_BOARD_EARLY_INIT_F + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(SCSI, scsi, 0) \ + +#include <config_distro_bootcmd.h> +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "image=Image\0" \ + BOOTENV \ + "scriptaddr=0x90100000\0" \ + "kernel_addr_r=0x90100000\0" \ + "fdt_addr_r=0x95000000\0" \ + "boot_fit=no\0" \ + "fdtfile=ft-d2000.dtb\0" \ + +#endif + -- 2.17.1

3 2

Hints on how to use efi_driver/efi_block_device.c
by Christian Melki 08 Sep '21

08 Sep '21

I was hoping that U-boot would detect BLOCK_IO devices provided by UEFI automatically. But I can't see anything attached under lsblk or find some other information about this. For example, Barebox works just fine on both Virtualbox and real hardware in this regard. Barebox does not have an emmc driver for the real hardware but piggybacks off the UEFI protocol for this. I'm sure that the idea with this U-boot driver is something like that, but would appreciate some hints on how to use it. Ie, standard usage. UEFI boots of a drive, posts some handles(?) to a block device and U-boot picks it up, not knowing more about the abstracted hardware. Best regards, Christian

4 6

Re: [PATCH] arm: imx8mp-evk: CLOCK Enable SPI and QOS clock
by Ramon Fried 08 Sep '21

08 Sep '21

On Wed, Sep 8, 2021 at 8:27 AM Arendt, Steffen <s.arendt(a)sensopart.de> wrote: > Enable clocks for SPI and QOS (Ethernet) for the imx8mp SoC > > > diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c > index c77500bcce..1ab5587e4e 100644 > --- a/drivers/clk/imx/clk-imx8mp.c > +++ b/drivers/clk/imx/clk-imx8mp.c > @@ -116,6 +116,30 @@ static const char *imx8mp_i2c6_sels[] = > {"clock-osc-24m", "sys_pll1_160m", "sys_ > "sys_pll3_out", "audio_pll1_out", > "video_pll1_out", > "audio_pll2_out", > "sys_pll1_133m", }; > > +#if CONFIG_IS_ENABLED(DM_SPI) > +static const char *imx8mp_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", > "sys_pll1_40m", > + "sys_pll1_160m", > "sys_pll1_800m", "sys_pll3_out", > + "sys_pll2_250m", > "audio_pll2_out", }; > + > +static const char *imx8mp_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", > "sys_pll1_40m", > + "sys_pll1_160m", > "sys_pll1_800m", "sys_pll3_out", > + "sys_pll2_250m", > "audio_pll2_out", }; > + > +static const char *imx8mp_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", > "sys_pll1_40m", > + "sys_pll1_160m", > "sys_pll1_800m", "sys_pll3_out", > + "sys_pll2_250m", > "audio_pll2_out", }; > +#endif > + > +#if CONFIG_IS_ENABLED(DWC_ETH_QOS) > +static const char *imx8mp_enet_qos_sels[] = {"osc_24m", "sys_pll2_125m", > "sys_pll2_50m", > + "sys_pll2_100m", > "sys_pll1_160m", "audio_pll1_out", > + "video_pll1_out", "clk_ext4", > }; > + > +static const char *imx8mp_enet_qos_timer_sels[] = {"osc_24m", > "sys_pll2_100m", "audio_pll1_out", > + "clk_ext1", "clk_ext2", > "clk_ext3", > + "clk_ext4", > "video_pll1_out", }; > +#endif > + > static const char *imx8mp_usdhc1_sels[] = {"clock-osc-24m", > "sys_pll1_400m", "sys_pll1_800m", > "sys_pll2_500m", > "sys_pll3_out", "sys_pll1_266m", > "audio_pll2_out", > "sys_pll1_100m", }; > @@ -397,6 +421,28 @@ static int imx8mp_clk_probe(struct udevice *dev) > > clk_dm(IMX8MP_CLK_USDHC3_ROOT, imx_clk_gate4("usdhc3_root_clk", > "usdhc3", base + 0x45e0, 0)); > > +#if CONFIG_IS_ENABLED(DM_SPI) > + clk_dm(IMX8MP_CLK_ECSPI1, > + imx8m_clk_composite("ecspi1", imx8mp_ecspi1_sels, base + > 0xb280)); > + clk_dm(IMX8MP_CLK_ECSPI2, > + imx8m_clk_composite("ecspi2", imx8mp_ecspi2_sels, base + > 0xb300)); > + clk_dm(IMX8MP_CLK_ECSPI3, > + imx8m_clk_composite("ecspi3", imx8mp_ecspi3_sels, base + > 0xc180)); > + clk_dm(IMX8MP_CLK_ECSPI1_ROOT, > + imx_clk_gate4("ecspi1_root_clk", "ecspi1", base + 0x4070, > 0)); > + clk_dm(IMX8MP_CLK_ECSPI2_ROOT, > + imx_clk_gate4("ecspi2_root_clk", "ecspi2", base + 0x4080, > 0)); > + clk_dm(IMX8MP_CLK_ECSPI3_ROOT, > + imx_clk_gate4("ecspi3_root_clk", "ecspi3", base + 0x4090, > 0)); > +#endif > + > +#if CONFIG_IS_ENABLED(DWC_ETH_QOS) > + clk_dm(IMX8MP_CLK_ENET_QOS, > + imx8m_clk_composite("enet_qos", > imx8mp_enet_qos_sels, base + 0xa880)); > + clk_dm(IMX8MP_CLK_ENET_QOS_TIMER, > + imx8m_clk_composite("enet_qos_timer", > imx8mp_enet_qos_timer_sels, base + 0xa900)); > +#endif > + > return 0; > } > > > [image: SensoPart] <https://www.sensopart.com/> > <https://www.linkedin.com/company/sensopart> > <https://www.youtube.com/user/sensopart> > <https://www.xing.com/pages/sensopartindustriesensorikgmbh> > > *SensoPart Industriesensorik GmbH* > Am Wiedenbach 1 > 79695 Wieden > Deutschland > > Eingetragen im Amtsgericht Freiburg i.Br. > Registernummer: HRB 660163 > USt-IdNr.: DE 811614252 > Geschäftsführer: Dr. Theodor Wanner, Thorsten Wanner > > Informationen gem. Art. 13 DSGVO für unsere Kunden, Partner, Lieferanten > finden Sie in unserer Erklärung zum Datenschutz unter > https://www.sensopart.com/de/datenschutz > > > Please make sure not to send signatures when you send patches. Thanks, Ramon.

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