September 2021 - U-Boot

[PATCH 01/12] lmb: Always compile arch_lmb_reserve() into U-Boot on arm
by Marek Vasut 24 Sep '21

24 Sep '21

The arch_lmb_reserve() is called by lib/lmb.c lmb_reserve_common() even if CMD_BOOT{I,M,Z} is not enabled. However, the arm32/arm64 variant of arch_lmb_reserve() is only compiled in if CMD_BOOT{I,M,Z} is enabled. This currently does not trigger build error, because there is an empty weak implementation of arch_lmb_reserve(), however that is not the function that should be used on arm32/arm64. Fix this by moving the arch_lmb_reserve() implementation into common code and always compile it in. Reviewed-by: Tom Rini <trini(a)konsulko.com> Signed-off-by: Marek Vasut <marek.vasut+renesas(a)gmail.com> Cc: Simon Glass <sjg(a)chromium.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt(a)gmail.com> Cc: Tom Rini <trini(a)konsulko.com> --- V2: Add RB --- arch/arm/lib/bootm.c | 45 -------------------------------------------- arch/arm/lib/stack.c | 45 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+), 45 deletions(-) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index f60ee3a7e6..dd6a69315a 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -16,7 +16,6 @@ #include <command.h> #include <cpu_func.h> #include <dm.h> -#include <lmb.h> #include <log.h> #include <asm/global_data.h> #include <dm/root.h> @@ -43,50 +42,6 @@ DECLARE_GLOBAL_DATA_PTR; static struct tag *params; -static ulong get_sp(void) -{ - ulong ret; - - asm("mov %0, sp" : "=r"(ret) : ); - return ret; -} - -void arch_lmb_reserve(struct lmb *lmb) -{ - ulong sp, bank_end; - int bank; - - /* - * Booting a (Linux) kernel image - * - * Allocate space for command line and board info - the - * address should be as high as possible within the reach of - * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused - * memory, which means far enough below the current stack - * pointer. - */ - sp = get_sp(); - debug("## Current stack ends at 0x%08lx ", sp); - - /* adjust sp by 4K to be safe */ - sp -= 4096; - for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - if (!gd->bd->bi_dram[bank].size || - sp < gd->bd->bi_dram[bank].start) - continue; - /* Watch out for RAM at end of address space! */ - bank_end = gd->bd->bi_dram[bank].start + - gd->bd->bi_dram[bank].size - 1; - if (sp > bank_end) - continue; - if (bank_end > gd->ram_top) - bank_end = gd->ram_top - 1; - - lmb_reserve(lmb, sp, bank_end - sp + 1); - break; - } -} - __weak void board_quiesce_devices(void) { } diff --git a/arch/arm/lib/stack.c b/arch/arm/lib/stack.c index b03e1cfc80..3f961f4454 100644 --- a/arch/arm/lib/stack.c +++ b/arch/arm/lib/stack.c @@ -12,6 +12,7 @@ */ #include <common.h> #include <init.h> +#include <lmb.h> #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; @@ -33,3 +34,47 @@ int arch_reserve_stacks(void) return 0; } + +static ulong get_sp(void) +{ + ulong ret; + + asm("mov %0, sp" : "=r"(ret) : ); + return ret; +} + +void arch_lmb_reserve(struct lmb *lmb) +{ + ulong sp, bank_end; + int bank; + + /* + * Booting a (Linux) kernel image + * + * Allocate space for command line and board info - the + * address should be as high as possible within the reach of + * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused + * memory, which means far enough below the current stack + * pointer. + */ + sp = get_sp(); + debug("## Current stack ends at 0x%08lx ", sp); + + /* adjust sp by 4K to be safe */ + sp -= 4096; + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + if (!gd->bd->bi_dram[bank].size || + sp < gd->bd->bi_dram[bank].start) + continue; + /* Watch out for RAM at end of address space! */ + bank_end = gd->bd->bi_dram[bank].start + + gd->bd->bi_dram[bank].size - 1; + if (sp > bank_end) + continue; + if (bank_end > gd->ram_top) + bank_end = gd->ram_top - 1; + + lmb_reserve(lmb, sp, bank_end - sp + 1); + break; + } +} -- 2.33.0

4 27

[PATCH] pci: Fix configuring io/memory base and limit registers of PCI bridges
by Pali Rohár 24 Sep '21

24 Sep '21

Lower 4 bits of PCI_MEMORY_BASE and PCI_MEMORY_LIMIT registers are reserved and should be zero. So do not set them to non-zero value. Lower 4 bits of PCI_PREF_MEMORY_BASE and PCI_PREF_MEMORY_LIMIT registers contain information if 64-bit memory addressing is supported. So preserve this information when overwriting these registers. Lower 4 bits of PCI_IO_BASE and PCI_IO_LIMIT register contain information if 32-bit io addressing is supported. So preserve this information and do not try to configure 32-bit io addressing (via PCI_IO_BASE_UPPER16 and PCI_IO_LIMIT_UPPER16 registers) when it is unsupported. Signed-off-by: Pali Rohár <pali(a)kernel.org> --- drivers/pci/pci_auto.c | 39 +++++++++++++++++++++++++++++---------- 1 file changed, 29 insertions(+), 10 deletions(-) diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c index b128a05dd380..7b6e629cae70 100644 --- a/drivers/pci/pci_auto.c +++ b/drivers/pci/pci_auto.c @@ -165,6 +165,7 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) struct pci_region *pci_prefetch; struct pci_region *pci_io; u16 cmdstat, prefechable_64; + u8 io_32; struct udevice *ctlr = pci_get_controller(dev); struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr); @@ -175,6 +176,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat); dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64); prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK; + dm_pci_read_config8(dev, PCI_IO_LIMIT, &io_32); + io_32 &= PCI_IO_RANGE_TYPE_MASK; /* Configure bus number registers */ dm_pci_write_config8(dev, PCI_PRIMARY_BUS, @@ -191,7 +194,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) * I/O space */ dm_pci_write_config16(dev, PCI_MEMORY_BASE, - (pci_mem->bus_lower & 0xfff00000) >> 16); + ((pci_mem->bus_lower & 0xfff00000) >> 16) & + PCI_MEMORY_RANGE_MASK); cmdstat |= PCI_COMMAND_MEMORY; } @@ -205,7 +209,8 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) * I/O space */ dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, - (pci_prefetch->bus_lower & 0xfff00000) >> 16); + (((pci_prefetch->bus_lower & 0xfff00000) >> 16) & + PCI_PREF_RANGE_MASK) | prefechable_64); if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) #ifdef CONFIG_SYS_PCI_64BIT dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, @@ -217,8 +222,10 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) cmdstat |= PCI_COMMAND_MEMORY; } else { /* We don't support prefetchable memory for now, so disable */ - dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000); - dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0); + dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000 | + prefechable_64); + dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0 | + prefechable_64); if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) { dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0); dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0); @@ -230,8 +237,10 @@ void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus) pciauto_region_align(pci_io, 0x1000); dm_pci_write_config8(dev, PCI_IO_BASE, - (pci_io->bus_lower & 0x0000f000) >> 8); - dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, + (((pci_io->bus_lower & 0x0000f000) >> 8) & + PCI_IO_RANGE_MASK) | io_32); + if (io_32 == PCI_IO_RANGE_TYPE_32) + dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16, (pci_io->bus_lower & 0xffff0000) >> 16); cmdstat |= PCI_COMMAND_IO; @@ -261,7 +270,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) pciauto_region_align(pci_mem, 0x100000); dm_pci_write_config16(dev, PCI_MEMORY_LIMIT, - (pci_mem->bus_lower - 1) >> 16); + ((pci_mem->bus_lower - 1) >> 16) & + PCI_MEMORY_RANGE_MASK); } if (pci_prefetch) { @@ -275,7 +285,8 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) pciauto_region_align(pci_prefetch, 0x100000); dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, - (pci_prefetch->bus_lower - 1) >> 16); + (((pci_prefetch->bus_lower - 1) >> 16) & + PCI_PREF_RANGE_MASK) | prefechable_64); if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) #ifdef CONFIG_SYS_PCI_64BIT dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, @@ -286,12 +297,20 @@ void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus) } if (pci_io) { + u8 io_32; + + dm_pci_read_config8(dev, PCI_IO_LIMIT, + &io_32); + io_32 &= PCI_IO_RANGE_TYPE_MASK; + /* Round I/O allocator to 4KB boundary */ pciauto_region_align(pci_io, 0x1000); dm_pci_write_config8(dev, PCI_IO_LIMIT, - ((pci_io->bus_lower - 1) & 0x0000f000) >> 8); - dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, + ((((pci_io->bus_lower - 1) & 0x0000f000) >> 8) & + PCI_IO_RANGE_MASK) | io_32); + if (io_32 == PCI_IO_RANGE_TYPE_32) + dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, ((pci_io->bus_lower - 1) & 0xffff0000) >> 16); } } -- 2.20.1

3 2

[PATCH v2] arm: mediatek: merge board Kconfigs into mach-mediatek
by Guillaume La Roque 24 Sep '21

24 Sep '21

On MediaTek boards we cannot override the SYS_BOARD / SYS_CONFIG_NAME variables from defconfig. This is because in board/mediatek/mtXXXX/Kconfig this value was override by default due to the if CONFIG_TARGET_MTXXXX condition. Merge all the Kconfigs to the mach-medatek/Kconfig. This way: - we only define SYS_{SOC,VENDOR} once - all board definitions are in a single place, simplifying the build logic. Signed-off-by: Guillaume La Roque <glaroque(a)baylibre.com> --- arch/arm/mach-mediatek/Kconfig | 42 +++++++++++++++++++++++----- arch/mips/mach-mtmips/Kconfig | 3 ++ arch/mips/mach-mtmips/mt7620/Kconfig | 8 +++++- arch/mips/mach-mtmips/mt7628/Kconfig | 9 +++++- board/mediatek/mt7620/Kconfig | 12 -------- board/mediatek/mt7622/Kconfig | 17 ----------- board/mediatek/mt7623/Kconfig | 13 --------- board/mediatek/mt7628/Kconfig | 12 -------- board/mediatek/mt7629/Kconfig | 17 ----------- board/mediatek/mt8183/Kconfig | 13 --------- board/mediatek/mt8512/Kconfig | 14 ---------- board/mediatek/mt8516/Kconfig | 13 --------- board/mediatek/mt8518/Kconfig | 14 ---------- 13 files changed, 53 insertions(+), 134 deletions(-) delete mode 100644 board/mediatek/mt7620/Kconfig delete mode 100644 board/mediatek/mt7622/Kconfig delete mode 100644 board/mediatek/mt7623/Kconfig delete mode 100644 board/mediatek/mt7628/Kconfig delete mode 100644 board/mediatek/mt7629/Kconfig delete mode 100644 board/mediatek/mt8183/Kconfig delete mode 100644 board/mediatek/mt8512/Kconfig delete mode 100644 board/mediatek/mt8516/Kconfig delete mode 100644 board/mediatek/mt8518/Kconfig diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index e067604d9b..43979838e0 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -80,12 +80,40 @@ config TARGET_MT8518 endchoice -source "board/mediatek/mt7622/Kconfig" -source "board/mediatek/mt7623/Kconfig" -source "board/mediatek/mt7629/Kconfig" -source "board/mediatek/mt8183/Kconfig" -source "board/mediatek/mt8512/Kconfig" -source "board/mediatek/mt8516/Kconfig" -source "board/mediatek/mt8518/Kconfig" +config SYS_BOARD + string "Board name" + default "mt7622" if TARGET_MT7622 + default "mt7623" if TARGET_MT7623 + default "mt7629" if TARGET_MT7629 + default "mt8183" if TARGET_MT8183 + default "mt8512" if TARGET_MT8512 + default "mt8516" if TARGET_MT8516 + default "mt8518" if TARGET_MT8518 + default "" + help + This option contains information about board name. + Based on this option board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> will + be used. + +config SYS_CONFIG_NAME + string "Board configuration name" + default "mt7622" if TARGET_MT7622 + default "mt7623" if TARGET_MT7623 + default "mt7629" if TARGET_MT7629 + default "mt8183" if TARGET_MT8183 + default "mt8512" if TARGET_MT8512 + default "mt8516" if TARGET_MT8516 + default "mt8518" if TARGET_MT8518 + default "" + help + This option contains information about board configuration name. + Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header + will be used for board configuration. + +config MTK_BROM_HEADER_INFO + string + default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622 + default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 + default "lk=1" if TARGET_MT7623 endif diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach-mtmips/Kconfig index 8756cadb0b..05347ff78c 100644 --- a/arch/mips/mach-mtmips/Kconfig +++ b/arch/mips/mach-mtmips/Kconfig @@ -1,6 +1,9 @@ menu "MediaTek MIPS platforms" depends on ARCH_MTMIPS +config SYS_VENDOR + default "mediatek" if BOARD_MT7628_RFB || BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB + config SYS_MALLOC_F_LEN default 0x1000 diff --git a/arch/mips/mach-mtmips/mt7620/Kconfig b/arch/mips/mach-mtmips/mt7620/Kconfig index 5db83eb9d9..3ca711ad0f 100644 --- a/arch/mips/mach-mtmips/mt7620/Kconfig +++ b/arch/mips/mach-mtmips/mt7620/Kconfig @@ -66,6 +66,12 @@ config CPU_FREQ_MULTI default 6 if CPU_FREQ_600MHZ default 7 if CPU_FREQ_620MHZ -source "board/mediatek/mt7620/Kconfig" +config SYS_CONFIG_NAME + string "Board configuration name" + default "mt7620" if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB + +config SYS_BOARD + string "Board name" + default "mt7620" if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB endif diff --git a/arch/mips/mach-mtmips/mt7628/Kconfig b/arch/mips/mach-mtmips/mt7628/Kconfig index e3f56e782e..feb122df32 100644 --- a/arch/mips/mach-mtmips/mt7628/Kconfig +++ b/arch/mips/mach-mtmips/mt7628/Kconfig @@ -45,8 +45,15 @@ config SPL_UART2_SPIS_PINMUX Select this if the UART2 of your board is connected to GPIO 16/17 (shared with SPIS) rather than the usual GPIO 20/21. +config SYS_BOARD + string "Board name" + default "mt7628" if BOARD_MT7628_RFB + +config SYS_CONFIG_NAME + string "Board configuration name" + default "mt7628" if BOARD_MT7628_RFB + source "board/gardena/smart-gateway-mt7688/Kconfig" -source "board/mediatek/mt7628/Kconfig" source "board/seeed/linkit-smart-7688/Kconfig" source "board/vocore/vocore2/Kconfig" diff --git a/board/mediatek/mt7620/Kconfig b/board/mediatek/mt7620/Kconfig deleted file mode 100644 index b9137adcc9..0000000000 --- a/board/mediatek/mt7620/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if BOARD_MT7620_RFB || BOARD_MT7620_MT7530_RFB - -config SYS_BOARD - default "mt7620" - -config SYS_VENDOR - default "mediatek" - -config SYS_CONFIG_NAME - default "mt7620" - -endif diff --git a/board/mediatek/mt7622/Kconfig b/board/mediatek/mt7622/Kconfig deleted file mode 100644 index d0abdc0a67..0000000000 --- a/board/mediatek/mt7622/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -if TARGET_MT7622 - -config SYS_BOARD - default "mt7622" - -config SYS_CONFIG_NAME - default "mt7622" - -config MTK_BROM_HEADER_INFO - string - default "lk=1" - -config MTK_BROM_HEADER_INFO - string - default "media=nor" - -endif diff --git a/board/mediatek/mt7623/Kconfig b/board/mediatek/mt7623/Kconfig deleted file mode 100644 index a8c670e71f..0000000000 --- a/board/mediatek/mt7623/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -if TARGET_MT7623 - -config SYS_BOARD - default "mt7623" - -config SYS_CONFIG_NAME - default "mt7623" - -config MTK_BROM_HEADER_INFO - string - default "lk=1" - -endif diff --git a/board/mediatek/mt7628/Kconfig b/board/mediatek/mt7628/Kconfig deleted file mode 100644 index d6b6f9d632..0000000000 --- a/board/mediatek/mt7628/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if BOARD_MT7628_RFB - -config SYS_BOARD - default "mt7628" - -config SYS_VENDOR - default "mediatek" - -config SYS_CONFIG_NAME - default "mt7628" - -endif diff --git a/board/mediatek/mt7629/Kconfig b/board/mediatek/mt7629/Kconfig deleted file mode 100644 index 6055164b52..0000000000 --- a/board/mediatek/mt7629/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -if TARGET_MT7629 - -config SYS_BOARD - default "mt7629" - -config SYS_CONFIG_NAME - default "mt7629" - -config MTK_SPL_PAD_SIZE - hex - default 0x10000 - -config MTK_BROM_HEADER_INFO - string - default "media=nor" - -endif diff --git a/board/mediatek/mt8183/Kconfig b/board/mediatek/mt8183/Kconfig deleted file mode 100644 index b75c3b8d80..0000000000 --- a/board/mediatek/mt8183/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -if TARGET_MT8183 - -config SYS_BOARD - default "mt8183" - -config SYS_CONFIG_NAME - default "mt8183" - -config MTK_BROM_HEADER_INFO - string - default "media=emmc" - -endif diff --git a/board/mediatek/mt8512/Kconfig b/board/mediatek/mt8512/Kconfig deleted file mode 100644 index 87bd1fbe69..0000000000 --- a/board/mediatek/mt8512/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -if TARGET_MT8512 - -config SYS_BOARD - default "mt8512" - -config SYS_CONFIG_NAME - default "mt8512" - - -config MTK_BROM_HEADER_INFO - string - default "media=nor" - -endif diff --git a/board/mediatek/mt8516/Kconfig b/board/mediatek/mt8516/Kconfig deleted file mode 100644 index a87d3872fe..0000000000 --- a/board/mediatek/mt8516/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -if TARGET_MT8516 - -config SYS_BOARD - default "mt8516" - -config SYS_CONFIG_NAME - default "mt8516" - -config MTK_BROM_HEADER_INFO - string - default "media=emmc" - -endif diff --git a/board/mediatek/mt8518/Kconfig b/board/mediatek/mt8518/Kconfig deleted file mode 100644 index 1971c4d8c3..0000000000 --- a/board/mediatek/mt8518/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -if TARGET_MT8518 - -config SYS_BOARD - default "mt8518" - -config SYS_CONFIG_NAME - default "mt8518" - - -config MTK_BROM_HEADER_INFO - string - default "media=nor" - -endif -- 2.25.1

2 1

[PATCH] image: add lz4 zstd compression magic map
by Artem Lapkin 24 Sep '21

24 Sep '21

Add lz4 and zstd compression magic map. Already can decompress images with lz4 and zstd compression type. Signed-off-by: Artem Lapkin <art(a)khadas.com> --- common/image.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/common/image.c b/common/image.c index 59c52a1f9a..e199d61a4c 100644 --- a/common/image.c +++ b/common/image.c @@ -216,6 +216,8 @@ static const struct comp_magic_map image_comp[] = { { IH_COMP_GZIP, "gzip", {0x1f, 0x8b},}, { IH_COMP_LZMA, "lzma", {0x5d, 0x00},}, { IH_COMP_LZO, "lzo", {0x89, 0x4c},}, + { IH_COMP_LZ4, "lz4", {0x04, 0x22},}, + { IH_COMP_ZSTD, "zstd", {0x28, 0xb5},}, { IH_COMP_NONE, "none", {}, }, }; -- 2.25.1

2 1

[PATCH] crc32: Add crc32 implementation using __builtin_aarch64_crc32b
by Marek Vasut 24 Sep '21

24 Sep '21

ARMv8.0 has optional crc32 instruction for crc32 calculation. The instruction is mandatory since ARMv8.1. The crc32 calculation is faster using the dedicated instruction, e.g. 1.4 GHz iMX8MN gives: => time crc32 0x50000000 0x2000000 time: 0.126 seconds # crc32 instruction time: 0.213 seconds # software crc32 Add implementation using the compiler builtin wrapper for the crc32 instruction and enable it by default, since we don't support any platforms which do not implement this instruction. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Simon Glass <sjg(a)chromium.org> Cc: Tom Rini <trini(a)konsulko.com> --- arch/arm/Kconfig | 9 +++++++++ arch/arm/Makefile | 4 ++++ lib/crc32.c | 7 +++++++ 3 files changed, 20 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2d59562665f..134d3c6563d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -10,6 +10,15 @@ config ARM64 select SYS_CACHE_SHIFT_6 if ARM64 +config ARM64_CRC32 + bool "Enable support for CRC32 instruction" + default y + help + ARMv8 implements dedicated crc32 instruction for crc32 calculation. + This is faster than software crc32 calculation. This instruction may + not be present on all ARMv8.0, but is always present on ARMv8.1 and + newer. + config POSITION_INDEPENDENT bool "Generate position-independent pre-relocation code" help diff --git a/arch/arm/Makefile b/arch/arm/Makefile index c68e598a675..ce977bf6323 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -18,7 +18,11 @@ arch-$(CONFIG_CPU_V7A) =$(call cc-option, -march=armv7-a, \ $(call cc-option, -march=armv7)) arch-$(CONFIG_CPU_V7M) =-march=armv7-m arch-$(CONFIG_CPU_V7R) =-march=armv7-r +ifeq ($(CONFIG_ARM64_CRC32),y) +arch-$(CONFIG_ARM64) =-march=armv8-a+crc +else arch-$(CONFIG_ARM64) =-march=armv8-a +endif # On Tegra systems we must build SPL for the armv4 core on the device # but otherwise we can use the value in CONFIG_SYS_ARM_ARCH diff --git a/lib/crc32.c b/lib/crc32.c index f2acc107fe4..a207e3d2b40 100644 --- a/lib/crc32.c +++ b/lib/crc32.c @@ -184,6 +184,12 @@ const uint32_t * ZEXPORT get_crc_table() */ uint32_t __efi_runtime crc32_no_comp(uint32_t crc, const Bytef *buf, uInt len) { +#ifdef CONFIG_ARM64_CRC32 + crc = cpu_to_le32(crc); + while (len--) + crc = __builtin_aarch64_crc32b(crc, *buf++); + return le32_to_cpu(crc); +#else const uint32_t *tab = crc_table; const uint32_t *b =(const uint32_t *)buf; size_t rem_len; @@ -221,6 +227,7 @@ uint32_t __efi_runtime crc32_no_comp(uint32_t crc, const Bytef *buf, uInt len) } return le32_to_cpu(crc); +#endif } #undef DO_CRC -- 2.33.0

2 1

[PATCH 2/2] armv8/cache.S: Triple with single instruction
by Pierre-Clément Tosi 24 Sep '21

24 Sep '21

Replace the current 2-instruction 2-step tripling code by a corresponding single instruction leveraging ARMv8-A's "flexible second operand as a register with optional shift". This has the added benefit (albeit arguably negligible) of reducing the final code size. Fix the comment as the tripled cache level is placed in x12, not x0. Signed-off-by: Pierre-Clément Tosi <ptosi(a)google.com> --- arch/arm/cpu/armv8/cache.S | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index aabb3dff61..5051597f6f 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -80,8 +80,7 @@ ENTRY(__asm_dcache_all) /* x15 <- return address */ loop_level: - lsl x12, x0, #1 - add x12, x12, x0 /* x0 <- tripled cache level */ + add x12, x0, x0, lsl #1 /* x12 <- tripled cache level */ lsr x12, x10, x12 and x12, x12, #7 /* x12 <- cache type */ cmp x12, #2 -- 2.33.0.259.gc128427fd7-goog -- Pierre

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[PATCH 1/2] armv8/cache.S: Read sysreg fields through ubfx
by Pierre-Clément Tosi 24 Sep '21

24 Sep '21

Improve the file's readability and conciseness by using the appropriate Aarch64 instruction: ubfx (unsigned bitfield extract). This makes the code easier to follow as it directly manipulates the offsets and widths of the fields read from system registers, as they are expressed in the Standard (ARM ARM). This has the added benefit (albeit arguably negligible) of reducing the final code size. Signed-off-by: Pierre-Clément Tosi <ptosi(a)google.com> --- arch/arm/cpu/armv8/cache.S | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index 443d94c262..aabb3dff61 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -27,13 +27,11 @@ ENTRY(__asm_dcache_level) msr csselr_el1, x12 /* select cache level */ isb /* sync change of cssidr_el1 */ mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ - and x2, x6, #7 /* x2 <- log2(cache line size)-4 */ + ubfx x2, x6, #0, #3 /* x2 <- log2(cache line size)-4 */ + ubfx x3, x6, #3, #10 /* x3 <- number of cache ways - 1 */ + ubfx x4, x6, #13, #15 /* x4 <- number of cache sets - 1 */ add x2, x2, #4 /* x2 <- log2(cache line size) */ - mov x3, #0x3ff - and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */ clz w5, w3 /* bit position of #ways */ - mov x4, #0x7fff - and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */ /* x12 <- cache level << 1 */ /* x2 <- line length offset */ /* x3 <- number of cache ways - 1 */ @@ -72,8 +70,7 @@ ENTRY(__asm_dcache_all) mov x1, x0 dsb sy mrs x10, clidr_el1 /* read clidr_el1 */ - lsr x11, x10, #24 - and x11, x11, #0x7 /* x11 <- loc */ + ubfx x11, x10, #24, #3 /* x11 <- loc */ cbz x11, finished /* if loc is 0, exit */ mov x15, lr mov x0, #0 /* start flush at cache level 0 */ @@ -131,8 +128,7 @@ ENDPROC(__asm_invalidate_dcache_all) .pushsection .text.__asm_flush_dcache_range, "ax" ENTRY(__asm_flush_dcache_range) mrs x3, ctr_el0 - lsr x3, x3, #16 - and x3, x3, #0xf + ubfx x3, x3, #16, #4 mov x2, #4 lsl x2, x2, x3 /* cache line size */ @@ -158,7 +154,7 @@ ENDPROC(__asm_flush_dcache_range) .pushsection .text.__asm_invalidate_dcache_range, "ax" ENTRY(__asm_invalidate_dcache_range) mrs x3, ctr_el0 - ubfm x3, x3, #16, #19 + ubfx x3, x3, #16, #4 mov x2, #4 lsl x2, x2, x3 /* cache line size */ -- 2.33.0.259.gc128427fd7-goog -- Pierre

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[PATCH] cmd: mmc: check whether card is SD or eMMC before hwpartition
by Jaehoon Chung 24 Sep '21

24 Sep '21

It doesn't need to follow more sequence to do the hwparititioning, because SD doesn't support hwpartitioning feature. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> --- cmd/mmc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/cmd/mmc.c b/cmd/mmc.c index f1e30d0cf64b..62c7e9129666 100644 --- a/cmd/mmc.c +++ b/cmd/mmc.c @@ -673,6 +673,11 @@ static int do_mmc_hwpartition(struct cmd_tbl *cmdtp, int flag, if (!mmc) return CMD_RET_FAILURE; + if (IS_SD(mmc)) { + puts("SD doesn't support partitioning\n"); + return CMD_RET_FAILURE; + } + if (argc < 1) return CMD_RET_USAGE; i = 1; -- 2.29.0

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Re: [PATCH 1/1] riscv: ae350: enable Coherence Manager for ae350
by Rick Chen 24 Sep '21

24 Sep '21

> From: Leo Yu-Chi Liang(梁育齊) <ycliang(a)andestech.com> > Sent: Thursday, September 23, 2021 10:34 AM > To: u-boot(a)lists.denx.de > Cc: Rick Jian-Zhi Chen(陳建志) <rick(a)andestech.com>; Leo Yu-Chi Liang(梁育齊) <ycliang(a)andestech.com> > Subject: [PATCH 1/1] riscv: ae350: enable Coherence Manager for ae350 > > If Coherence Manager were not set in the beginning, u-boot-spl would sometimes fail to boot to u-boot proper. > > Enable CM and I/D cache at the same time in harts_early_init > > Signed-off-by: Leo Yu-Chi Liang <ycliang(a)andestech.com> > --- > arch/riscv/cpu/ax25/cpu.c | 42 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 42 insertions(+) Reviewed-by: Rick Chen <rick(a)andestech.com>

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[RFC PATCH 1/4] Revert "nvme: Correct the prps per page calculation method"
by Stefan Agner 24 Sep '21

24 Sep '21

This reverts commit 859b33c948945f7904f60a2c12a3792d356d51ad. If there is more than one PRP List the last entry is a pointer to the next list. From the NVM Express specification: "The last entry within a memory page, as indicated by the memory page size in the CC.MPS field, shall be a PRP List pointer if there is more than a single memory page of data to be transferred." For the purpose of calculating the number of pages required for PRP lists we should always assume that the last entry is required for the next PRP list. Signed-off-by: Stefan Agner <stefan(a)agner.ch> Cc: Wesley Sheng <wesleyshenggit(a)sina.com> --- drivers/nvme/nvme.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c index f6465ea7f4..1ae3001a90 100644 --- a/drivers/nvme/nvme.c +++ b/drivers/nvme/nvme.c @@ -81,7 +81,7 @@ static int nvme_setup_prps(struct nvme_dev *dev, u64 *prp2, u64 *prp_pool; int length = total_len; int i, nprps; - u32 prps_per_page = page_size >> 3; + u32 prps_per_page = (page_size >> 3) - 1; u32 num_pages; length -= (page_size - offset); -- 2.33.0

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