September 2021 - U-Boot

[PATCH] mtd: spinand: macronix: Fix ECC Status Read
by li.haolin＠qq.com 08 Oct '21

08 Oct '21

From: Haolin Li <li.haolin(a)qq.com> According to datasheet, the upper four bits are reserved or used for reflecting the ECC status of the accumulated pages. The error bits number for the worst segment of the current page is encoded on lower four bits. Fix it by masking the upper bits. This same issue has been already fixed in the linux kernel by: "mtd: spinand: macronix: Fix ECC Status Read" (sha1: f4cb4d7b46f6409382fd981eec9556e1f3c1dc5d) Apply the same fix in the U-Boot driver. Signed-off-by: Haolin Li <li.haolin(a)qq.com> --- drivers/mtd/nand/spi/macronix.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c index f4a8e81639..6d643a8000 100644 --- a/drivers/mtd/nand/spi/macronix.c +++ b/drivers/mtd/nand/spi/macronix.c @@ -14,6 +14,8 @@ #include <linux/mtd/spinand.h> #define SPINAND_MFR_MACRONIX 0xC2 +#define MACRONIX_ECCSR_MASK 0x0F + static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), @@ -59,7 +61,13 @@ static int mx35lf1ge4ab_get_eccsr(struct spinand_device *spinand, u8 *eccsr) SPI_MEM_OP_DUMMY(1, 1), SPI_MEM_OP_DATA_IN(1, eccsr, 1)); - return spi_mem_exec_op(spinand->slave, &op); + int ret = spi_mem_exec_op(spinand->slave, &op); + + if (ret) + return ret; + + *eccsr &= MACRONIX_ECCSR_MASK; + return 0; } static int mx35lf1ge4ab_ecc_get_status(struct spinand_device *spinand, -- 2.25.1

2 1

[PATCH u-boot-marvell v2 0/6] A3720 PCIe enhancements
by Marek Behún 08 Oct '21

08 Oct '21

From: Marek Behún <marek.behun(a)nic.cz> Hello Stefan, Pali has worked on some more enhancements for Armada 3720 PCIe driver (Aardvark). The main change is adding support for accessing configuration space of the PCI Bridge on the PCIe Root Port. Linux does something similar with pci-bridge-emul. Marek Changes since v1: - fix mistake in the documentation change in the last patch Marek Behún (2): arm: a37xx: pci: Cosmetic change arm: a37xx: pci: Update private structure documentation Pali Rohár (4): arm: a37xx: pci: Fix pcie_advk_link_up() arm: a37xx: pci: Add support for accessing PCI Bridge on root bus arm: a37xx: pci: Do not automatically enable bus mastering on PCI Bridge arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port drivers/pci/pci-aardvark.c | 199 +++++++++++++++++++++++++++++-------- include/pci.h | 4 + 2 files changed, 163 insertions(+), 40 deletions(-) -- 2.32.0

3 15

[PATCH u-boot-marvell 0/9] a38x serdes cleanup
by Marek Behún 08 Oct '21

08 Oct '21

Hi Stefan, this series by Pali cleans unneeded code in arch/arm/mach-mvebu/serdes/a38x. Pali studied the code, added comments about what the code does, and then removed unneeded parts, wich explanations in commits. Marek Pali Rohár (9): arm: mvebu: a38x: serdes: Add comments and use macros in PCIe code arm: mvebu: a38x: serdes: Remove duplicate macro SOC_CTRL_REG arm: mvebu: a38x: serdes: Add comments for hws_pex_config() code arm: mvebu: a38x: serdes: Don't overwrite read-only SAR PCIe registers arm: mvebu: a38x: serdes: Don't set PCIe Common Clock Configuration arm: mvebu: a38x: serdes: Don't overwrite PCI device ID arm: mvebu: a38x: serdes: Don't configure PCIe cards in SerDes init code arm: mvebu: a38x: serdes: Remove unused PCIe macros and functions arm: mvebu: a38x: serdes: Update comment about PCIE*_ENABLE_* defines arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.c | 297 +----------------- arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h | 68 +--- .../serdes/a38x/high_speed_env_spec.c | 42 +-- 3 files changed, 22 insertions(+), 385 deletions(-) -- 2.32.0

2 20

[PATCH 1/3] phy: marvell: a3700: Set TXDCLK_2X_SEL bit during PCIe initialization
by Pali Rohár 08 Oct '21

08 Oct '21

Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe Root Complex mode. Same change was included in TF-A project: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9408 Signed-off-by: Pali Rohár <pali(a)kernel.org> --- drivers/phy/marvell/comphy_a3700.c | 2 +- drivers/phy/marvell/comphy_a3700.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 5eb137db4884..afa1295bbdb8 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -200,7 +200,7 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) * 6. Enable the output of 100M/125M/500M clock */ reg_set16(phy_addr(PCIE, MISC_REG0), - 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF); + 0xA00D | rb_clk500m_en | rb_txdclk_2x_sel | rb_clk100m_125m_en, 0xFFFF); /* * 7. Enable TX diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h index 8748c6c84ae6..23c8ffbff44d 100644 --- a/drivers/phy/marvell/comphy_a3700.h +++ b/drivers/phy/marvell/comphy_a3700.h @@ -120,6 +120,7 @@ static inline void __iomem *phy_addr(enum phy_unit unit, u32 addr) #define MISC_REG0 0x4f #define rb_clk100m_125m_en BIT(4) +#define rb_txdclk_2x_sel BIT(6) #define rb_clk500m_en BIT(7) #define rb_ref_clk_sel BIT(10) -- 2.20.1

2 9

[PATCH] arm: a37xx: pci: Increase PCIe IO size from 64 KiB to 1 MiB
by Pali Rohár 08 Oct '21

08 Oct '21

Commit 079b35a26111 ("arm: a37xx: pci: Increase PCIe MEM size from 16 MiB to 127 MiB") increased size of PCIe MEM to 127 MiB, which is the maximal possible size for allocated 128 MiB PCIe window. PCIe IO size in that commit was unchanged. Armada 3720 PCIe controller supports 32-bit IO space mapping so it is possible to assign more than 64 KiB if address space for IO. Currently controller has assigned 127 MiB + 64 KiB memory and therefore there is 960 KiB of unused memory. So assign it to IO space by increasing IO window from 64 KiB to 1 MiB. Signed-off-by: Pali Rohár <pali(a)kernel.org> Fixes: 079b35a26111 ("arm: a37xx: pci: Increase PCIe MEM size from 16 MiB to 127 MiB") --- arch/arm/dts/armada-37xx.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi index 2615b8c748c1..fec34609cf82 100644 --- a/arch/arm/dts/armada-37xx.dtsi +++ b/arch/arm/dts/armada-37xx.dtsi @@ -335,14 +335,14 @@ /* * The 128 MiB address range [0xe8000000-0xf0000000] is * dedicated for PCIe and can be assigned to 8 windows - * with size a power of two. Use one 64 KiB window for + * with size a power of two. Use one 1 MiB window for * IO at the end and the remaining seven windows * (totaling 127 MiB) for MEM. */ ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x7f00000 /* Port 0 MEM */ - 0x81000000 0 0xefff0000 - 0 0xefff0000 0 0x10000>; /* Port 0 IO*/ + 0x81000000 0 0xeff00000 + 0 0xeff00000 0 0x100000>; /* Port 0 IO*/ }; }; }; -- 2.20.1

2 2

[PATCH 1/2] board: stm32mp1: Remove gpio_hog_probe_all() from board
by Patrice Chotard 08 Oct '21

08 Oct '21

DM_GPIO_HOG flag has been replaced by GPIO_HOG flag since a while in commit 49b10cb49262 ("gpio: fixes for gpio-hog support"). And furthermore, gpio_hog_probe_all() is already called in board_r.c. So gpio_hog_probe() can be removed from stm32mp1.c. Signed-off-by: Patrice Chotard <patrice.chotard(a)foss.st.com> --- board/st/stm32mp1/stm32mp1.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 032f08d795..b5500399e6 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -649,9 +649,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100; - if (CONFIG_IS_ENABLED(DM_GPIO_HOG)) - gpio_hog_probe_all(); - board_key_check(); if (board_is_ev1()) -- 2.17.1

4 6

[PATCH v1 0/7] i2c: stm32f7: driver update
by Patrice Chotard 08 Oct '21

08 Oct '21

This series is adding/updating several driver's feature: - each I2C instance has its own private data - add DT i2c-analog-filter property support - implement digital filter setting - add DT i2c-digital-filter-width-ns and i2c-digital-filter properties support - i2cclk is computed only one time Patrice Chotard (2): arm: dts: stm32: Add i2c-analog-filter property in I2C nodes for stm32f746 arm: dts: stm32: Add i2c-analog-filter property in I2C nodes for stm32h743 Patrick Delaunay (5): i2c: stm32f7: move driver data of each instance in a privdata i2c: stm32f7: support DT binding i2c-analog-filter i2c: stm32f7: fix configuration of the digital filter i2c: stm32f7: add support for DNF i2c-digital-filter binding i2c: stm32f7: compute i2cclk only one time arch/arm/dts/stm32f746.dtsi | 4 ++ arch/arm/dts/stm32h743.dtsi | 4 ++ drivers/i2c/stm32f7_i2c.c | 91 +++++++++++++++++++++---------------- 3 files changed, 59 insertions(+), 40 deletions(-) -- 2.17.1

2 21

[PATCH] spi: stm32: Add ofdata_to_platdata() callback
by Patrice Chotard 08 Oct '21

08 Oct '21

Parse DT in ofdata_to_platdata() callback instead of probe(). Signed-off-by: Patrice Chotard <patrice.chotard(a)foss.st.com> --- drivers/spi/stm32_spi.c | 224 +++++++++++++++++++++++----------------- 1 file changed, 132 insertions(+), 92 deletions(-) diff --git a/drivers/spi/stm32_spi.c b/drivers/spi/stm32_spi.c index bd8514033d..fe5419e851 100644 --- a/drivers/spi/stm32_spi.c +++ b/drivers/spi/stm32_spi.c @@ -97,11 +97,14 @@ #define SPI_SIMPLEX_RX 2 #define SPI_HALF_DUPLEX 3 -struct stm32_spi_priv { +struct stm32_spi_plat { void __iomem *base; struct clk clk; struct reset_ctl rst_ctl; struct gpio_desc cs_gpios[MAX_CS_COUNT]; +}; + +struct stm32_spi_priv { ulong bus_clk_rate; unsigned int fifo_size; unsigned int cur_bpw; @@ -115,28 +118,32 @@ struct stm32_spi_priv { bool cs_high; }; -static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv) +static void stm32_spi_write_txfifo(struct udevice *bus) { + struct stm32_spi_priv *priv = dev_get_priv(bus); + struct stm32_spi_plat *plat = dev_get_plat(bus); + void __iomem *base = plat->base; + while ((priv->tx_len > 0) && - (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP)) { + (readl(base + STM32_SPI_SR) & SPI_SR_TXP)) { u32 offs = priv->cur_xferlen - priv->tx_len; if (priv->tx_len >= sizeof(u32) && IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u32))) { const u32 *tx_buf32 = (const u32 *)(priv->tx_buf + offs); - writel(*tx_buf32, priv->base + STM32_SPI_TXDR); + writel(*tx_buf32, base + STM32_SPI_TXDR); priv->tx_len -= sizeof(u32); } else if (priv->tx_len >= sizeof(u16) && IS_ALIGNED((uintptr_t)(priv->tx_buf + offs), sizeof(u16))) { const u16 *tx_buf16 = (const u16 *)(priv->tx_buf + offs); - writew(*tx_buf16, priv->base + STM32_SPI_TXDR); + writew(*tx_buf16, base + STM32_SPI_TXDR); priv->tx_len -= sizeof(u16); } else { const u8 *tx_buf8 = (const u8 *)(priv->tx_buf + offs); - writeb(*tx_buf8, priv->base + STM32_SPI_TXDR); + writeb(*tx_buf8, base + STM32_SPI_TXDR); priv->tx_len -= sizeof(u8); } } @@ -144,9 +151,12 @@ static void stm32_spi_write_txfifo(struct stm32_spi_priv *priv) log_debug("%d bytes left\n", priv->tx_len); } -static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv) +static void stm32_spi_read_rxfifo(struct udevice *bus) { - u32 sr = readl(priv->base + STM32_SPI_SR); + struct stm32_spi_priv *priv = dev_get_priv(bus); + struct stm32_spi_plat *plat = dev_get_plat(bus); + void __iomem *base = plat->base; + u32 sr = readl(base + STM32_SPI_SR); u32 rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT; while ((priv->rx_len > 0) && @@ -158,7 +168,7 @@ static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv) (priv->rx_len >= sizeof(u32) || (sr & SPI_SR_RXWNE))) { u32 *rx_buf32 = (u32 *)(priv->rx_buf + offs); - *rx_buf32 = readl(priv->base + STM32_SPI_RXDR); + *rx_buf32 = readl(base + STM32_SPI_RXDR); priv->rx_len -= sizeof(u32); } else if (IS_ALIGNED((uintptr_t)(priv->rx_buf + offs), sizeof(u16)) && (priv->rx_len >= sizeof(u16) || @@ -166,38 +176,38 @@ static void stm32_spi_read_rxfifo(struct stm32_spi_priv *priv) (rxplvl >= 2 || priv->cur_bpw > 8)))) { u16 *rx_buf16 = (u16 *)(priv->rx_buf + offs); - *rx_buf16 = readw(priv->base + STM32_SPI_RXDR); + *rx_buf16 = readw(base + STM32_SPI_RXDR); priv->rx_len -= sizeof(u16); } else { u8 *rx_buf8 = (u8 *)(priv->rx_buf + offs); - *rx_buf8 = readb(priv->base + STM32_SPI_RXDR); + *rx_buf8 = readb(base + STM32_SPI_RXDR); priv->rx_len -= sizeof(u8); } - sr = readl(priv->base + STM32_SPI_SR); + sr = readl(base + STM32_SPI_SR); rxplvl = (sr & SPI_SR_RXPLVL) >> SPI_SR_RXPLVL_SHIFT; } log_debug("%d bytes left\n", priv->rx_len); } -static int stm32_spi_enable(struct stm32_spi_priv *priv) +static int stm32_spi_enable(void __iomem *base) { log_debug("\n"); /* Enable the SPI hardware */ - setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE); + setbits_le32(base + STM32_SPI_CR1, SPI_CR1_SPE); return 0; } -static int stm32_spi_disable(struct stm32_spi_priv *priv) +static int stm32_spi_disable(void __iomem *base) { log_debug("\n"); /* Disable the SPI hardware */ - clrbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_SPE); + clrbits_le32(base + STM32_SPI_CR1, SPI_CR1_SPE); return 0; } @@ -205,45 +215,48 @@ static int stm32_spi_disable(struct stm32_spi_priv *priv) static int stm32_spi_claim_bus(struct udevice *slave) { struct udevice *bus = dev_get_parent(slave); - struct stm32_spi_priv *priv = dev_get_priv(bus); + struct stm32_spi_plat *plat = dev_get_plat(bus); + void __iomem *base = plat->base; dev_dbg(slave, "\n"); /* Enable the SPI hardware */ - return stm32_spi_enable(priv); + return stm32_spi_enable(base); } static int stm32_spi_release_bus(struct udevice *slave) { struct udevice *bus = dev_get_parent(slave); - struct stm32_spi_priv *priv = dev_get_priv(bus); + struct stm32_spi_plat *plat = dev_get_plat(bus); + void __iomem *base = plat->base; dev_dbg(slave, "\n"); /* Disable the SPI hardware */ - return stm32_spi_disable(priv); + return stm32_spi_disable(base); } static void stm32_spi_stopxfer(struct udevice *dev) { - struct stm32_spi_priv *priv = dev_get_priv(dev); + struct stm32_spi_plat *plat = dev_get_plat(dev); + void __iomem *base = plat->base; u32 cr1, sr; int ret; dev_dbg(dev, "\n"); - cr1 = readl(priv->base + STM32_SPI_CR1); + cr1 = readl(base + STM32_SPI_CR1); if (!(cr1 & SPI_CR1_SPE)) return; /* Wait on EOT or suspend the flow */ - ret = readl_poll_timeout(priv->base + STM32_SPI_SR, sr, + ret = readl_poll_timeout(base + STM32_SPI_SR, sr, !(sr & SPI_SR_EOT), 100000); if (ret < 0) { if (cr1 & SPI_CR1_CSTART) { - writel(cr1 | SPI_CR1_CSUSP, priv->base + STM32_SPI_CR1); - if (readl_poll_timeout(priv->base + STM32_SPI_SR, + writel(cr1 | SPI_CR1_CSUSP, base + STM32_SPI_CR1); + if (readl_poll_timeout(base + STM32_SPI_SR, sr, !(sr & SPI_SR_SUSP), 100000) < 0) dev_err(dev, "Suspend request timeout\n"); @@ -251,11 +264,12 @@ static void stm32_spi_stopxfer(struct udevice *dev) } /* clear status flags */ - setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL); + setbits_le32(base + STM32_SPI_IFCR, SPI_IFCR_ALL); } static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable) { + struct stm32_spi_plat *plat = dev_get_plat(dev); struct stm32_spi_priv *priv = dev_get_priv(dev); dev_dbg(dev, "cs=%d enable=%d\n", cs, enable); @@ -263,18 +277,20 @@ static int stm32_spi_set_cs(struct udevice *dev, unsigned int cs, bool enable) if (cs >= MAX_CS_COUNT) return -ENODEV; - if (!dm_gpio_is_valid(&priv->cs_gpios[cs])) + if (!dm_gpio_is_valid(&plat->cs_gpios[cs])) return -EINVAL; if (priv->cs_high) enable = !enable; - return dm_gpio_set_value(&priv->cs_gpios[cs], enable ? 1 : 0); + return dm_gpio_set_value(&plat->cs_gpios[cs], enable ? 1 : 0); } static int stm32_spi_set_mode(struct udevice *bus, uint mode) { struct stm32_spi_priv *priv = dev_get_priv(bus); + struct stm32_spi_plat *plat = dev_get_plat(bus); + void __iomem *base = plat->base; u32 cfg2_clrb = 0, cfg2_setb = 0; dev_dbg(bus, "mode=%d\n", mode); @@ -295,7 +311,7 @@ static int stm32_spi_set_mode(struct udevice *bus, uint mode) cfg2_clrb |= SPI_CFG2_LSBFRST; if (cfg2_clrb || cfg2_setb) - clrsetbits_le32(priv->base + STM32_SPI_CFG2, + clrsetbits_le32(base + STM32_SPI_CFG2, cfg2_clrb, cfg2_setb); if (mode & SPI_CS_HIGH) @@ -308,6 +324,8 @@ static int stm32_spi_set_mode(struct udevice *bus, uint mode) static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len) { struct stm32_spi_priv *priv = dev_get_priv(dev); + struct stm32_spi_plat *plat = dev_get_plat(dev); + void __iomem *base = plat->base; u32 fthlv, half_fifo; /* data packet should not exceed 1/2 of fifo space */ @@ -321,7 +339,7 @@ static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len) if (!fthlv) fthlv = 1; - clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_FTHLV, + clrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_FTHLV, (fthlv - 1) << SPI_CFG1_FTHLV_SHIFT); return 0; @@ -330,6 +348,8 @@ static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len) static int stm32_spi_set_speed(struct udevice *bus, uint hz) { struct stm32_spi_priv *priv = dev_get_priv(bus); + struct stm32_spi_plat *plat = dev_get_plat(bus); + void __iomem *base = plat->base; u32 mbrdiv; long div; @@ -353,7 +373,7 @@ static int stm32_spi_set_speed(struct udevice *bus, uint hz) if (!mbrdiv) return -EINVAL; - clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_MBR, + clrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_MBR, (mbrdiv - 1) << SPI_CFG1_MBR_SHIFT); priv->cur_hz = hz; @@ -367,6 +387,8 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen, struct udevice *bus = dev_get_parent(slave); struct dm_spi_slave_plat *slave_plat; struct stm32_spi_priv *priv = dev_get_priv(bus); + struct stm32_spi_plat *plat = dev_get_plat(bus); + void __iomem *base = plat->base; u32 sr; u32 ifcr = 0; u32 xferlen; @@ -376,7 +398,7 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen, xferlen = bitlen / 8; if (xferlen <= SPI_CR2_TSIZE) - writel(xferlen, priv->base + STM32_SPI_CR2); + writel(xferlen, base + STM32_SPI_CR2); else return -EMSGSIZE; @@ -396,15 +418,15 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen, priv->cur_xferlen = xferlen; /* Disable the SPI hardware to unlock CFG1/CFG2 registers */ - stm32_spi_disable(priv); + stm32_spi_disable(base); - clrsetbits_le32(priv->base + STM32_SPI_CFG2, SPI_CFG2_COMM, + clrsetbits_le32(base + STM32_SPI_CFG2, SPI_CFG2_COMM, mode << SPI_CFG2_COMM_SHIFT); stm32_spi_set_fthlv(bus, xferlen); /* Enable the SPI hardware */ - stm32_spi_enable(priv); + stm32_spi_enable(base); } dev_dbg(bus, "priv->tx_len=%d priv->rx_len=%d\n", @@ -416,12 +438,12 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen, /* Be sure to have data in fifo before starting data transfer */ if (priv->tx_buf) - stm32_spi_write_txfifo(priv); + stm32_spi_write_txfifo(bus); - setbits_le32(priv->base + STM32_SPI_CR1, SPI_CR1_CSTART); + setbits_le32(base + STM32_SPI_CR1, SPI_CR1_CSTART); while (1) { - sr = readl(priv->base + STM32_SPI_SR); + sr = readl(base + STM32_SPI_SR); if (sr & SPI_SR_OVR) { dev_err(bus, "Overrun: RX data lost\n"); @@ -433,7 +455,7 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen, dev_warn(bus, "System too slow is limiting data throughput\n"); if (priv->rx_buf && priv->rx_len > 0) - stm32_spi_read_rxfifo(priv); + stm32_spi_read_rxfifo(bus); ifcr |= SPI_SR_SUSP; } @@ -443,23 +465,23 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen, if (sr & SPI_SR_TXP) if (priv->tx_buf && priv->tx_len > 0) - stm32_spi_write_txfifo(priv); + stm32_spi_write_txfifo(bus); if (sr & SPI_SR_RXP) if (priv->rx_buf && priv->rx_len > 0) - stm32_spi_read_rxfifo(priv); + stm32_spi_read_rxfifo(bus); if (sr & SPI_SR_EOT) { if (priv->rx_buf && priv->rx_len > 0) - stm32_spi_read_rxfifo(priv); + stm32_spi_read_rxfifo(bus); break; } - writel(ifcr, priv->base + STM32_SPI_IFCR); + writel(ifcr, base + STM32_SPI_IFCR); } /* clear status flags */ - setbits_le32(priv->base + STM32_SPI_IFCR, SPI_IFCR_ALL); + setbits_le32(base + STM32_SPI_IFCR, SPI_IFCR_ALL); stm32_spi_stopxfer(bus); if (flags & SPI_XFER_END) @@ -470,42 +492,72 @@ static int stm32_spi_xfer(struct udevice *slave, unsigned int bitlen, static int stm32_spi_get_fifo_size(struct udevice *dev) { - struct stm32_spi_priv *priv = dev_get_priv(dev); + struct stm32_spi_plat *plat = dev_get_plat(dev); + void __iomem *base = plat->base; u32 count = 0; - stm32_spi_enable(priv); + stm32_spi_enable(base); - while (readl(priv->base + STM32_SPI_SR) & SPI_SR_TXP) - writeb(++count, priv->base + STM32_SPI_TXDR); + while (readl(base + STM32_SPI_SR) & SPI_SR_TXP) + writeb(++count, base + STM32_SPI_TXDR); - stm32_spi_disable(priv); + stm32_spi_disable(base); dev_dbg(dev, "%d x 8-bit fifo size\n", count); return count; } +static int stm32_spi_of_to_plat(struct udevice *dev) +{ + struct stm32_spi_plat *plat = dev_get_plat(dev); + int ret; + + plat->base = dev_read_addr_ptr(dev); + if (!plat->base) { + dev_err(dev, "can't get registers base address\n"); + return -ENOENT; + } + + ret = clk_get_by_index(dev, 0, &plat->clk); + if (ret < 0) + return ret; + + ret = reset_get_by_index(dev, 0, &plat->rst_ctl); + if (ret < 0) + goto clk_err; + + ret = gpio_request_list_by_name(dev, "cs-gpios", plat->cs_gpios, + ARRAY_SIZE(plat->cs_gpios), 0); + if (ret < 0) { + dev_err(dev, "Can't get %s cs gpios: %d", dev->name, ret); + ret = -ENOENT; + goto clk_err; + } + + return 0; + +clk_err: + clk_free(&plat->clk); + + return ret; +} + static int stm32_spi_probe(struct udevice *dev) { + struct stm32_spi_plat *plat = dev_get_plat(dev); struct stm32_spi_priv *priv = dev_get_priv(dev); + void __iomem *base = plat->base; unsigned long clk_rate; int ret; unsigned int i; - priv->base = dev_remap_addr(dev); - if (!priv->base) - return -EINVAL; - /* enable clock */ - ret = clk_get_by_index(dev, 0, &priv->clk); + ret = clk_enable(&plat->clk); if (ret < 0) return ret; - ret = clk_enable(&priv->clk); - if (ret < 0) - return ret; - - clk_rate = clk_get_rate(&priv->clk); + clk_rate = clk_get_rate(&plat->clk); if (!clk_rate) { ret = -EINVAL; goto clk_err; @@ -514,46 +566,34 @@ static int stm32_spi_probe(struct udevice *dev) priv->bus_clk_rate = clk_rate; /* perform reset */ - ret = reset_get_by_index(dev, 0, &priv->rst_ctl); - if (ret < 0) - goto clk_err; - - reset_assert(&priv->rst_ctl); + reset_assert(&plat->rst_ctl); udelay(2); - reset_deassert(&priv->rst_ctl); - - ret = gpio_request_list_by_name(dev, "cs-gpios", priv->cs_gpios, - ARRAY_SIZE(priv->cs_gpios), 0); - if (ret < 0) { - dev_err(dev, "Can't get cs gpios: %d", ret); - goto reset_err; - } + reset_deassert(&plat->rst_ctl); priv->fifo_size = stm32_spi_get_fifo_size(dev); - priv->cur_mode = SPI_FULL_DUPLEX; priv->cur_xferlen = 0; priv->cur_bpw = SPI_DEFAULT_WORDLEN; - clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_DSIZE, + clrsetbits_le32(base + STM32_SPI_CFG1, SPI_CFG1_DSIZE, priv->cur_bpw - 1); - for (i = 0; i < ARRAY_SIZE(priv->cs_gpios); i++) { - if (!dm_gpio_is_valid(&priv->cs_gpios[i])) + for (i = 0; i < ARRAY_SIZE(plat->cs_gpios); i++) { + if (!dm_gpio_is_valid(&plat->cs_gpios[i])) continue; - dm_gpio_set_dir_flags(&priv->cs_gpios[i], + dm_gpio_set_dir_flags(&plat->cs_gpios[i], GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); } /* Ensure I2SMOD bit is kept cleared */ - clrbits_le32(priv->base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD); + clrbits_le32(base + STM32_SPI_I2SCFGR, SPI_I2SCFGR_I2SMOD); /* * - SS input value high * - transmitter half duplex direction * - automatic communication suspend when RX-Fifo is full */ - setbits_le32(priv->base + STM32_SPI_CR1, + setbits_le32(base + STM32_SPI_CR1, SPI_CR1_SSI | SPI_CR1_HDDIR | SPI_CR1_MASRX); /* @@ -562,40 +602,38 @@ static int stm32_spi_probe(struct udevice *dev) * SS input value is determined by the SSI bit * - keep control of all associated GPIOs */ - setbits_le32(priv->base + STM32_SPI_CFG2, + setbits_le32(base + STM32_SPI_CFG2, SPI_CFG2_MASTER | SPI_CFG2_SSM | SPI_CFG2_AFCNTR); return 0; -reset_err: - reset_free(&priv->rst_ctl); - clk_err: - clk_disable(&priv->clk); - clk_free(&priv->clk); + clk_disable(&plat->clk); + clk_free(&plat->clk); return ret; }; static int stm32_spi_remove(struct udevice *dev) { - struct stm32_spi_priv *priv = dev_get_priv(dev); + struct stm32_spi_plat *plat = dev_get_plat(dev); + void __iomem *base = plat->base; int ret; stm32_spi_stopxfer(dev); - stm32_spi_disable(priv); + stm32_spi_disable(base); - ret = reset_assert(&priv->rst_ctl); + ret = reset_assert(&plat->rst_ctl); if (ret < 0) return ret; - reset_free(&priv->rst_ctl); + reset_free(&plat->rst_ctl); - ret = clk_disable(&priv->clk); + ret = clk_disable(&plat->clk); if (ret < 0) return ret; - clk_free(&priv->clk); + clk_free(&plat->clk); return ret; }; @@ -618,7 +656,9 @@ U_BOOT_DRIVER(stm32_spi) = { .id = UCLASS_SPI, .of_match = stm32_spi_ids, .ops = &stm32_spi_ops, - .priv_auto = sizeof(struct stm32_spi_priv), + .of_to_plat = stm32_spi_of_to_plat, + .plat_auto = sizeof(struct stm32_spi_plat), + .priv_auto = sizeof(struct stm32_spi_priv), .probe = stm32_spi_probe, .remove = stm32_spi_remove, }; -- 2.17.1

3 2

[PATCH 1/2] phy: stm32-usbphyc: use connector for vbus-supply with phy-stm32-usbphyc
by Patrick Delaunay 08 Oct '21

08 Oct '21

The vbus-supply is an optional property of sub-node connector node. and no more in the usb phyc node (in first proposed binding). This regulator for USB VBUS may be needed for host mode. See the latest kernel binding for details in Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml. usbphyc_port0: usb-phy@0 { reg = <0>; phy-supply = <&vdd_usb>; #phy-cells = <0>; connector { compatible = "usb-a-connector"; vbus-supply = <&vbus_sw>; }; }; Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- drivers/phy/phy-stm32-usbphyc.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/phy/phy-stm32-usbphyc.c b/drivers/phy/phy-stm32-usbphyc.c index 02d859a039..c206efd28d 100644 --- a/drivers/phy/phy-stm32-usbphyc.c +++ b/drivers/phy/phy-stm32-usbphyc.c @@ -339,7 +339,7 @@ static int stm32_usbphyc_probe(struct udevice *dev) { struct stm32_usbphyc *usbphyc = dev_get_priv(dev); struct reset_ctl reset; - ofnode node; + ofnode node, connector; int i, ret; usbphyc->base = dev_read_addr(dev); @@ -395,10 +395,12 @@ static int stm32_usbphyc_probe(struct udevice *dev) return ret; } - ret = stm32_usbphyc_get_regulator(node, "vbus-supply", - &usbphyc_phy->vbus); - if (ret) - usbphyc_phy->vbus = NULL; + usbphyc_phy->vbus = NULL; + connector = ofnode_find_subnode(node, "connector"); + if (ofnode_valid(connector)) { + ret = stm32_usbphyc_get_regulator(connector, "vbus-supply", + &usbphyc_phy->vbus); + } node = dev_read_next_subnode(node); } -- 2.25.1

2 5

[PATCH 1/2] arm: stm32: Disable ATAGs support
by Patrick Delaunay 08 Oct '21

08 Oct '21

These platforms never had to support an ATAGs-based Linux Kernel, so remove the options. Cc: Marek Vasut <marex(a)denx.de> Signed-off-by: Tom Rini <trini(a)konsulko.com> Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- Hi, this patch is a rebased version of the STM32 part [1] of Tom's patchset [2]. I also update the new file include/configs/stm32h750-art-pi.h [1] [13/13] arm: stm32: Disable ATAGs support https://patchwork.ozlabs.org/project/uboot/patch/20210204022415.20589-13-tr… [2] arm: nanopi2: Remove unused code https://patchwork.ozlabs.org/project/uboot/list/?series=227910&state=* Patrick include/configs/stm32f429-discovery.h | 5 ----- include/configs/stm32f429-evaluation.h | 5 ----- include/configs/stm32f469-discovery.h | 5 ----- include/configs/stm32f746-disco.h | 5 ----- include/configs/stm32h743-disco.h | 5 ----- include/configs/stm32h743-eval.h | 5 ----- include/configs/stm32h750-art-pi.h | 5 ----- include/configs/stm32mp1.h | 5 ----- 8 files changed, 40 deletions(-) diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 9d029fbcc6..dbbce49475 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -27,11 +27,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_MALLOC_LEN (2 << 20) diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h index fefdb2dd15..29a41e8067 100644 --- a/include/configs/stm32f429-evaluation.h +++ b/include/configs/stm32f429-evaluation.h @@ -29,11 +29,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h index ba9f05a61b..b9b932c651 100644 --- a/include/configs/stm32f469-discovery.h +++ b/include/configs/stm32f469-discovery.h @@ -29,11 +29,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 08d050adfa..b72b989c2c 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -36,11 +36,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h index 6e10dbdfe9..e5bb08eec7 100644 --- a/include/configs/stm32h743-disco.h +++ b/include/configs/stm32h743-disco.h @@ -24,11 +24,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h index 268d39c7ad..89169f85d5 100644 --- a/include/configs/stm32h743-eval.h +++ b/include/configs/stm32h743-eval.h @@ -24,11 +24,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) diff --git a/include/configs/stm32h750-art-pi.h b/include/configs/stm32h750-art-pi.h index 3fd5461167..a9006e224a 100644 --- a/include/configs/stm32h750-art-pi.h +++ b/include/configs/stm32h750-art-pi.h @@ -24,11 +24,6 @@ #define CONFIG_SYS_HZ_CLOCK 1000000 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index b372838be8..fb4e4fb0bc 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -33,11 +33,6 @@ #define CONFIG_LOADADDR 0xc2000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* ATAGs */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - /* * For booting Linux, use the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. -- 2.25.1

5 8