August 2021 - U-Boot

[PATCH 0/4] Add octal DTR support for Macronix flash
by JaimeLiao 23 Aug '21

23 Aug '21

This series add support for Macronix octal DTR flash, add second time Softreset with "INVERT" command extension type and follow linux kernel to enable 4byte opcode when possible. JaimeLiao (4): mtd: spi-nor: macronix: add support for Macronix octaflash mtd: spi-nor-core: Adding different type of command extension in Soft Reset mtd: spi-nor-core: set 4byte opcode when possible mtd: spi-nor-core: Add support for Macronix Octal flash drivers/mtd/spi/spi-nor-core.c | 109 +++++++++++++++++++++++++++++++++ drivers/mtd/spi/spi-nor-ids.c | 22 ++++++- include/linux/mtd/spi-nor.h | 13 +++- 3 files changed, 141 insertions(+), 3 deletions(-) -- 2.17.1

3 6

[PATCH] display_options: Do not use %llu in print_size
by Matwey V. Kornilov 22 Aug '21

22 Aug '21

tiny-printf variant doesn't know how to handle %llu format string, but both tiny-printf and print_size can meet in SPL when TFTP is used to obtain main u-boot image. This is known to lead to critical boot issue at AM335x platform when printf is catched in infinite loop. To avoid such issues and make print_size function tiny-printf friendly, use %u instead of %luu. Note, that the size value is guaranteed to be less than 1024 in this conditional branch, so the cast to unsigned int is safe. Signed-off-by: Matwey V. Kornilov <matwey.kornilov(a)gmail.com> --- lib/display_options.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/lib/display_options.c b/lib/display_options.c index c08a87e316..4da1f5244f 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -107,7 +107,12 @@ void print_size(uint64_t size, const char *s) } if (!c) { - printf("%llu Bytes%s", size, s); + /* + * SPL tiny-printf is not capable for printing uint64_t. + * We have just checked that the size is small enought to fit + * unsigned int safely. + */ + printf("%u Bytes%s", (unsigned int)size, s); return; } -- 2.31.1

3 2

[PATCH] tiny-printf: Handle %pM format when CONFIG_SPL_NET_SUPPORT is enabled
by Matwey V. Kornilov 22 Aug '21

22 Aug '21

%pM format string is used to print MAC-address and this is required while SPL network boot. This patch fixes the SPL boot issues like the following: Trying to boot from USB eth ## Error: flags type check failure for "ethaddr" <= "40309614M" (type: m) ## Error inserting "ethaddr" variable, errno=1 eth0: eth_cpsw## Error: flags type check failure for "eth1addr" <= "81f01114M" (type: m) ## Error inserting "eth1addr" variable, errno=1 , eth1: usb_ether eth_cpsw Waiting for PHY auto negotiation to complete......... TIMEOUT ! Problem booting with BOOTP SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### Signed-off-by: Matwey V. Kornilov <matwey.kornilov(a)gmail.com> --- lib/tiny-printf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/tiny-printf.c b/lib/tiny-printf.c index 8fc7e48d99..0b2fabf118 100644 --- a/lib/tiny-printf.c +++ b/lib/tiny-printf.c @@ -269,7 +269,7 @@ static int _vprintf(struct printf_info *info, const char *fmt, va_list va) } break; case 'p': -#ifdef DEBUG +#if IS_ENABLED(CONFIG_SPL_NET_SUPPORT) || defined(DEBUG) pointer(info, fmt, va_arg(va, void *)); /* * Skip this because it pulls in _ctype which is -- 2.31.1

3 4

[PATCH v4] Fix flashing of eMMC user area with Fastboot
by Oleh Kravchenko 22 Aug '21

22 Aug '21

'gpt' and 'mmc0' fastboot partitions have been treated as the same device, but it is wrong. Fill disk_partition structure with eMMC user partition info to properly flash data. Signed-off-by: Oleh Kravchenko <oleg(a)kaa.org.ua> Cc: Pantelis Antoniou <panto(a)antoniou-consulting.com> Cc: Marek Vasut <marex(a)denx.de> Cc: Sean Anderson <sean.anderson(a)seco.com> Cc: Tom Rini <trini(a)konsulko.com> --- Changes for v2: - code cleanup; Changes for v3: - QA passed at https://github.com/u-boot/u-boot/pull/75; Changes for v4: - fixed ugly code; - QA passed at https://github.com/u-boot/u-boot/pull/75. drivers/fastboot/fb_mmc.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c index 2f3837e559..a009863e89 100644 --- a/drivers/fastboot/fb_mmc.c +++ b/drivers/fastboot/fb_mmc.c @@ -512,7 +512,7 @@ void fastboot_mmc_flash_write(const char *cmd, void *download_buffer, u32 download_bytes, char *response) { struct blk_desc *dev_desc; - struct disk_partition info; + struct disk_partition info = {0}; #ifdef CONFIG_FASTBOOT_MMC_BOOT_SUPPORT if (strcmp(cmd, CONFIG_FASTBOOT_MMC_BOOT1_NAME) == 0) { @@ -532,12 +532,7 @@ void fastboot_mmc_flash_write(const char *cmd, void *download_buffer, #endif #if CONFIG_IS_ENABLED(EFI_PARTITION) -#ifndef CONFIG_FASTBOOT_MMC_USER_SUPPORT if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0) { -#else - if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0 || - strcmp(cmd, CONFIG_FASTBOOT_MMC_USER_NAME) == 0) { -#endif dev_desc = fastboot_mmc_get_dev(response); if (!dev_desc) return; @@ -599,7 +594,20 @@ void fastboot_mmc_flash_write(const char *cmd, void *download_buffer, } #endif - if (fastboot_mmc_get_part_info(cmd, &dev_desc, &info, response) < 0) +#if CONFIG_IS_ENABLED(FASTBOOT_MMC_USER_SUPPORT) + if (strcmp(cmd, CONFIG_FASTBOOT_MMC_USER_NAME) == 0) { + dev_desc = fastboot_mmc_get_dev(response); + if (!dev_desc) + return; + + strlcpy((char *)&info.name, cmd, sizeof(info.name)); + info.size = dev_desc->lba; + info.blksz = dev_desc->blksz; + } +#endif + + if (!info.name[0] && + fastboot_mmc_get_part_info(cmd, &dev_desc, &info, response) < 0) return; if (is_sparse_image(download_buffer)) { -- 2.26.3

3 7

[PATCH v2] Fix flash and erase of eMMC Boot2 with Fastboot
by Oleh Kravchenko 22 Aug '21

22 Aug '21

The current U-Boot version has the next matches for boot partitions: > mmc0boot0 to EMMC_BOOT1 > mmc0boot1 to EMMC_BOOT1 (should be EMMC_BOOT2) This patch fixes a typo for the boot partition number. Signed-off-by: Oleh Kravchenko <oleg(a)kaa.org.ua> Cc: Pantelis Antoniou <panto(a)antoniou-consulting.com> Cc: Marek Vasut <marex(a)denx.de> --- Changes for v2: - updated commit message - CI https://github.com/u-boot/u-boot/pull/76 drivers/fastboot/fb_mmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c index 2f3837e559..2326067882 100644 --- a/drivers/fastboot/fb_mmc.c +++ b/drivers/fastboot/fb_mmc.c @@ -525,7 +525,7 @@ void fastboot_mmc_flash_write(const char *cmd, void *download_buffer, if (strcmp(cmd, CONFIG_FASTBOOT_MMC_BOOT2_NAME) == 0) { dev_desc = fastboot_mmc_get_dev(response); if (dev_desc) - fb_mmc_boot_ops(dev_desc, download_buffer, 1, + fb_mmc_boot_ops(dev_desc, download_buffer, 2, download_bytes, response); return; } @@ -655,7 +655,7 @@ void fastboot_mmc_erase(const char *cmd, char *response) /* erase EMMC boot2 */ dev_desc = fastboot_mmc_get_dev(response); if (dev_desc) - fb_mmc_boot_ops(dev_desc, NULL, 1, 0, response); + fb_mmc_boot_ops(dev_desc, NULL, 2, 0, response); return; } #endif -- 2.26.3

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[PATCH 1/3] watchdog: Add a driver for the sunxi watchdog
by Samuel Holland 22 Aug '21

22 Aug '21

This driver supports the sun4i/sun6i/sun20i watchdog timers. They have a maximum timeout of 16 seconds. Signed-off-by: Samuel Holland <samuel(a)sholland.org> --- drivers/watchdog/Kconfig | 8 ++ drivers/watchdog/Makefile | 1 + drivers/watchdog/sunxi_wdt.c | 188 +++++++++++++++++++++++++++++++++++ 3 files changed, 197 insertions(+) create mode 100644 drivers/watchdog/sunxi_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index f0ff2612a6b..59112147343 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -27,6 +27,7 @@ config WATCHDOG_TIMEOUT_MSECS default 128000 if ARCH_MX25 || ARCH_MX31 || ARCH_MX5 || ARCH_MX6 default 128000 if ARCH_MX7 || ARCH_VF610 default 30000 if ARCH_SOCFPGA + default 16000 if ARCH_SUNXI default 60000 help Watchdog timeout in msec @@ -241,6 +242,13 @@ config WDT_STM32MP Enable the STM32 watchdog (IWDG) driver. Enable support to configure STM32's on-SoC watchdog. +config WDT_SUNXI + bool "Allwinner sunxi watchdog timer support" + depends on WDT && ARCH_SUNXI + default y + help + Enable support for the watchdog timer in Allwinner sunxi SoCs. + config XILINX_TB_WATCHDOG bool "Xilinx Axi watchdog timer support" depends on WDT diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 5c7ef593fe5..20cf4280db0 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -35,5 +35,6 @@ obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o obj-$(CONFIG_WDT_SP805) += sp805_wdt.o obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o +obj-$(CONFIG_WDT_SUNXI) += sunxi_wdt.o obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o obj-$(CONFIG_WDT_XILINX) += xilinx_wwdt.o diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c new file mode 100644 index 00000000000..b40a1d29caa --- /dev/null +++ b/drivers/watchdog/sunxi_wdt.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Derived from linux/drivers/watchdog/sunxi_wdt.c: + * Copyright (C) 2013 Carlo Caione + * Copyright (C) 2012 Henrik Nordstrom + */ + +#include <dm.h> +#include <wdt.h> +#include <asm/io.h> +#include <linux/delay.h> + +#define MSEC_PER_SEC 1000 + +#define WDT_MAX_TIMEOUT 16 +#define WDT_TIMEOUT_MASK 0xf + +#define WDT_CTRL_RELOAD ((1 << 0) | (0x0a57 << 1)) + +#define WDT_MODE_EN BIT(0) + +struct sunxi_wdt_reg { + u8 wdt_ctrl; + u8 wdt_cfg; + u8 wdt_mode; + u8 wdt_timeout_shift; + u8 wdt_reset_mask; + u8 wdt_reset_val; + u32 wdt_key_val; +}; + +struct sunxi_wdt_priv { + void __iomem *base; + const struct sunxi_wdt_reg *regs; +}; + +/* Map of timeout in seconds to register value */ +static const u8 wdt_timeout_map[1 + WDT_MAX_TIMEOUT] = { + [0] = 0x0, + [1] = 0x1, + [2] = 0x2, + [3] = 0x3, + [4] = 0x4, + [5] = 0x5, + [6] = 0x6, + [7] = 0x7, + [8] = 0x7, + [9] = 0x8, + [10] = 0x8, + [11] = 0x9, + [12] = 0x9, + [13] = 0xa, + [14] = 0xa, + [15] = 0xb, + [16] = 0xb, +}; + +static int sunxi_wdt_reset(struct udevice *dev) +{ + struct sunxi_wdt_priv *priv = dev_get_priv(dev); + const struct sunxi_wdt_reg *regs = priv->regs; + void __iomem *base = priv->base; + + writel(WDT_CTRL_RELOAD, base + regs->wdt_ctrl); + + return 0; +} + +static int sunxi_wdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + struct sunxi_wdt_priv *priv = dev_get_priv(dev); + const struct sunxi_wdt_reg *regs = priv->regs; + void __iomem *base = priv->base; + u32 val; + + timeout /= MSEC_PER_SEC; + if (timeout > WDT_MAX_TIMEOUT) + timeout = WDT_MAX_TIMEOUT; + + /* Set system reset function */ + val = readl(base + regs->wdt_cfg); + val &= ~regs->wdt_reset_mask; + val |= regs->wdt_reset_val; + val |= regs->wdt_key_val; + writel(val, base + regs->wdt_cfg); + + /* Set timeout and enable watchdog */ + val = readl(base + regs->wdt_mode); + val &= ~(WDT_TIMEOUT_MASK << regs->wdt_timeout_shift); + val |= wdt_timeout_map[timeout] << regs->wdt_timeout_shift; + val |= WDT_MODE_EN; + val |= regs->wdt_key_val; + writel(val, base + regs->wdt_mode); + + return sunxi_wdt_reset(dev); +} + +static int sunxi_wdt_stop(struct udevice *dev) +{ + struct sunxi_wdt_priv *priv = dev_get_priv(dev); + const struct sunxi_wdt_reg *regs = priv->regs; + void __iomem *base = priv->base; + + writel(regs->wdt_key_val, base + regs->wdt_mode); + + return 0; +} + +static int sunxi_wdt_expire_now(struct udevice *dev, ulong flags) +{ + int ret; + + ret = sunxi_wdt_start(dev, 0, flags); + if (ret) + return ret; + + mdelay(500); + + return 0; +} + +static const struct wdt_ops sunxi_wdt_ops = { + .reset = sunxi_wdt_reset, + .start = sunxi_wdt_start, + .stop = sunxi_wdt_stop, + .expire_now = sunxi_wdt_expire_now, +}; + +static const struct sunxi_wdt_reg sun4i_wdt_reg = { + .wdt_ctrl = 0x00, + .wdt_cfg = 0x04, + .wdt_mode = 0x04, + .wdt_timeout_shift = 3, + .wdt_reset_mask = 0x2, + .wdt_reset_val = 0x2, +}; + +static const struct sunxi_wdt_reg sun6i_wdt_reg = { + .wdt_ctrl = 0x10, + .wdt_cfg = 0x14, + .wdt_mode = 0x18, + .wdt_timeout_shift = 4, + .wdt_reset_mask = 0x3, + .wdt_reset_val = 0x1, +}; + +static const struct sunxi_wdt_reg sun20i_wdt_reg = { + .wdt_ctrl = 0x10, + .wdt_cfg = 0x14, + .wdt_mode = 0x18, + .wdt_timeout_shift = 4, + .wdt_reset_mask = 0x03, + .wdt_reset_val = 0x01, + .wdt_key_val = 0x16aa0000, +}; + +static const struct udevice_id sunxi_wdt_ids[] = { + { .compatible = "allwinner,sun4i-a10-wdt", .data = (ulong)&sun4i_wdt_reg }, + { .compatible = "allwinner,sun6i-a31-wdt", .data = (ulong)&sun6i_wdt_reg }, + { .compatible = "allwinner,sun20i-d1-wdt", .data = (ulong)&sun20i_wdt_reg }, + { /* sentinel */ } +}; + +static int sunxi_wdt_probe(struct udevice *dev) +{ + struct sunxi_wdt_priv *priv = dev_get_priv(dev); + + priv->base = dev_remap_addr(dev); + if (!priv->base) + return -EINVAL; + + priv->regs = (void *)dev_get_driver_data(dev); + if (!priv->regs) + return -EINVAL; + + sunxi_wdt_stop(dev); + + return 0; +} + +U_BOOT_DRIVER(sunxi_wdt) = { + .name = "sunxi_wdt", + .id = UCLASS_WDT, + .of_match = sunxi_wdt_ids, + .probe = sunxi_wdt_probe, + .priv_auto = sizeof(struct sunxi_wdt_priv), + .ops = &sunxi_wdt_ops, +}; -- 2.31.1

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[PATCH] cmd: ubi: add a command to swap volumes
by Ayoub Zaki 22 Aug '21

22 Aug '21

This commit adds the command ubi swap to swap an ubi volumes. The format of the command is: ubi swap <volume_a> <volume_b>. To enable this command, the option CMD_UBI_SWAPVOL must be selected. Signed-off-by: Ayoub Zaki <ayoub.zaki(a)embexus.com> --- cmd/Kconfig | 8 ++++++++ cmd/ubi.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/cmd/Kconfig b/cmd/Kconfig index f196e6cdd8..c33cfd8439 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -2373,6 +2373,14 @@ config CMD_UBI_RENAME Enable a "ubi" command to rename ubi volume: ubi rename <oldname> <newname> +config CMD_UBI_SWAPVOL + bool "Enable swap volumes" + depends on CMD_UBI + default n + help + Enable a "ubi" command to swap ubi volumes: + ubi swap <volume_a> <volume_b> + config CMD_UBIFS tristate "Enable UBIFS - Unsorted block images filesystem commands" depends on CMD_UBI diff --git a/cmd/ubi.c b/cmd/ubi.c index cb14e3e1e7..1b8197a4e3 100644 --- a/cmd/ubi.c +++ b/cmd/ubi.c @@ -289,6 +289,54 @@ static int ubi_rename_vol(char *oldname, char *newname) return ubi_rename_volumes(ubi, &list); } +static int ubi_swap_vol(char *volume_a, char *volume_b) +{ + struct ubi_volume *vol_a, *vol_b; + struct ubi_rename_entry a, b; + struct ubi_volume_desc desc_a, desc_b; + struct list_head list; + + vol_a = ubi_find_volume(volume_a); + if (!vol_a) { + printf("%s: volume %s doesn't exist\n", __func__, volume_a); + return ENODEV; + } + + vol_b = ubi_find_volume(volume_b); + if (!vol_b) { + printf("%s: volume %s doesn't exist\n", __func__, volume_a); + return ENODEV; + } + + printf("Swap UBI volumes: %s - %s\n", volume_a, volume_b); + + if (ubi->ro_mode) { + printf("%s: ubi device is in read-only mode\n", __func__); + return EROFS; + } + + a.new_name_len = strlen(volume_a); + strcpy(a.new_name, volume_a); + a.remove = 0; + desc_a.vol = vol_b; + desc_a.mode = 0; + a.desc = &desc_a; + + b.new_name_len = strlen(volume_b); + strcpy(b.new_name, volume_b); + b.remove = 0; + desc_b.vol = vol_a; + desc_b.mode = 0; + b.desc = &desc_b; + + INIT_LIST_HEAD(&a.list); + INIT_LIST_HEAD(&b.list); + INIT_LIST_HEAD(&list); + list_add(&a.list, &list); + list_add(&b.list, &list); + return ubi_rename_volumes(ubi, &list); +} + static int ubi_volume_continue_write(char *volume, void *buf, size_t size) { int err = 1; @@ -645,6 +693,9 @@ static int do_ubi(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (IS_ENABLED(CONFIG_CMD_UBI_RENAME) && !strncmp(argv[1], "rename", 6)) return ubi_rename_vol(argv[2], argv[3]); + if (IS_ENABLED(CONFIG_CMD_UBI_SWAPVOL) && !strncmp(argv[1], "swap", 4)) + return ubi_swap_vol(argv[2], argv[3]); + if (strncmp(argv[1], "skipcheck", 9) == 0) { /* E.g., change skip_check flag */ if (argc == 4) { @@ -735,6 +786,9 @@ U_BOOT_CMD( " - Remove volume\n" #if IS_ENABLED(CONFIG_CMD_UBI_RENAME) "ubi rename oldname newname\n" +#endif +#if IS_ENABLED(CONFIG_CMD_UBI_SWAPVOL) + "ubi swap volume_a volume_b\n" #endif "ubi skipcheck volume on/off - Set or clear skip_check flag in volume header\n" "[Legends]\n" -- 2.17.1

2 1

[v6 00/17] Add Intel N5X SoC support
by Siew Chin Lim 20 Aug '21

20 Aug '21

This is the 6th version of patchset to add Intel N5X SoC[1] support. Intel N5X SoC is with a 64-bit quad core ARM Cortex-A53 MPCore hard processor system (HPS). New IPs in N5X are clock manager and DDR subsystem, other IPs have minor changes compared to Agilex. Intel N5X SoC supports legacy boot without ATF for debugging purpose, ATF boot, and ATF boot with VAB enabled. [1]: https://www.intel.com/content/www/us/en/products/programmable/asic/easic-de… Patch status: Have changes: Patch 15 Other patches unchanged. Detail changelog can find in commit message. v5->v6: -------- Patch 15: - Sort the node name in alphanumeric order in socfpga_n5x_socdk-u-boot.dtsi - Remove duplicated qspi node from socfpga_n5x_socdk-u-boot.dtsi, It is defined in socfpga_n5x_socdk.dtsi - Remove the incorrect clkmgr compatible name in socfpga_n5x_socdk.dtsi History: -------- [v1] https://patchwork.ozlabs.org/project/uboot/cover/20210331143908.48211-1-ell… [v2] https://patchwork.ozlabs.org/project/uboot/cover/20210430073814.193576-1-el… [v3] https://patchwork.ozlabs.org/project/uboot/cover/20210613084852.30868-1-ell… [v4] https://patchwork.ozlabs.org/project/uboot/cover/20210712094921.16950-1-ell… [v5] https://patchwork.ozlabs.org/project/uboot/cover/20210809071841.187051-1-el… Siew Chin Lim (14): arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux function arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h arm: socfpga: Add base address for Intel N5X device drivers: clk: Add clock driver for Intel N5X device arm: socfpga: Get clock manager base address for Intel N5X device drivers: clk: Add memory clock driver for Intel N5X device arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.h arm: socfpga: Add clock manager for Intel N5X device arm: socfpga: Changed misc_s10.c to misc_soc64.c arm: socfpga: Add SPL for Intel N5X device board: intel: Add socdk board support for Intel N5X device arm: dts: Add base dtsi and devkit dts for Intel N5X device include: configs: Add Intel N5X device CONFIGs arm: socfpga: Enable Intel N5X device build Tien Fong Chee (3): arm: socfpga: Add handoff data support for Intel N5X device ddr: socfpga: Enable memory test on memory size less than 1GB ddr: altera: Add SDRAM driver for Intel N5X device arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_n5x-u-boot.dtsi | 191 ++ arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 63 + arch/arm/dts/socfpga_n5x_socdk.dts | 122 ++ arch/arm/mach-socfpga/Kconfig | 21 +- arch/arm/mach-socfpga/Makefile | 32 +- arch/arm/mach-socfpga/board.c | 17 +- arch/arm/mach-socfpga/clock_manager_n5x.c | 80 + .../mach/{base_addr_s10.h => base_addr_soc64.h} | 11 +- arch/arm/mach-socfpga/include/mach/clock_manager.h | 3 + .../include/mach/clock_manager_agilex.h | 2 - .../include/mach/clock_manager_arria10.h | 1 - .../mach-socfpga/include/mach/clock_manager_gen5.h | 1 - .../mach-socfpga/include/mach/clock_manager_n5x.h | 12 + .../mach-socfpga/include/mach/clock_manager_s10.h | 1 - arch/arm/mach-socfpga/include/mach/firewall.h | 6 + arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 38 +- .../include/mach/system_manager_soc64.h | 10 +- arch/arm/mach-socfpga/misc.c | 3 + arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 +- arch/arm/mach-socfpga/spl_n5x.c | 94 + arch/arm/mach-socfpga/system_manager_soc64.c | 18 +- arch/arm/mach-socfpga/wrap_handoff_soc64.c | 132 +- board/intel/n5x-socdk/MAINTAINERS | 7 + board/intel/n5x-socdk/Makefile | 7 + board/intel/n5x-socdk/socfpga.c | 7 + configs/socfpga_agilex_atf_defconfig | 2 +- ...lex_atf_defconfig => socfpga_n5x_atf_defconfig} | 13 +- ..._agilex_atf_defconfig => socfpga_n5x_defconfig} | 28 +- ...lex_atf_defconfig => socfpga_n5x_vab_defconfig} | 14 +- configs/socfpga_stratix10_atf_defconfig | 2 +- drivers/clk/altera/Makefile | 4 +- drivers/clk/altera/clk-mem-n5x.c | 136 ++ drivers/clk/altera/clk-mem-n5x.h | 84 + drivers/clk/altera/clk-n5x.c | 489 +++++ drivers/clk/altera/clk-n5x.h | 217 ++ drivers/ddr/altera/Makefile | 3 +- drivers/ddr/altera/sdram_n5x.c | 2298 ++++++++++++++++++++ drivers/ddr/altera/sdram_soc64.c | 94 +- drivers/ddr/altera/sdram_soc64.h | 1 + include/configs/socfpga_n5x_socdk.h | 45 + include/configs/socfpga_soc64_common.h | 2 +- include/dt-bindings/clock/n5x-clock.h | 71 + 43 files changed, 4276 insertions(+), 119 deletions(-) create mode 100644 arch/arm/dts/socfpga_n5x-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_n5x_socdk.dts create mode 100644 arch/arm/mach-socfpga/clock_manager_n5x.c rename arch/arm/mach-socfpga/include/mach/{base_addr_s10.h => base_addr_soc64.h} (85%) create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h rename arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} (100%) create mode 100644 arch/arm/mach-socfpga/spl_n5x.c create mode 100644 board/intel/n5x-socdk/MAINTAINERS create mode 100644 board/intel/n5x-socdk/Makefile create mode 100644 board/intel/n5x-socdk/socfpga.c copy configs/{socfpga_agilex_atf_defconfig => socfpga_n5x_atf_defconfig} (83%) copy configs/{socfpga_agilex_atf_defconfig => socfpga_n5x_defconfig} (64%) copy configs/{socfpga_agilex_atf_defconfig => socfpga_n5x_vab_defconfig} (82%) create mode 100644 drivers/clk/altera/clk-mem-n5x.c create mode 100644 drivers/clk/altera/clk-mem-n5x.h create mode 100644 drivers/clk/altera/clk-n5x.c create mode 100644 drivers/clk/altera/clk-n5x.h create mode 100644 drivers/ddr/altera/sdram_n5x.c create mode 100644 include/configs/socfpga_n5x_socdk.h create mode 100644 include/dt-bindings/clock/n5x-clock.h -- 2.13.0

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[RFC PATCH 0/6] Add C tests for hush
by Francis Laniel 20 Aug '21

20 Aug '21

Hi everyone. First, I hope you are fine and the same for your relatives. This series introduces C tests for hush. The main goal of these tests is to act as regression tests in case of hush being modified. During their writings some bugs were found, unfortunately I did not write patches to fix them. First, I think these bugs were present in Busybox when hush was taken from. Also, as the whole U-Boot board scripts seem to work with these bugs maybe correcting them can lead to breaking things somewhere... This is why I marked this series as RFC as I would like the hear the opinion of the community on this problem. Regarding the series, first commit introduces a new subcommand to ut: ut hush. Then, others add tests for the following: * if test condition: All these tests were taken from test_hush_if_test.py which was then removed. * variable expansion: These tests ensures variable expansion is correct. While writing them a bug was found in hush where the following: foo='bar "quux' echo $foo prints: bar quux instead of: bar "quux * commands lists: These tests test several command separated by ';', "&&" and "||". Here also, some bugs were found, indeed the following: false && false || true returns 0 in actual (2021) hush's Busybox, while it returns 1 in U-Boot. * loops: This test is quite simple as we do not have math support in U-Boot, this can be tricky to heavily test while and until loops. To conclude, here is this series diffstat: Francis Laniel (6): test: Add framework to test hush behavior. test: hush: Test hush if/else. test/py: hush_if_test: Remove the test file. test: hush: Test hush variable expansion. test: hush: Test hush commands list. test: hush: Test hush loops. include/test/hush.h | 15 ++ include/test/suites.h | 1 + test/Makefile | 3 + test/cmd_ut.c | 6 + test/hush/Makefile | 10 + test/hush/cmd_ut_hush.c | 20 ++ test/hush/dollar.c | 188 ++++++++++++++++++ test/hush/if.c | 308 +++++++++++++++++++++++++++++ test/hush/list.c | 79 ++++++++ test/hush/loop.c | 64 ++++++ test/py/tests/test_hush_if_test.py | 192 ------------------ 11 files changed, 694 insertions(+), 192 deletions(-) create mode 100644 include/test/hush.h create mode 100644 test/hush/Makefile create mode 100644 test/hush/cmd_ut_hush.c create mode 100644 test/hush/dollar.c create mode 100644 test/hush/if.c create mode 100644 test/hush/list.c create mode 100644 test/hush/loop.c delete mode 100644 test/py/tests/test_hush_if_test.py Best regards. -- 2.25.1

1 6

[PATCH] configs: ls1046aqds: Configure environment related configs
by Kuldeep Singh 20 Aug '21

20 Aug '21

LS1046A-QDS board requires updation in few environment configs in TFA defconfigs of the board. Following are the changes: - Update CONFIG_ENV_ADDR - Update CONFIG_ENV_SECT_SIZE - Enable CONFIG_SYS_RELOC_GD_ENV_ADDR Signed-off-by: Kuldeep Singh <kuldeep.singh(a)nxp.com> --- configs/ls1046aqds_tfa_defconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 8ae5159f42..1c228f370a 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -7,7 +7,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 -CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-qds-duart" CONFIG_FSL_USE_PCA9547_MUX=y @@ -45,7 +45,8 @@ CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_BUS=y CONFIG_ENV_SPI_BUS=0 -CONFIG_ENV_ADDR=0x40500000 +CONFIG_ENV_ADDR=0x60500000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y CONFIG_FSL_CAAM=y -- 2.25.1

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