August 2021 - U-Boot

[PATCH v2 0/3] riscv: enable SBI system reset
by Heinrich Schuchardt 02 Aug '21

02 Aug '21

The purpose of this series is to provide the UEFI ResetSystem() service at runtime on RISC-V systems. With SBI v0.3 a system reset extension is available. This allows to implement reboot and poweroff in U-Boot in a system independent way. * Provide a system reset driver using the system reset extension. v2: correct constants in patch 1 which were copied from incorrect Linux avoid a superfluous check in the sysreset driver drop K210 specific patches which need further work Heinrich Schuchardt (3): risv: add missing SBI extension definitions cmd/sbi: use constants instead of numerical values sysreset: provide SBI based sysreset driver MAINTAINERS | 1 + arch/riscv/cpu/cpu.c | 13 ++++- arch/riscv/include/asm/sbi.h | 37 ++++++++++++- arch/riscv/lib/sbi.c | 21 ++++++-- cmd/riscv/sbi.c | 30 +++++------ drivers/sysreset/Kconfig | 11 ++++ drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_sbi.c | 96 +++++++++++++++++++++++++++++++++ lib/efi_loader/Kconfig | 2 +- 9 files changed, 189 insertions(+), 23 deletions(-) create mode 100644 drivers/sysreset/sysreset_sbi.c -- 2.30.2

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[PATCH v2] armv8: fsl : create bootcmd and mcinitcmd as per boot source
by Wasim Khan 02 Aug '21

02 Aug '21

From: Wasim Khan <wasim.khan(a)nxp.com> NXP platforms expect custom bootcmd and mcinitcmd to be updated as per boot source with default environment. Check env variable fsl_bootcmd_mcinitcmd_set to prepare bootcmd and mcinitcmd Fixes: cbf77d201870 (armv8: fsl-layerscape: Fix automatic setting of bootmcd with TF-A) Signed-off-by: Wasim Khan <wasim.khan(a)nxp.com> --- Changes in v2: Updated commit description as per review comments Earlier: Fixes: cbf77d2018 Now : Fixes: cbf77d201870 (armv8: fsl-layerscape: Fix automatic setting of bootmcd with TF-A arch/arm/cpu/armv8/fsl-layerscape/soc.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 0562d28705..a77128b424 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -953,12 +953,15 @@ int board_late_init(void) #endif #ifdef CONFIG_TFABOOT /* - * Set bootcmd and mcinitcmd if they don't exist in the environment. + * Set bootcmd and mcinitcmd if "fsl_bootcmd_mcinitcmd_set" does + * not exists in env */ - if (!env_get("bootcmd")) + if (env_get_yesno("fsl_bootcmd_mcinitcmd_set") <= 0) { + // Set bootcmd and mcinitcmd as per boot source fsl_setenv_bootcmd(); - if (!env_get("mcinitcmd")) fsl_setenv_mcinitcmd(); + env_set("fsl_bootcmd_mcinitcmd_set", "y"); + } #endif #ifdef CONFIG_QSPI_AHB_INIT qspi_ahb_init(); -- 2.25.1

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Re: [PATCH] riscv: cpu: fu740: Fix typo of date
by Leo Liang 02 Aug '21

02 Aug '21

On Mon, Aug 02, 2021 at 03:33:17PM +0800, Zong Li wrote: > Fixed the typo of date of copyright declaration. > > Signed-off-by: Zong Li <zong.li(a)sifive.com> > --- > arch/riscv/cpu/fu740/spl.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Leo Yu-Chi Liang <ycliang(a)andestech.com>

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[PATCH 0/3] Convert the Dreamplug Ethernet and SATA to Driver Model.
by Tony Dinh 02 Aug '21

02 Aug '21

- Enable DM SATA, removed IDE driver, add SATA MV driver. - Use Ethernet PHY names from device tree. - Replace the old Ethernet PHY addr lookup with a device tree parsing lookup function. Tony Dinh (3): arm: kirkwood: Dreamplug: Add DM Ethernet and DM SATA configs arm: kirkwood: Dreamplug: Use Ethernet PHY name and address from device tree arm: kirkwood: Dreamplug: Add DM SATA and remove IDE configs board/Marvell/dreamplug/dreamplug.c | 62 ++++++++++++++++++++++------- configs/dreamplug_defconfig | 4 ++ include/configs/dreamplug.h | 12 +++++- 3 files changed, 62 insertions(+), 16 deletions(-) -- 2.20.1

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[PATCH] riscv: cpu: fu740: Fix typo of date
by Zong Li 02 Aug '21

02 Aug '21

Fixed the typo of date of copyright declaration. Signed-off-by: Zong Li <zong.li(a)sifive.com> --- arch/riscv/cpu/fu740/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/cpu/fu740/spl.c b/arch/riscv/cpu/fu740/spl.c index 55e30346ff..c6816e9ed4 100644 --- a/arch/riscv/cpu/fu740/spl.c +++ b/arch/riscv/cpu/fu740/spl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2020-201 SiFive, Inc + * Copyright (C) 2020-2021 SiFive, Inc * Pragnesh Patel <pragnesh.patel(a)sifive.com> */ -- 2.32.0

2 1

[PATCH 1/1] efi_loader: typo cerificate
by Heinrich Schuchardt 02 Aug '21

02 Aug '21

%s/cerificate/certificate/ Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- lib/efi_loader/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index 9b369430e2..08469d9cd9 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -23,7 +23,7 @@ endif ifeq ($(CONFIG_EFI_CAPSULE_AUTHENTICATE),y) EFI_CAPSULE_KEY_PATH := $(subst $\",,$(CONFIG_EFI_CAPSULE_KEY_PATH)) ifeq ("$(wildcard $(EFI_CAPSULE_KEY_PATH))","") -$(error .esl cerificate not found. Configure your CONFIG_EFI_CAPSULE_KEY_PATH) +$(error .esl certificate not found. Configure your CONFIG_EFI_CAPSULE_KEY_PATH) endif endif -- 2.30.2

2 1

[PATCH v2 1/2] x86: fsp: Don't program MTRR for DRAM for FSP1
by Bin Meng 02 Aug '21

02 Aug '21

There are several outstanding issues as to why this does not apply to FSP1: * For FSP1, the system memory and reserved memory used by FSP are already programmed in the MTRR by FSP. * The 'mtrr_top' mistakenly includes TSEG memory range that has the same RES_MEM_RESERVED resource type. Its address is programmed and reported by FSP to be near the top of 4 GiB space, which is not what we want for SDRAM. * The call to mtrr_add_request() is not guaranteed to have its size to be exactly the power of 2. This causes reserved bits of the IA32_MTRR_PHYSMASK register to be written which generates #GP. For FSP2, it seems this is necessary as without this, U-Boot boot process on Chromebook Coral goes very slowly. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- Changes in v2: - Keep programing MTRR to FSP2 only arch/x86/lib/fsp/fsp_dram.c | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c index 8ad9aeedac..2bd408d0c5 100644 --- a/arch/x86/lib/fsp/fsp_dram.c +++ b/arch/x86/lib/fsp/fsp_dram.c @@ -48,12 +48,28 @@ int dram_init_banksize(void) phys_addr_t mtrr_top; phys_addr_t low_end; uint bank; + bool update_mtrr; + + /* + * For FSP1, the system memory and reserved memory used by FSP are + * already programmed in the MTRR by FSP. Also it is observed that + * FSP on Intel Queensbay platform reports the TSEG memory range + * that has the same RES_MEM_RESERVED resource type whose address + * is programmed by FSP to be near the top of 4 GiB space, which is + * not what we want for DRAM. + * + * However it seems FSP2's behavior is different. We need to add the + * DRAM range in MTRR otherwise the boot process goes very slowly, + * which was observed on Chrromebook Coral with FSP2. + */ + update_mtrr = CONFIG_IS_ENABLED(FSP_VERSION2); if (!ll_boot_init()) { gd->bd->bi_dram[0].start = 0; gd->bd->bi_dram[0].size = gd->ram_size; - mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size); + if (update_mtrr) + mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size); return 0; } @@ -76,8 +92,10 @@ int dram_init_banksize(void) } else { gd->bd->bi_dram[bank].start = res_desc->phys_start; gd->bd->bi_dram[bank].size = res_desc->len; - mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start, - res_desc->len); + if (update_mtrr) + mtrr_add_request(MTRR_TYPE_WRBACK, + res_desc->phys_start, + res_desc->len); log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start, gd->bd->bi_dram[bank].size); @@ -92,7 +110,8 @@ int dram_init_banksize(void) * Set up an MTRR to the top of low, reserved memory. This is necessary * for graphics to run at full speed in U-Boot. */ - mtrr_add_request(MTRR_TYPE_WRBACK, 0, mtrr_top); + if (update_mtrr) + mtrr_add_request(MTRR_TYPE_WRBACK, 0, mtrr_top); return 0; } -- 2.25.1

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[PATCH 1/2] x86: queensbay: Optimize disable_igd() a little
by Bin Meng 02 Aug '21

02 Aug '21

Initialize igd and sdvo to NULL so that we don't need to test the return value of dm_pci_bus_find_bdf() later. Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- arch/x86/cpu/queensbay/tnc.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index 782ed863fe..e38c0198e4 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -18,18 +18,15 @@ static int __maybe_unused disable_igd(void) { - struct udevice *igd, *sdvo; + struct udevice *igd = NULL; + struct udevice *sdvo = NULL; int ret; ret = dm_pci_bus_find_bdf(TNC_IGD, &igd); - if (ret) - return ret; if (!igd) return 0; ret = dm_pci_bus_find_bdf(TNC_SDVO, &sdvo); - if (ret) - return ret; if (!sdvo) return 0; -- 2.25.1

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[PATCH 0/7] x86: Various fixes to MTRR and FSP codes
by Bin Meng 02 Aug '21

02 Aug '21

At present Intel Crown Bay does not boot. This was caused by various regression issues introduced when supporting FSP2, and some flaws in MTRR codes. With this series, U-Boot boot again on Intel Crown Bay board. This series is available at u-boot-x86/crownbay for testing. Bin Meng (7): x86: fsp: Don't program MTRR for DRAM x86: mtrr: Do not clear the unused ones in mtrr_commit() x86: mtrr: Skip MSRs that were already programmed in mtrr_commit() x86: mtrr: Abort if requested size is not power of 2 x86: cmd: hob: Fix the command usage and help messages x86: cmd: hob: Fix display of resource type for system memory x86: fsp: Only FSP2 has INIT_PHASE_END_FIRMWARE arch/x86/cpu/mtrr.c | 13 ++++++++----- arch/x86/include/asm/mtrr.h | 7 ++++--- arch/x86/lib/fsp/fsp_common.c | 16 +++++++++------- arch/x86/lib/fsp/fsp_dram.c | 35 ++++++++++------------------------- cmd/x86/hob.c | 9 ++++----- 5 files changed, 35 insertions(+), 45 deletions(-) -- 2.25.1

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[PATCH v5 11/12] vpl: Add Kconfig options for VPL
by Simon Glass 02 Aug '21

02 Aug '21

Add VPL versions of commonly used Kconfig options. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v5: - Rebase this patch on mainline (for GPIO and MISC Kconfig renames) Changes in v4: - Add options for blk, core, misc and tpl also - Add VPL_SIZE_LIMIT Kconfig | 10 ++ common/Kconfig | 67 +++++++++++++ common/spl/Kconfig | 202 +++++++++++++++++++++++++++++++++++++++ drivers/block/Kconfig | 12 +++ drivers/clk/Kconfig | 10 ++ drivers/core/Kconfig | 33 +++++++ drivers/core/Makefile | 2 +- drivers/gpio/Kconfig | 11 +++ drivers/i2c/Kconfig | 11 +++ drivers/misc/Kconfig | 28 ++++++ drivers/pinctrl/Kconfig | 18 +++- drivers/rtc/Kconfig | 9 ++ drivers/serial/Kconfig | 20 ++++ drivers/sysreset/Kconfig | 10 ++ drivers/timer/Kconfig | 10 ++ drivers/tpm/Kconfig | 30 ++++++ dts/Kconfig | 9 ++ lib/Kconfig | 62 ++++++++++++ 18 files changed, 551 insertions(+), 3 deletions(-) diff --git a/Kconfig b/Kconfig index 76c0cdacb0c..2d73997702f 100644 --- a/Kconfig +++ b/Kconfig @@ -279,6 +279,16 @@ config TPL_SYS_MALLOC_F_LEN particular needs this to operate, so that it can allocate the initial serial device and any others that are needed. +config VPL_SYS_MALLOC_F_LEN + hex "Size of malloc() pool in VPL before relocation" + depends on SYS_MALLOC_F && VPL + default SYS_MALLOC_F_LEN + help + Before relocation, memory is very limited on many platforms. Still, + we can provide a small malloc() pool if needed. Driver model in + particular needs this to operate, so that it can allocate the + initial serial device and any others that are needed. + menuconfig EXPERT bool "Configure standard U-Boot features (expert users)" default y diff --git a/common/Kconfig b/common/Kconfig index 7508589fd37..ec82106f3d3 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -81,6 +81,15 @@ config TPL_LOGLEVEL int default LOGLEVEL +config VPL_LOGLEVEL + int "loglevel for VPL" + default LOGLEVEL + help + All Messages with a loglevel smaller than the console loglevel will + be compiled in to VPL. See LOGLEVEL for a list of available log + levels. Setting this to a value above 4 may increase the code size + significantly. + config SILENT_CONSOLE bool "Support a silent console" help @@ -254,6 +263,15 @@ config LOG if LOG +config VPL_LOG + bool "Enable logging support in VPL" + depends on LOG + help + This enables support for logging of status and debug messages. These + can be displayed on the console, recorded in a memory buffer, or + discarded if not needed. Logging supports various categories and + levels of severity. + config LOG_MAX_LEVEL int "Maximum log level to record" default 6 @@ -423,6 +441,47 @@ config TPL_LOG_CONSOLE endif +config VPL_LOG + bool "Enable logging support in VPL" + depends on LOG + help + This enables support for logging of status and debug messages. These + can be displayed on the console, recorded in a memory buffer, or + discarded if not needed. Logging supports various categories and + levels of severity. + +if VPL_LOG + +config VPL_LOG_MAX_LEVEL + int "Maximum log level to record in VPL" + default 3 + help + This selects the maximum log level that will be recorded. Any value + higher than this will be ignored. If possible log statements below + this level will be discarded at build time. Levels: + + 0 - emergency + 1 - alert + 2 - critical + 3 - error + 4 - warning + 5 - note + 6 - info + 7 - debug + 8 - debug content + 9 - debug hardware I/O + +config VPL_LOG_CONSOLE + bool "Allow log output to the console in VPL" + default y + help + Enables a log driver which writes log records to the console. + Generally the console is the serial port or LCD display. Only the + log message is shown - other details like level, category, file and + line number are omitted. + +endif + config LOG_ERROR_RETURN bool "Log all functions which return an error" help @@ -719,6 +778,14 @@ config TPL_BLOBLIST This enables a bloblist in TPL. The bloblist is set up in TPL and passed to SPL and U-Boot proper. +config VPL_BLOBLIST + bool "Support for a bloblist in VPL" + depends on BLOBLIST && VPL_LIBGENERIC_SUPPORT && VPL_LIBCOMMON_SUPPORT + default y if VPL + help + This enables a bloblist in VPL. The bloblist is set up in VPL and + passed to SPL and U-Boot proper. + config BLOBLIST_SIZE hex "Size of bloblist" depends on BLOBLIST diff --git a/common/spl/Kconfig b/common/spl/Kconfig index fb28946f72f..7c311b13a10 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1648,6 +1648,208 @@ config TPL_YMODEM_SUPPORT endif # TPL +config VPL + bool + depends on SUPPORT_SPL + prompt "Enable VPL" + help + If you want to build VPL as well as the normal image, TPL and SPL, + say Y. + +if VPL + +config VPL_BANNER_PRINT + bool "Enable output of the VPL banner 'U-Boot VPL ...'" + depends on VPL + default y + help + If this option is enabled, VPL will print the banner with version + info. Disabling this option could be useful to reduce VPL boot time + (e.g. approx. 6 ms faster, when output on i.MX6 with 115200 baud). + +config VPL_BOARD_INIT + bool "Call board-specific initialization in VPL" + help + If this option is enabled, U-Boot will call the function + spl_board_init() from board_init_r(). This function should be + provided by the board. + +config VPL_CACHE + depends on CACHE + bool "Support cache drivers in VPL" + help + Enable support for cache drivers in VPL. + +config VPL_DM_SPI + bool "Support SPI DM drivers in VPL" + help + Enable support for SPI DM drivers in VPL. + +config VPL_DM_SPI_FLASH + bool "Support SPI DM FLASH drivers in VPL" + help + Enable support for SPI DM flash drivers in VPL. + +config VPL_FRAMEWORK + bool "Support VPL based upon the common SPL framework" + default y + help + Enable the SPL framework under common/spl/ for VPL builds. + This framework supports MMC, NAND and YMODEM and other methods + loading of U-Boot's next stage. If unsure, say Y. + +config VPL_HANDOFF + bool "Pass hand-off information from VPL to SPL" + depends on HANDOFF && VPL_BLOBLIST + default y + help + This option enables VPL to write handoff information. This can be + used to pass information like the size of SDRAM from VPL to SPL. Also + VPL can receive information from TPL in the same place if that is + enabled. + +config VPL_LIBCOMMON_SUPPORT + bool "Support common libraries" + default y if SPL_LIBCOMMON_SUPPORT + help + Enable support for common U-Boot libraries within VPL. See + SPL_LIBCOMMON_SUPPORT for details. + +config VPL_LIBGENERIC_SUPPORT + bool "Support generic libraries" + default y if SPL_LIBGENERIC_SUPPORT + help + Enable support for generic U-Boot libraries within VPL. These + libraries include generic code to deal with device tree, hashing, + printf(), compression and the like. This option is enabled on many + boards. Enable this option to build the code in lib/ as part of a + VPL build. + +config VPL_DRIVERS_MISC + bool "Support misc drivers" + default y if TPL_DRIVERS_MISC + help + Enable miscellaneous drivers in VPL. These drivers perform various + tasks that don't fall nicely into other categories, Enable this + option to build the drivers in drivers/misc as part of a VPL + build, for those that support building in VPL (not all drivers do). + +config VPL_ENV_SUPPORT + bool "Support an environment" + help + Enable environment support in VPL. The U-Boot environment provides + a number of settings (essentially name/value pairs) which can + control many aspects of U-Boot's operation. Enabling this option will + make env_get() and env_set() available in VSPL. + +config VPL_GPIO + bool "Support GPIO in VPL" + default y if SPL_GPIO + help + Enable support for GPIOs (General-purpose Input/Output) in VPL. + GPIOs allow U-Boot to read the state of an input line (high or + low) and set the state of an output line. This can be used to + drive LEDs, control power to various system parts and read user + input. GPIOs can be useful in VPL to enable a 'sign-of-life' LED, + for example. Enable this option to build the drivers in + drivers/gpio as part of a VPL build. + +config VPL_HANDOFF + bool "Pass hand-off information from VPL to SPL and U-Boot proper" + depends on HANDOFF && VPL_BLOBLIST + default y + help + This option enables VPL to write handoff information. This can be + used to pass information like the size of SDRAM from VPL to U-Boot + proper. The information is also available to VPL if it is useful + there. + +config VPL_HASH_SUPPORT + bool "Support hashing drivers in VPL" + depends on VPL + select SHA1 + select SHA256 + help + Enable hashing drivers in VPL. These drivers can be used to + accelerate secure boot processing in secure applications. Enable + this option to build system-specific drivers for hash acceleration + as part of a VPL build. + +config VPL_I2C_SUPPORT + bool "Support I2C in VPL" + default y if SPL_I2C_SUPPORT + help + Enable support for the I2C bus in VPL. Vee SPL_I2C_SUPPORT for + details. + +config VPL_PCH_SUPPORT + bool "Support PCH drivers" + default y if TPL_PCH_SUPPORT + help + Enable support for PCH (Platform Controller Hub) devices in VPL. + These are used to set up GPIOs and the SPI peripheral early in + boot. This enables the drivers in drivers/pch as part of a VPL + build. + +config VPL_PCI + bool "Support PCI drivers" + default y if SPL_PCI + help + Enable support for PCI in VPL. For platforms that need PCI to boot, + or must perform some init using PCI in VPL, this provides the + necessary driver support. This enables the drivers in drivers/pci + as part of a VPL build. + +config VPL_RTC_SUPPORT + bool "Support RTC drivers" + help + Enable RTC (Real-time Clock) support in VPL. This includes support + for reading and setting the time. Some RTC devices also have some + non-volatile (battery-backed) memory which is accessible if + needed. This enables the drivers in drivers/rtc as part of a VPL + build. + +config VPL_SERIAL_SUPPORT + bool "Support serial" + default y if SPL_SERIAL_SUPPORT + select VPL_PRINTF + select VPL_STRTO + help + Enable support for serial in VPL. See SPL_SERIAL_SUPPORT for + details. + +config VPL_SIZE_LIMIT + hex "Maximum size of VPL image" + depends on VPL + default 0x0 + help + Specifies the maximum length of the U-Boot VPL image. + If this value is zero, it is ignored. + +config VPL_SPI_SUPPORT + bool "Support SPI drivers" + help + Enable support for using SPI in VPL. See SPL_SPI_SUPPORT for + details. + +config VPL_SPI_FLASH_SUPPORT + bool "Support SPI flash drivers" + help + Enable support for using SPI flash in VPL, and loading U-Boot from + SPI flash. SPI flash (Serial Peripheral Bus flash) is named after + the SPI bus that is used to connect it to a system. It is a simple + but fast bidirectional 4-wire bus (clock, chip select and two data + lines). This enables the drivers in drivers/mtd/spi as part of a + VPL build. This normally requires VPL_SPI_SUPPORT. + +config VPL_TEXT_BASE + hex "VPL Text Base" + default 0x0 + help + The address in memory that VPL will be running from. + +endif # VPL + config SPL_AT91_MCK_BYPASS bool "Use external clock signal as a source of main clock for AT91 platforms" depends on ARCH_AT91 diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 4023332dd98..8cb43f5e207 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -39,6 +39,18 @@ config TPL_BLK be partitioned into several areas, called 'partitions' in U-Boot. A filesystem can be placed in each partition. +config VPL_BLK + bool "Support block devices in VPL" + depends on VPL_DM && BLK + default y + help + Enable support for block devices, such as SCSI, MMC and USB + flash sticks. These provide a block-level interface which permits + reading, writing and (in some cases) erasing blocks. Block + devices often have a partition table which allows the device to + be partitioned into several areas, called 'partitions' in U-Boot. + A filesystem can be placed in each partition. + config BLOCK_CACHE bool "Use block device cache" depends on BLK diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index e07c6dd78a6..4b0bed66bfb 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -30,6 +30,16 @@ config TPL_CLK setting up clocks within TPL, and allows the same drivers to be used as U-Boot proper. +config VPL_CLK + bool "Enable clock support in VPL" + depends on CLK && VPL_DM + help + The clock subsystem adds a small amount of overhead to the image. + If this is acceptable and you have a need to use clock drivers in + SPL, enable this option. It might provide a cleaner interface to + setting up clocks within TPL, and allows the same drivers to be + used as U-Boot proper. + config CLK_BCM6345 bool "Clock controller driver for BCM6345" depends on CLK && ARCH_BMIPS diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 9ae188c1dfc..33ef6a362f0 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -35,6 +35,16 @@ config TPL_DM CONFIG_SPL_SYS_MALLOC_F_LEN for more details on how to enable it. Disable this for very small implementations. +config VPL_DM + bool "Enable Driver Model for VPL" + depends on DM && VPL + default y if SPL_DM + help + Enable driver model in VPL. You will need to provide a + suitable malloc() implementation. If you are not using the + full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START, + consider using CONFIG_SYS_MALLOC_SIMPLE. + config DM_WARN bool "Enable warnings in driver model" depends on DM @@ -113,6 +123,15 @@ config SPL_DM_SEQ_ALIAS numbered devices (e.g. serial0 = &serial0). This feature can be disabled if it is not required, to save code space in SPL. +config VPL_DM_SEQ_ALIAS + bool "Support numbered aliases in device tree in VPL" + depends on VPL_DM + default y + help + Most boards will have a '/aliases' node containing the path to + numbered devices (e.g. serial0 = &serial0). This feature can be + disabled if it is not required, to save code space in VPL. + config SPL_DM_INLINE_OFNODE bool "Inline some ofnode functions which are seldom used in SPL" depends on SPL_DM @@ -286,6 +305,20 @@ config SPL_OF_TRANSLATE used for the address translation. This function is faster and smaller in size than fdt_translate_address(). +config VPL_OF_TRANSLATE + bool "Translate addresses using fdt_translate_address in SPL" + depends on SPL_DM && VPL_OF_CONTROL + help + If this option is enabled, the reg property will be translated + using the fdt_translate_address() function. This is necessary + on some platforms (e.g. MVEBU) using complex "ranges" + properties in many nodes. As this translation is not handled + correctly in the default simple_bus_translate() function. + + If this option is not enabled, simple_bus_translate() will be + used for the address translation. This function is faster and + smaller in size than fdt_translate_address(). + config TRANSLATION_OFFSET bool "Platforms specific translation offset" depends on DM && OF_CONTROL diff --git a/drivers/core/Makefile b/drivers/core/Makefile index 5edd4e41357..07a0886383f 100644 --- a/drivers/core/Makefile +++ b/drivers/core/Makefile @@ -5,7 +5,7 @@ obj-y += device.o fdtaddr.o lists.o root.o uclass.o util.o obj-$(CONFIG_$(SPL_TPL_)ACPIGEN) += acpi.o obj-$(CONFIG_DEVRES) += devres.o -obj-$(CONFIG_$(SPL_)DM_DEVICE_REMOVE) += device-remove.o +obj-$(CONFIG_$(SPL_TPL_)DM_DEVICE_REMOVE) += device-remove.o obj-$(CONFIG_$(SPL_)SIMPLE_BUS) += simple-bus.o obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o obj-$(CONFIG_DM) += dump.o diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 09695f6c2b0..4d573bde805 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -36,6 +36,17 @@ config TPL_DM_GPIO particular GPIOs that they provide. The uclass interface is defined in include/asm-generic/gpio.h. +config VPL_DM_GPIO + bool "Enable Driver Model for GPIO drivers in VPL" + depends on DM_GPIO && VPL_DM && VPL_GPIO + default y + help + Enable driver model for GPIO access in VPL. The standard GPIO + interface (gpio_get_value(), etc.) is then implemented by + the GPIO uclass. Drivers provide methods to query the + particular GPIOs that they provide. The uclass interface + is defined in include/asm-generic/gpio.h. + config GPIO_HOG bool "Enable GPIO hog support" depends on DM_GPIO diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 63d03a3cebf..308198a44d5 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -47,6 +47,17 @@ config SPL_DM_I2C device (bus child) info is kept as parent platdata. The interface is defined in include/i2c.h. +config VPL_DM_I2C + bool "Enable Driver Model for I2C drivers in VPL" + depends on VPL_DM && DM_I2C + default y + help + Enable driver model for I2C. The I2C uclass interface: probe, read, + write and speed, is implemented with the bus drivers operations, + which provide methods for bus setting and data transfer. Each chip + device (bus child) info is kept as parent platdata. The interface + is defined in include/i2c.h. + config I2C_CROS_EC_TUNNEL tristate "Chrome OS EC tunnel I2C bus" depends on CROS_EC diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 997b7132211..dca25dea56c 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -122,6 +122,16 @@ config TPL_CROS_EC control access to the battery and main PMIC depending on the device. You can use the 'crosec' command to access it. +config VPL_CROS_EC + bool "Enable Chrome OS EC in VPL" + depends on VPL + help + Enable access to the Chrome OS EC in VPL. This is a separate + microcontroller typically available on a SPI bus on Chromebooks. It + provides access to the keyboard, some internal storage and may + control access to the battery and main PMIC depending on the + device. You can use the 'crosec' command to access it. + config CROS_EC_I2C bool "Enable Chrome OS EC I2C driver" depends on CROS_EC @@ -158,6 +168,15 @@ config TPL_CROS_EC_LPC through a legacy port interface, so on x86 machines the main function of the EC is power and thermal management. +config VPL_CROS_EC_LPC + bool "Enable Chrome OS EC LPC driver in VPL" + depends on CROS_EC + help + Enable I2C access to the Chrome OS EC. This is used on x86 + Chromebooks such as link and falco. The keyboard is provided + through a legacy port interface, so on x86 machines the main + function of the EC is power and thermal management. + config CROS_EC_SANDBOX bool "Enable Chrome OS EC sandbox driver" depends on CROS_EC && SANDBOX @@ -185,6 +204,15 @@ config TPL_CROS_EC_SANDBOX EC flash read/write/erase support and a few other things. It is enough to perform a Chrome OS verified boot on sandbox. +config VPL_CROS_EC_SANDBOX + bool "Enable Chrome OS EC sandbox driver in VPL" + depends on VPL_CROS_EC && SANDBOX + help + Enable a sandbox emulation of the Chrome OS EC in VPL. This supports + keyboard (use the -l flag to enable the LCD), verified boot context, + EC flash read/write/erase support and a few other things. It is + enough to perform a Chrome OS verified boot on sandbox. + config CROS_EC_SPI bool "Enable Chrome OS EC SPI driver" depends on CROS_EC diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 77fb8511144..d967a82f726 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -89,20 +89,34 @@ config TPL_PINCTRL This option is an TPL variant of the PINCTRL option. See the help of PINCTRL for details. +config VPL_PINCTRL + bool "Support pin controllers in VPL" + depends on VPL && VPL_DM + help + This option is an VPL variant of the PINCTRL option. + See the help of PINCTRL for details. + config SPL_PINCTRL_FULL bool "Support full pin controllers in SPL" depends on SPL_PINCTRL && SPL_OF_CONTROL default n if TARGET_STM32F746_DISCO default y help - This option is an SPL-variant of the PINCTRL_FULL option. + This option is an SPL variant of the PINCTRL_FULL option. See the help of PINCTRL_FULL for details. config TPL_PINCTRL_FULL bool "Support full pin controllers in TPL" depends on TPL_PINCTRL && TPL_OF_CONTROL help - This option is an TPL-variant of the PINCTRL_FULL option. + This option is a TPL variant of the PINCTRL_FULL option. + See the help of PINCTRL_FULL for details. + +config VPL_PINCTRL_FULL + bool "Support full pin controllers in VPL" + depends on VPL_PINCTRL && VPL_OF_CONTROL + help + This option is a VPL variant of the PINCTRL_FULL option. See the help of PINCTRL_FULL for details. config SPL_PINCTRL_GENERIC diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index cbdfddb80f6..3de6d3fb4d8 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -32,6 +32,15 @@ config TPL_DM_RTC drivers to perform the actual functions. See rtc.h for a description of the API. +config VPL_DM_RTC + bool "Enable Driver Model for RTC drivers in VPL" + depends on VPL_DM + help + Enable drver model for real-time-clock drivers. The RTC uclass + then provides the rtc_get()/rtc_set() interface, delegating to + drivers to perform the actual functions. See rtc.h for a + description of the API. + config RTC_ENABLE_32KHZ_OUTPUT bool "Enable RTC 32Khz output" help diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 93348c0929c..a5142606c71 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -63,6 +63,16 @@ config TPL_SERIAL_PRESENT This option enables the full UART in TPL, so if is it disabled, the full UART driver will be omitted, thus saving space. +config VPL_SERIAL_PRESENT + bool "Provide a serial driver in VPL" + depends on DM_SERIAL && VPL + default y + help + In very space-constrained devices even the full UART driver is too + large. In this case the debug UART can still be used in some cases. + This option enables the full UART in TPL, so if is it disabled, + the full UART driver will be omitted, thus saving space. + # Logic to allow us to use the imply keyword to set what the default port # should be. The default is otherwise 1. config CONS_INDEX_0 @@ -172,6 +182,16 @@ config TPL_DM_SERIAL implements serial_putc() etc. The uclass interface is defined in include/serial.h. +config VPL_DM_SERIAL + bool "Enable Driver Model for serial drivers in VPL" + depends on DM_SERIAL + default y if VPL && DM_SERIAL + help + Enable driver model for serial in VPL. This replaces + drivers/serial/serial.c with the serial uclass, which + implements serial_putc() etc. The uclass interface is + defined in include/serial.h. + config DEBUG_UART bool "Enable an early debug UART for debugging" help diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index ac77ffbc8be..fec6fed6c31 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -31,6 +31,16 @@ config TPL_SYSRESET to effect a reset. The uclass will try all available drivers when reset_walk() is called. +config VPL_SYSRESET + bool "Enable support for system reset drivers in VPL mode" + depends on SYSRESET && VPL_DM + default y if TPL_SYSRESET + help + Enable system reset drivers which can be used to reset the CPU or + board. Each driver can provide a reset method which will be called + to effect a reset. The uclass will try all available drivers when + reset_walk() is called. + if SYSRESET config SYSRESET_CMD_RESET diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index ee81dfa7768..ac601f00ecf 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -27,6 +27,16 @@ config TPL_TIMER function. This enables the drivers in drivers/timer as part of an TPL build. +config VPL_TIMER + bool "Enable driver model for timer drivers in VPL" + depends on TIMER && VPL + default y if TPL_TIMER + help + Enable support for timer drivers in VPL. These can be used to get + a timer value when in VPL, or perhaps for implementing a delay + function. This enables the drivers in drivers/timer as part of an + TPL build. + config TIMER_EARLY bool "Allow timer to be used early in U-Boot" depends on TIMER diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig index 9eebab5cfd9..48864f29770 100644 --- a/drivers/tpm/Kconfig +++ b/drivers/tpm/Kconfig @@ -137,6 +137,36 @@ config TPM2_CR50_I2C trust for a device, It operates like a TPM and can be used with verified boot. Cr50 is used on recent Chromebooks (since 2017). +config SPL_TPM2_CR50_I2C + bool "Enable support for Google cr50 TPM" + depends on DM_I2C && SPL_TPM + help + Cr50 is an implementation of a TPM on Google's H1 security chip. + This uses the same open-source firmware as the Chromium OS EC. + While Cr50 has other features, its primary role is as the root of + trust for a device, It operates like a TPM and can be used with + verified boot. Cr50 is used on recent Chromebooks (since 2017). + +config TPL_TPM2_CR50_I2C + bool "Enable support for Google cr50 TPM" + depends on DM_I2C && TPL_TPM + help + Cr50 is an implementation of a TPM on Google's H1 security chip. + This uses the same open-source firmware as the Chromium OS EC. + While Cr50 has other features, its primary role is as the root of + trust for a device, It operates like a TPM and can be used with + verified boot. Cr50 is used on recent Chromebooks (since 2017). + +config VPL_TPM2_CR50_I2C + bool "Enable support for Google cr50 TPM" + depends on DM_I2C && VPL_TPM + help + Cr50 is an implementation of a TPM on Google's H1 security chip. + This uses the same open-source firmware as the Chromium OS EC. + While Cr50 has other features, its primary role is as the root of + trust for a device, It operates like a TPM and can be used with + verified boot. Cr50 is used on recent Chromebooks (since 2017). + config TPM2_TIS_SANDBOX bool "Enable sandbox TPMv2.x driver" depends on TPM_V2 && SANDBOX diff --git a/dts/Kconfig b/dts/Kconfig index dabe0080c1e..4a6cb3a8af3 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -76,6 +76,15 @@ config TPL_OF_CONTROL which is not enough to support device tree. Enable this option to allow such boards to be supported by U-Boot TPL. +config VPL_OF_CONTROL + bool "Enable run-time configuration via Device Tree in VPL" + depends on VPL && OF_CONTROL + default y if SPL_OF_CONTROL + help + Some boards use device tree in U-Boot but only have 4KB of SRAM + which is not enough to support device tree. Enable this option to + allow such boards to be supported by U-Boot VPL. + config OF_LIVE bool "Enable use of a live tree" depends on DM && OF_CONTROL diff --git a/lib/Kconfig b/lib/Kconfig index fdcf7ea4050..8cf7acf89f4 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -80,6 +80,11 @@ config TPL_PRINTF select TPL_SPRINTF select TPL_STRTO if !TPL_USE_TINY_PRINTF +config VPL_PRINTF + bool + select VPL_SPRINTF + select VPL_STRTO if !VPL_USE_TINY_PRINTF + config SPRINTF bool default y @@ -90,6 +95,9 @@ config SPL_SPRINTF config TPL_SPRINTF bool +config VPL_SPRINTF + bool + config SSCANF bool default n @@ -104,6 +112,9 @@ config SPL_STRTO config TPL_STRTO bool +config VPL_STRTO + bool + config IMAGE_SPARSE bool @@ -156,6 +167,17 @@ config TPL_USE_TINY_PRINTF The supported format specifiers are %c, %s, %u/%d and %x. +config VPL_USE_TINY_PRINTF + bool "Enable tiny printf() version for VPL" + depends on VPL + help + This option enables a tiny, stripped down printf version. + This should only be used in space limited environments, + like SPL versions with hard memory limits. This version + reduces the code size by about 2.5KiB on armv7. + + The supported format specifiers are %c, %s, %u/%d and %x. + config PANIC_HANG bool "Do not reset the system on fatal error" help @@ -340,6 +362,17 @@ config TPL_TPM for the low-level TPM interface, but only one TPM is supported at a time by the TPM library. +config VPL_TPM + bool "Trusted Platform Module (TPM) Support in VPL" + depends on VPL_DM + help + This enables support for TPMs which can be used to provide security + features for your board. The TPM can be connected via LPC or I2C + and a sandbox TPM is provided for testing purposes. Use the 'tpm' + command to interactive the TPM. Driver model support is provided + for the low-level TPM interface, but only one TPM is supported at + a time by the TPM library. + endmenu menu "Android Verified Boot" @@ -527,6 +560,12 @@ config SPL_LZMA help This enables support for LZMA compression algorithm for SPL boot. +config VPL_LZMA + bool "Enable LZMA decompression support for VPL build" + default y if LZMA + help + This enables support for LZMA compression algorithm for VPL boot. + config SPL_LZO bool "Enable LZO decompression support in SPL" help @@ -607,6 +646,7 @@ config OF_LIBFDT_OVERLAY config SPL_OF_LIBFDT bool "Enable the FDT library for SPL" + depends on SPL_LIBGENERIC_SUPPORT default y if SPL_OF_CONTROL help This enables the FDT library (libfdt). It provides functions for @@ -628,6 +668,7 @@ config SPL_OF_LIBFDT_ASSUME_MASK config TPL_OF_LIBFDT bool "Enable the FDT library for TPL" + depends on TPL_LIBGENERIC_SUPPORT default y if TPL_OF_CONTROL help This enables the FDT library (libfdt). It provides functions for @@ -647,6 +688,27 @@ config TPL_OF_LIBFDT_ASSUME_MASK 0xff means all assumptions are made and any invalid data may cause unsafe execution. See FDT_ASSUME_PERFECT, etc. in libfdt_internal.h +config VPL_OF_LIBFDT + bool "Enable the FDT library for VPL" + default y if VPL_OF_CONTROL && !VPL_OF_PLATDATA + help + This enables the FDT library (libfdt). It provides functions for + accessing binary device tree images in memory, such as adding and + removing nodes and properties, scanning through the tree and finding + particular compatible nodes. The library operates on a flattened + version of the device tree. + +config VPL_OF_LIBFDT_ASSUME_MASK + hex "Mask of conditions to assume for libfdt" + depends on VPL_OF_LIBFDT || FIT + default 0xff + help + Use this to change the assumptions made by libfdt in SPL about the + device tree it is working with. A value of 0 means that no assumptions + are made, and libfdt is able to deal with malicious data. A value of + 0xff means all assumptions are made and any invalid data may cause + unsafe execution. See FDT_ASSUME_PERFECT, etc. in libfdt_internal.h + config FDT_FIXUP_PARTITIONS bool "overwrite MTD partitions in DTS through defined in 'mtdparts'" depends on OF_LIBFDT -- 2.32.0.554.ge1b32706d8-goog

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