August 2021 - U-Boot

U-Boot contributor call (3-Aug-21) in 25 minutes
by Simon Glass 03 Aug '21

03 Aug '21

Hi, Agenda today at [1]: Marek - Should we compress U-Boot? (to save flash when you have plenty of RAM) Marek - Could of-platdata be used in U-Boot proper Ilias - Public keys in DT Regards, Simon [1] https://bit.ly/3bFvwA1 or https://docs.google.com/document/d/1YBOMsbM19uSFyoJWnt7-PsOLBaevzQUgV-hiR88…

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[PATCH v6 0/5] Add SIMATIC IOT2050 board support
by Jan Kiszka 03 Aug '21

03 Aug '21

This is the baseline support for the SIMATIC IOT2050 devices. Changes in v6: - rebased - converted board README to docs/board/siemens/iot2050.rst Changes in v5: - rebased - use DEFAULT_LINUX_BOOT_ENV from ti_armv7_common.h, rather than home-grown values - avoids misaligned kernel load address - no longer exposes issue around LMB reservations Changes in v4: - rebased - make rtd-wdt firmware a "loadable" inside U-Boot proper fit image, avoiding controversial embedding as object - improved mmc1 removal from boot_targets - fixed various build issues Changes in v3: - rebased - addressed several checkpatch warnings - a few #ifdef -> IS_ENABLED conversions - comment marker for SPDK identifier in .S file - trailing whitespaces - factored out rti_wdt_load_fw (less #ifdef) Changes in v2: - rebased - sync with upstream-accepted DT - add boot switch - include watchdog support Allows to boot mainline 5.10 kernels, but not the original BSP-derived kernel we currently ship as reference. This is due to the TI sysfw ABI breakages between 2.x and 3.x. We will soon provide a transitional kernel that allows booting both firmware ABIs - as long as full upstream kernel support is work in progress. Note that this baseline support lacks Ethernet drivers. We are working closely with TI to ensure that the to-be-upstreamed icssg-prueth driver will work both with new SR2.0 AM65x silicon as well as with SR1.0 which is used in the currently shipped IOT2050 devices. A staging tree for complete IOT2050 support can be found at [1]. Full image integration is available via [2]. Jan [1] https://github.com/siemens/u-boot/commits/jan/iot2050 [2] https://github.com/siemens/meta-iot2050 Jan Kiszka (5): arm: dts: Add IOT2050 device tree files board: siemens: Add support for SIMATIC IOT2050 devices arm64: dts: ti: k3-am65-mcu: Add RTI watchdog entry watchdog: rti_wdt: Add support for loading firmware iot2050: Enable watchdog support, but do not auto-start it arch/arm/dts/Makefile | 7 +- arch/arm/dts/k3-am65-iot2050-boot-image.dtsi | 121 ++++ .../dts/k3-am65-iot2050-common-u-boot.dtsi | 103 +++ arch/arm/dts/k3-am65-iot2050-common.dtsi | 655 ++++++++++++++++++ arch/arm/dts/k3-am65-iot2050-spl.dts | 16 + arch/arm/dts/k3-am65-mcu.dtsi | 9 + arch/arm/dts/k3-am6528-iot2050-basic.dts | 67 ++ arch/arm/dts/k3-am6548-iot2050-advanced.dts | 66 ++ arch/arm/mach-k3/Kconfig | 1 + board/siemens/iot2050/Kconfig | 32 + board/siemens/iot2050/MAINTAINERS | 9 + board/siemens/iot2050/Makefile | 10 + board/siemens/iot2050/board.c | 284 ++++++++ board/siemens/iot2050/config.mk | 8 + configs/iot2050_defconfig | 138 ++++ doc/board/siemens/iot2050.rst | 76 ++ drivers/watchdog/Kconfig | 20 + drivers/watchdog/rti_wdt.c | 88 +++ include/configs/iot2050.h | 62 ++ 19 files changed, 1771 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/k3-am65-iot2050-boot-image.dtsi create mode 100644 arch/arm/dts/k3-am65-iot2050-common-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am65-iot2050-common.dtsi create mode 100644 arch/arm/dts/k3-am65-iot2050-spl.dts create mode 100644 arch/arm/dts/k3-am6528-iot2050-basic.dts create mode 100644 arch/arm/dts/k3-am6548-iot2050-advanced.dts create mode 100644 board/siemens/iot2050/Kconfig create mode 100644 board/siemens/iot2050/MAINTAINERS create mode 100644 board/siemens/iot2050/Makefile create mode 100644 board/siemens/iot2050/board.c create mode 100644 board/siemens/iot2050/config.mk create mode 100644 configs/iot2050_defconfig create mode 100644 doc/board/siemens/iot2050.rst create mode 100644 include/configs/iot2050.h -- 2.31.1

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Please pull u-boot-x86
by Bin Meng 03 Aug '21

03 Aug '21

Hi Tom, This PR includes the following x86 changes for v2021.10: - Fixed broken ICH SPI driver in software sequencer mode - Added "m25p,fast-read" to SPI flash node for x86 boards - Drop ROM_NEEDS_BLOBS and BUILD_ROM for x86 ROM builds - Define a default TSC timer frequency for all x86 boards - x86 MTRR MSR programming codes bug fixes - x86 "hob" command bug fixes - Don't program MTRR for DRAM for FSP1 - Move INIT_PHASE_END_FIRMWARE to FSP2 - Use external graphics card by default on Intel Crown Bay - tangier: Fix DMA controller IRQ polarity in CSRT Azure results: PASS https://dev.azure.com/bmeng/GitHub/_build/results?buildId=412&view=results The following changes since commit 5371593aed56ee11cbb6cc6ac8d058fcd9b8f58c: Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi (2021-07-31 20:51:24 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-x86 for you to fetch changes up to 9feb5bdcc07b27806df07fd6b9260bb5cdef072d: x86: crownbay: Use external graphics card by default (2021-08-03 00:03:14 +0800) ---------------------------------------------------------------- Andy Shevchenko (1): x86: tangier: Fix DMA controller IRQ polarity in CSRT Bin Meng (16): spi: ich: Limit slave->max_read_size x86: crownbay: Disable CONFIG_SPI_FLASH_SMART_HWCAPS x86: dts: Add "m25p,fast-read" to SPI flash node x86: crownbay: Adjust VGA rom address x86: kconfig: Drop ROM_NEEDS_BLOBS and BUILD_ROM x86: tsc: Rename X86_TSC_TIMER_EARLY_FREQ to X86_TSC_TIMER_FREQ x86: dts: Define a default TSC timer frequency x86: mtrr: Do not clear the unused ones in mtrr_commit() x86: mtrr: Skip MSRs that were already programmed in mtrr_commit() x86: mtrr: Abort if requested size is not power of 2 x86: cmd: hob: Fix the command usage and help messages x86: cmd: hob: Fix display of resource type for system memory x86: fsp: Don't program MTRR for DRAM for FSP1 x86: fsp: Only FSP2 has INIT_PHASE_END_FIRMWARE x86: queensbay: Return directly if IGD / SDVO were already disabled x86: crownbay: Use external graphics card by default Kconfig | 21 --------------------- arch/x86/Kconfig | 2 -- arch/x86/cpu/mtrr.c | 13 ++++++++----- arch/x86/cpu/quark/Kconfig | 5 ++--- arch/x86/cpu/queensbay/tnc.c | 20 +++++++++----------- arch/x86/cpu/tangier/acpi.c | 4 ++-- arch/x86/dts/bayleybay.dts | 3 ++- arch/x86/dts/baytrail_som-db5800-som-6867.dts | 3 ++- arch/x86/dts/cherryhill.dts | 3 ++- arch/x86/dts/chromebook_coral.dts | 4 +++- arch/x86/dts/chromebook_link.dts | 3 ++- arch/x86/dts/chromebook_samus.dts | 3 ++- arch/x86/dts/chromebox_panther.dts | 3 ++- arch/x86/dts/conga-qeval20-qa3-e3845.dts | 3 ++- arch/x86/dts/coreboot.dts | 7 ++----- arch/x86/dts/cougarcanyon2.dts | 3 ++- arch/x86/dts/crownbay.dts | 2 +- arch/x86/dts/dfi-bt700.dtsi | 1 + arch/x86/dts/edison.dts | 2 +- arch/x86/dts/efi-x86_app.dts | 7 ++----- arch/x86/dts/efi-x86_payload.dts | 7 ++----- arch/x86/dts/galileo.dts | 7 ++----- arch/x86/dts/minnowmax.dts | 3 ++- arch/x86/dts/qemu-x86_i440fx.dts | 6 +----- arch/x86/dts/qemu-x86_q35.dts | 6 +----- arch/x86/dts/slimbootloader.dts | 2 +- arch/x86/dts/tsc_timer.dtsi | 1 + arch/x86/include/asm/mtrr.h | 7 ++++--- arch/x86/lib/fsp/fsp_common.c | 16 ---------------- arch/x86/lib/fsp/fsp_dram.c | 27 +++++++++++++++++++++++---- arch/x86/lib/fsp2/fsp_common.c | 17 +++++++++++++++++ cmd/x86/hob.c | 9 ++++----- configs/crownbay_defconfig | 3 ++- doc/arch/x86.rst | 13 ++----------- drivers/spi/ich.c | 6 ++++-- drivers/timer/Kconfig | 8 ++++---- drivers/timer/tsc_timer.c | 5 +++-- 37 files changed, 120 insertions(+), 135 deletions(-) Regards, Bin

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[PATCH 0/5] Use device tree to get DRAM for sama5d27_som1_ek/sama5d2_xplained
by Clément Léger 03 Aug '21

03 Aug '21

Loading U-Boot after OP-TEE requires to move the base address of the DRAM and reduce its size. Indeed, OP-TEE will be loaded at start of DRAM for these platforms and this DRAM will be secured and thus not accessible to U-Boot. Currently, addresses are hardcoded in board configs. This series adds memory property when missing to existing device tree and modify init code to fetch DRAM size from devicetree. This will allow to modify only the device tree to reduce DRAM when needed. Memory addresses have been chosen to have a 32Mb hole at the start of DRAM which allows to put OP-TEE and necessary exchange memory zones. Clément Léger (5): board: sama5d27_som1_ek: Get dram size and base from device tree board: sama5d27_som1_ek: Modify load addresses ARM: dts: at91: sama5d2: Add memory node in devicetree board: sama5d2_xplained: Get dram size and base from device tree board: sama5d2_xplained: Modify load addresses arch/arm/dts/sama5d2.dtsi | 4 ++++ .../atmel/sama5d27_som1_ek/sama5d27_som1_ek.c | 12 ++++++---- .../atmel/sama5d2_xplained/sama5d2_xplained.c | 11 +++++---- include/configs/sama5d27_som1_ek.h | 12 ++++------ include/configs/sama5d2_xplained.h | 24 ++++++++----------- 5 files changed, 33 insertions(+), 30 deletions(-) -- 2.32.0

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[Patch v2 1/2] spi: nxp-fspi: Add support for IP read only
by Kuldeep Singh 03 Aug '21

03 Aug '21

Add support for disabling AHB bus and read entire flash contents via IP bus only. Please note, this enables IP bus read using a quirk which can be enabled directly in device-type data or in existence of an errata where AHB bus may need to be disabled. Signed-off-by: Kuldeep Singh <kuldeep.singh(a)nxp.com> Acked-by: Jagan Teki <jagan(a)amarulasolutions.com> --- v2: - rebase to top of tree drivers/spi/nxp_fspi.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c index 6c5bad4c2c..e1b3d2d77b 100644 --- a/drivers/spi/nxp_fspi.c +++ b/drivers/spi/nxp_fspi.c @@ -304,6 +304,9 @@ #define POLL_TOUT 5000 #define NXP_FSPI_MAX_CHIPSELECT 4 +/* Access flash memory using IP bus only */ +#define FSPI_QUIRK_USE_IP_ONLY BIT(0) + struct nxp_fspi_devtype_data { unsigned int rxfifo; unsigned int txfifo; @@ -338,6 +341,11 @@ struct nxp_fspi { const struct nxp_fspi_devtype_data *devtype_data; }; +static inline int needs_ip_only(struct nxp_fspi *f) +{ + return f->devtype_data->quirks & FSPI_QUIRK_USE_IP_ONLY; +} + /* * R/W functions for big- or little-endian registers: * The FSPI controller's endianness is independent of @@ -769,12 +777,14 @@ static int nxp_fspi_exec_op(struct spi_slave *slave, nxp_fspi_prepare_lut(f, op); /* - * If we have large chunks of data, we read them through the AHB bus - * by accessing the mapped memory. In all other cases we use - * IP commands to access the flash. + * If we have large chunks of data, we read them through the AHB bus by + * accessing the mapped memory. In all other cases we use IP commands + * to access the flash. Read via AHB bus may be corrupted due to + * existence of an errata and therefore discard AHB read in such cases. */ if (op->data.nbytes > (f->devtype_data->rxfifo - 4) && - op->data.dir == SPI_MEM_DATA_IN) { + op->data.dir == SPI_MEM_DATA_IN && + !needs_ip_only(f)) { nxp_fspi_read_ahb(f, op); } else { if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT) @@ -808,6 +818,12 @@ static int nxp_fspi_adjust_op_size(struct spi_slave *slave, op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); } + /* Limit data bytes to RX FIFO in case of IP read only */ + if (needs_ip_only(f) && + op->data.dir == SPI_MEM_DATA_IN && + op->data.nbytes > f->devtype_data->rxfifo) + op->data.nbytes = f->devtype_data->rxfifo; + return 0; } -- 2.25.1

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[PATCH v2 1/2] mtd: spi-nor: Respect flash's hwcaps in spi_nor_adjust_hwcaps()
by Bin Meng 03 Aug '21

03 Aug '21

The smart spi_nor_adjust_hwcaps() does not respect the SPI flash's hwcaps, and only looks to the controller on what can be supported. The flash's hwcaps needs to be AND'ed before checking. Fixes: 71025f013ccb ("mtd: spi-nor-core: Rework hwcaps selection") Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> Reviewed-by: Pratyush Yadav <p.yadav(a)ti.com> --- Changes in v2: - Update comments per Pratyush's review drivers/mtd/spi/spi-nor-core.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 99e2f16349..c8c3bdd890 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2858,10 +2858,11 @@ spi_nor_adjust_hwcaps(struct spi_nor *nor, unsigned int cap; /* - * Enable all caps by default. We will mask them after checking what's - * really supported using spi_mem_supports_op(). + * Start by assuming the controller supports every capability. + * We will mask them after checking what's really supported + * using spi_mem_supports_op(). */ - *hwcaps = SNOR_HWCAPS_ALL; + *hwcaps = SNOR_HWCAPS_ALL & params->hwcaps.mask; /* X-X-X modes are not supported yet, mask them all. */ *hwcaps &= ~SNOR_HWCAPS_X_X_X; -- 2.25.1

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[PATCH] spi: spi-mem-nodm: Fix read data size issue
by Bin Meng 03 Aug '21

03 Aug '21

When slave drivers don't set the max_read_size, the spi-mem should directly use data.nbytes and not limit to any size. But current logic will limit to the max_write_size. This commit mirrors the same changes in the dm version done in commit 535b1fdb8e5e ("spi: spi-mem: Fix read data size issue"). Signed-off-by: Bin Meng <bmeng.cn(a)gmail.com> --- drivers/spi/spi-mem-nodm.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-mem-nodm.c b/drivers/spi/spi-mem-nodm.c index a228c808c7..77ddb19a9f 100644 --- a/drivers/spi/spi-mem-nodm.c +++ b/drivers/spi/spi-mem-nodm.c @@ -93,12 +93,14 @@ int spi_mem_adjust_op_size(struct spi_slave *slave, if (slave->max_write_size && len > slave->max_write_size) return -EINVAL; - if (op->data.dir == SPI_MEM_DATA_IN && slave->max_read_size) - op->data.nbytes = min(op->data.nbytes, - slave->max_read_size); - else if (slave->max_write_size) + if (op->data.dir == SPI_MEM_DATA_IN) { + if (slave->max_read_size) + op->data.nbytes = min(op->data.nbytes, + slave->max_read_size); + } else if (slave->max_write_size) { op->data.nbytes = min(op->data.nbytes, slave->max_write_size - len); + } if (!op->data.nbytes) return -EINVAL; -- 2.25.1

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[PATCH] Avoid adding the same dataflash for the second time
by Jakub Frackowiak 03 Aug '21

03 Aug '21

The spi_dataflash_probe function should return after jedec_probe if it finds any serial flash. This functions adds the same SPI device two times without this path. Serial output when reading environment: Loading Environment from SPIFlash... SPI DataFlash: Detected at45db321d with page size 512 Bytes, erase size 512 Bytes, total 4 MiB, revision d SPI DataFlash: Detected AT45DB321x with page size 528 Bytes, erase size 528 Bytes, total 4.1 MiB, revision *** Warning - bad CRC, using default environment When this patch is applied: Loading Environment from SPIFlash... SPI DataFlash: Detected at45db321d with page size 512 Bytes, erase size 512 Bytes, total 4 MiB, revision d OK --- drivers/mtd/spi/sf_dataflash.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c index b59edd152c..7040f21eb2 100644 --- a/drivers/mtd/spi/sf_dataflash.c +++ b/drivers/mtd/spi/sf_dataflash.c @@ -630,6 +630,9 @@ static int spi_dataflash_probe(struct udevice *dev) if (status == 0 || status == 0xff) status = -ENODEV; goto err_jedec_probe; + + if (!status) + return 0; } /* -- 2.17.1

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[PATCH] armv7: Add Position Independent Execution support
by Chia-Wei Wang 03 Aug '21

03 Aug '21

A U-Boot image could be loaded and executed at a different location than it was linked at. For example, Aspeed takes a stable release version of U-Boot image as the golden one for recovery purposes. When the primary storage such as flash is corrupted, the golden image could be loaded to any SRAM/DRAM address on demands through ethernet/UART/etc. To deal with this condition, the PIE is needed as there is only one signed, golden image, which could be however executed at different places. This patch adds the PIE support for ARMv7 platform. Signed-off-by: Chia-Wei Wang <chiawei_wang(a)aspeedtech.com> --- arch/arm/Kconfig | 4 +++- arch/arm/cpu/armv7/start.S | 43 ++++++++++++++++++++++++++++++++++++++ arch/arm/lib/crt0.S | 11 ++++++++++ arch/arm/lib/relocate.S | 35 ++++++++++++++++++++++--------- 4 files changed, 82 insertions(+), 11 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2b7b625705..45879c9f06 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -9,7 +9,7 @@ config ARM64 select PHYS_64BIT select SYS_CACHE_SHIFT_6 -if ARM64 +if ARM64 || CPU_V7A config POSITION_INDEPENDENT bool "Generate position-independent pre-relocation code" help @@ -19,7 +19,9 @@ config POSITION_INDEPENDENT almost any 4K aligned address. This logic relies on the relocation information that is embedded in the binary to support U-Boot relocating itself to the top-of-RAM later during execution. +endif +if ARM64 config INIT_SP_RELATIVE bool "Specify the early stack pointer relative to the .bss section" default n if ARCH_QEMU diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index dcb4195d7b..3c0b2d6a71 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -39,6 +39,42 @@ reset: /* Allow the board to save important registers */ b save_boot_params save_boot_params_ret: +#ifdef CONFIG_POSITION_INDEPENDENT + /* + * Fix .rela.dyn relocations. This allows U-Boot to loaded to and + * executed at a different address than it was linked at. + */ +pie_fixup: + adr r0, reset /* r0 <- Runtime value of reset label */ + ldr r1, =reset /* r1 <- Linked value of reset label */ + subs r4, r0, r1 /* r4 <- Runtime-vs-link offset */ + beq pie_fixup_done + + adr r0, pie_fixup + ldr r1, _rel_dyn_start_ofs + add r2, r0, r1 /* r2 <- Runtime &__rel_dyn_start */ + ldr r1, _rel_dyn_end_ofs + add r3, r0, r1 /* r3 <- Runtime &__rel_dyn_end */ + +pie_fix_loop: + ldr r0, [r2] /* r0 <- Link location */ + ldr r1, [r2, #4] /* r1 <- fixup */ + cmp r1, #23 /* relative fixup? */ + bne pie_skip_reloc + + /* relative fix: increase location by offset */ + add r0, r4 + ldr r1, [r0] + add r1, r4 + str r1, [r0] + str r0, [r2] + add r2, #8 +pie_skip_reloc: + cmp r2, r3 + blo pie_fix_loop +pie_fixup_done: +#endif + #ifdef CONFIG_ARMV7_LPAE /* * check for Hypervisor support @@ -340,3 +376,10 @@ ENTRY(cpu_init_crit) b lowlevel_init @ go setup pll,mux,memory ENDPROC(cpu_init_crit) #endif + +#if CONFIG_POSITION_INDEPENDENT +_rel_dyn_start_ofs: + .word __rel_dyn_start - pie_fixup +_rel_dyn_end_ofs: + .word __rel_dyn_end - pie_fixup +#endif diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 46b6be21a8..956d258c9d 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -130,6 +130,14 @@ ENTRY(_main) ldr r9, [r9, #GD_NEW_GD] /* r9 <- gd->new_gd */ adr lr, here +#if defined(CONFIG_POSITION_INDEPENDENT) + adr r0, _main + ldr r1, _start_ofs + add r0, r1 + ldr r1, =CONFIG_SYS_TEXT_BASE + sub r1, r0 + add lr, r1 +#endif ldr r0, [r9, #GD_RELOC_OFF] /* r0 = gd->reloc_off */ add lr, lr, r0 #if defined(CONFIG_CPU_V7M) @@ -180,3 +188,6 @@ here: #endif ENDPROC(_main) + +_start_ofs: + .word _start - _main diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S index e5f7267be1..14b7f61c1a 100644 --- a/arch/arm/lib/relocate.S +++ b/arch/arm/lib/relocate.S @@ -78,22 +78,28 @@ ENDPROC(relocate_vectors) */ ENTRY(relocate_code) - ldr r1, =__image_copy_start /* r1 <- SRC &__image_copy_start */ - subs r4, r0, r1 /* r4 <- relocation offset */ - beq relocate_done /* skip relocation */ - ldr r2, =__image_copy_end /* r2 <- SRC &__image_copy_end */ - + adr r3, relocate_code + ldr r1, _image_copy_start_ofs + add r1, r3 /* r1 <- Run &__image_copy_start */ + subs r4, r0, r1 /* r4 <- Run to copy offset */ + beq relocate_done /* skip relocation */ + ldr r1, _image_copy_start_ofs + add r1, r3 /* r1 <- Run &__image_copy_start */ + ldr r2, _image_copy_end_ofs + add r2, r3 /* r2 <- Run &__image_copy_end */ copy_loop: - ldmia r1!, {r10-r11} /* copy from source address [r1] */ - stmia r0!, {r10-r11} /* copy to target address [r0] */ - cmp r1, r2 /* until source end address [r2] */ + ldmia r1!, {r10-r11} /* copy from source address [r1] */ + stmia r0!, {r10-r11} /* copy to target address [r0] */ + cmp r1, r2 /* until source end address [r2] */ blo copy_loop /* * fix .rel.dyn relocations */ - ldr r2, =__rel_dyn_start /* r2 <- SRC &__rel_dyn_start */ - ldr r3, =__rel_dyn_end /* r3 <- SRC &__rel_dyn_end */ + ldr r1, _rel_dyn_start_ofs + add r2, r1, r3 /* r2 <- Run &__rel_dyn_start */ + ldr r1, _rel_dyn_end_ofs + add r3, r1, r3 /* r3 <- Run &__rel_dyn_end */ fixloop: ldmia r2!, {r0-r1} /* (r0,r1) <- (SRC location,fixup) */ and r1, r1, #0xff @@ -129,3 +135,12 @@ relocate_done: #endif ENDPROC(relocate_code) + +_image_copy_start_ofs: + .word __image_copy_start - relocate_code +_image_copy_end_ofs: + .word __image_copy_end - relocate_code +_rel_dyn_start_ofs: + .word __rel_dyn_start - relocate_code +_rel_dyn_end_ofs: + .word __rel_dyn_end - relocate_code -- 2.17.1

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[PATCH v1] mtd: spi-nor-ids: Add support for XMC XM25QH64C
by Reto Schneider 03 Aug '21

03 Aug '21

From: Reto Schneider <reto.schneider(a)husqvarnagroup.com> This chip has been (briefly) tested on the MediaTek MT7688 based GARDENA smart gateway. Datasheet: http://xmcwh.com/Uploads/2020-12-17/XM25QH64C_Ver1.1.pdf Signed-off-by: Reto Schneider <reto.schneider(a)husqvarnagroup.com> --- drivers/mtd/spi/spi-nor-ids.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 2b57797954..b91be10fc3 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -335,6 +335,7 @@ const struct flash_info spi_nor_ids[] = { #ifdef CONFIG_SPI_FLASH_XMC /* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */ { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, #endif { }, -- 2.30.2

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