August 2021 - U-Boot

[PATCH 0/4] xilinx: Add RTC support for Xilinx ZynqMP
by Michal Simek 06 Aug '21

06 Aug '21

Hi, this series is correcting RTC uclass behavior to match RTC aliases to enable RTC_EMULATION driver with ZYNQMP driver. If DT node is present ZynqMP RTC is used. If not RTC emaulation is used. The driver has been tested on Xilinx zcu104 also with booting to Linux to make sure that U-Boot format match with Linux format. Thanks, Michal Michal Simek (4): dm: rtc: uclass: Add flag to control sequence numbering cmd: date: rtc: Update command to read the first RTC with seq 0 rtc: zynqmp: Add support for ZynqMP RTC xilinx: zynqmp: Enable CMD_RTC command with Zynqmp RTC driver MAINTAINERS | 1 + cmd/date.c | 9 +- configs/xilinx_zynqmp_virt_defconfig | 2 + drivers/rtc/Kconfig | 7 ++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-uclass.c | 1 + drivers/rtc/zynqmp_rtc.c | 158 +++++++++++++++++++++++++++ 7 files changed, 176 insertions(+), 3 deletions(-) create mode 100644 drivers/rtc/zynqmp_rtc.c -- 2.32.0

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[PATCH] reset: zynqmp: Add reset controller for ZynqMP SoC
by Michal Simek 06 Aug '21

06 Aug '21

Add firmware based reset controller for Xilinx ZynqMP SoC to let other drivers to call reset functions. Driver is only tested on Xilinx ZynqMP but support for Xilinx Versal can be simply added. That's why reset_id and nr_reset are assigned in probe folder. Driver is inpired by driver from Linux kernel. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- MAINTAINERS | 1 + drivers/reset/Kconfig | 9 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-zynqmp.c | 100 ++++++++++++++++++++++++++ include/zynqmp_firmware.h | 131 +++++++++++++++++++++++++++++++++++ 5 files changed, 242 insertions(+) create mode 100644 drivers/reset/reset-zynqmp.c diff --git a/MAINTAINERS b/MAINTAINERS index 483a45840803..868d4e145ca2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -600,6 +600,7 @@ F: drivers/mtd/nand/raw/zynq_nand.c F: drivers/net/phy/xilinx_phy.c F: drivers/net/zynq_gem.c F: drivers/serial/serial_zynq.c +F: drivers/reset/reset-zynqmp.c F: drivers/rtc/zynqmp_rtc.c F: drivers/spi/zynq_qspi.c F: drivers/spi/zynq_spi.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index a42b3f0077c9..d73daf5e3189 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -197,4 +197,13 @@ config RESET_SCMI Enable this option if you want to support reset controller devices exposed by a SCMI agent based on SCMI reset domain protocol communication with a SCMI server. + +config RESET_ZYNQMP + bool "Reset Driver for Xilinx ZynqMP SoC's" + depends on DM_RESET && ZYNQMP_FIRMWARE + help + Support for reset controller on Xilinx ZynqMP SoC. Driver is only + passing request via Xilinx firmware interface to TF-A and PMU + firmware. + endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 8a0f5280761a..d69486bdeb9e 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -29,3 +29,4 @@ obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o +obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o diff --git a/drivers/reset/reset-zynqmp.c b/drivers/reset/reset-zynqmp.c new file mode 100644 index 000000000000..57652346738d --- /dev/null +++ b/drivers/reset/reset-zynqmp.c @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 Xilinx, Inc. - Michal Simek + */ + +#define LOG_CATEGORY UCLASS_RESET + +#include <common.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <reset-uclass.h> +#include <zynqmp_firmware.h> + +#define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START) +#define ZYNQMP_RESET_ID ZYNQMP_PM_RESET_START + +struct zynqmp_reset_priv { + u32 reset_id; + u32 nr_reset; +}; + +static int zynqmp_pm_reset_assert(const u32 reset, + const enum zynqmp_pm_reset_action assert_flag) +{ + return xilinx_pm_request(PM_RESET_ASSERT, reset, assert_flag, 0, 0, + NULL); +} + +static int zynqmp_reset_assert(struct reset_ctl *rst) +{ + struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev); + + dev_dbg(rst->dev, "%s(rst=%p) (id=%lu)\n", __func__, rst, rst->id); + + return zynqmp_pm_reset_assert(priv->reset_id + rst->id, + PM_RESET_ACTION_ASSERT); +} + +static int zynqmp_reset_deassert(struct reset_ctl *rst) +{ + struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev); + + dev_dbg(rst->dev, "%s(rst=%p) (id=%lu)\n", __func__, rst, rst->id); + + return zynqmp_pm_reset_assert(priv->reset_id + rst->id, + PM_RESET_ACTION_RELEASE); +} + +static int zynqmp_reset_request(struct reset_ctl *rst) +{ + struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev); + + dev_dbg(rst->dev, "%s(rst=%p) (id=%lu) (nr_reset=%d)\n", __func__, + rst, rst->id, priv->nr_reset); + + if (rst->id > priv->nr_reset) + return -EINVAL; + + return 0; +} + +static int zynqmp_reset_free(struct reset_ctl *rst) +{ + struct zynqmp_reset_priv *priv = dev_get_priv(rst->dev); + + dev_dbg(rst->dev, "%s(rst=%p) (id=%lu) (nr_reset=%d)\n", __func__, + rst, rst->id, priv->nr_reset); + + return 0; +} + +static int zynqmp_reset_probe(struct udevice *dev) +{ + struct zynqmp_reset_priv *priv = dev_get_priv(dev); + + priv->reset_id = ZYNQMP_RESET_ID; + priv->nr_reset = ZYNQMP_NR_RESETS; + return 0; +} + +const struct reset_ops zynqmp_reset_ops = { + .request = zynqmp_reset_request, + .rfree = zynqmp_reset_free, + .rst_assert = zynqmp_reset_assert, + .rst_deassert = zynqmp_reset_deassert, +}; + +static const struct udevice_id zynqmp_reset_ids[] = { + { .compatible = "xlnx,zynqmp-reset" }, + { } +}; + +U_BOOT_DRIVER(zynqmp_reset) = { + .name = "zynqmp_reset", + .id = UCLASS_RESET, + .of_match = zynqmp_reset_ids, + .ops = &zynqmp_reset_ops, + .probe = zynqmp_reset_probe, + .priv_auto = sizeof(struct zynqmp_reset_priv), +}; diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 669af6765ce9..90ee1f6b2a78 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -67,6 +67,137 @@ enum pm_api_id { PM_API_MAX, }; +enum zynqmp_pm_reset_action { + PM_RESET_ACTION_RELEASE = 0, + PM_RESET_ACTION_ASSERT = 1, + PM_RESET_ACTION_PULSE = 2, +}; + +enum zynqmp_pm_reset { + ZYNQMP_PM_RESET_START = 1000, + ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START, + ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001, + ZYNQMP_PM_RESET_PCIE_CTRL = 1002, + ZYNQMP_PM_RESET_DP = 1003, + ZYNQMP_PM_RESET_SWDT_CRF = 1004, + ZYNQMP_PM_RESET_AFI_FM5 = 1005, + ZYNQMP_PM_RESET_AFI_FM4 = 1006, + ZYNQMP_PM_RESET_AFI_FM3 = 1007, + ZYNQMP_PM_RESET_AFI_FM2 = 1008, + ZYNQMP_PM_RESET_AFI_FM1 = 1009, + ZYNQMP_PM_RESET_AFI_FM0 = 1010, + ZYNQMP_PM_RESET_GDMA = 1011, + ZYNQMP_PM_RESET_GPU_PP1 = 1012, + ZYNQMP_PM_RESET_GPU_PP0 = 1013, + ZYNQMP_PM_RESET_GPU = 1014, + ZYNQMP_PM_RESET_GT = 1015, + ZYNQMP_PM_RESET_SATA = 1016, + ZYNQMP_PM_RESET_ACPU3_PWRON = 1017, + ZYNQMP_PM_RESET_ACPU2_PWRON = 1018, + ZYNQMP_PM_RESET_ACPU1_PWRON = 1019, + ZYNQMP_PM_RESET_ACPU0_PWRON = 1020, + ZYNQMP_PM_RESET_APU_L2 = 1021, + ZYNQMP_PM_RESET_ACPU3 = 1022, + ZYNQMP_PM_RESET_ACPU2 = 1023, + ZYNQMP_PM_RESET_ACPU1 = 1024, + ZYNQMP_PM_RESET_ACPU0 = 1025, + ZYNQMP_PM_RESET_DDR = 1026, + ZYNQMP_PM_RESET_APM_FPD = 1027, + ZYNQMP_PM_RESET_SOFT = 1028, + ZYNQMP_PM_RESET_GEM0 = 1029, + ZYNQMP_PM_RESET_GEM1 = 1030, + ZYNQMP_PM_RESET_GEM2 = 1031, + ZYNQMP_PM_RESET_GEM3 = 1032, + ZYNQMP_PM_RESET_QSPI = 1033, + ZYNQMP_PM_RESET_UART0 = 1034, + ZYNQMP_PM_RESET_UART1 = 1035, + ZYNQMP_PM_RESET_SPI0 = 1036, + ZYNQMP_PM_RESET_SPI1 = 1037, + ZYNQMP_PM_RESET_SDIO0 = 1038, + ZYNQMP_PM_RESET_SDIO1 = 1039, + ZYNQMP_PM_RESET_CAN0 = 1040, + ZYNQMP_PM_RESET_CAN1 = 1041, + ZYNQMP_PM_RESET_I2C0 = 1042, + ZYNQMP_PM_RESET_I2C1 = 1043, + ZYNQMP_PM_RESET_TTC0 = 1044, + ZYNQMP_PM_RESET_TTC1 = 1045, + ZYNQMP_PM_RESET_TTC2 = 1046, + ZYNQMP_PM_RESET_TTC3 = 1047, + ZYNQMP_PM_RESET_SWDT_CRL = 1048, + ZYNQMP_PM_RESET_NAND = 1049, + ZYNQMP_PM_RESET_ADMA = 1050, + ZYNQMP_PM_RESET_GPIO = 1051, + ZYNQMP_PM_RESET_IOU_CC = 1052, + ZYNQMP_PM_RESET_TIMESTAMP = 1053, + ZYNQMP_PM_RESET_RPU_R50 = 1054, + ZYNQMP_PM_RESET_RPU_R51 = 1055, + ZYNQMP_PM_RESET_RPU_AMBA = 1056, + ZYNQMP_PM_RESET_OCM = 1057, + ZYNQMP_PM_RESET_RPU_PGE = 1058, + ZYNQMP_PM_RESET_USB0_CORERESET = 1059, + ZYNQMP_PM_RESET_USB1_CORERESET = 1060, + ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061, + ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062, + ZYNQMP_PM_RESET_USB0_APB = 1063, + ZYNQMP_PM_RESET_USB1_APB = 1064, + ZYNQMP_PM_RESET_IPI = 1065, + ZYNQMP_PM_RESET_APM_LPD = 1066, + ZYNQMP_PM_RESET_RTC = 1067, + ZYNQMP_PM_RESET_SYSMON = 1068, + ZYNQMP_PM_RESET_AFI_FM6 = 1069, + ZYNQMP_PM_RESET_LPD_SWDT = 1070, + ZYNQMP_PM_RESET_FPD = 1071, + ZYNQMP_PM_RESET_RPU_DBG1 = 1072, + ZYNQMP_PM_RESET_RPU_DBG0 = 1073, + ZYNQMP_PM_RESET_DBG_LPD = 1074, + ZYNQMP_PM_RESET_DBG_FPD = 1075, + ZYNQMP_PM_RESET_APLL = 1076, + ZYNQMP_PM_RESET_DPLL = 1077, + ZYNQMP_PM_RESET_VPLL = 1078, + ZYNQMP_PM_RESET_IOPLL = 1079, + ZYNQMP_PM_RESET_RPLL = 1080, + ZYNQMP_PM_RESET_GPO3_PL_0 = 1081, + ZYNQMP_PM_RESET_GPO3_PL_1 = 1082, + ZYNQMP_PM_RESET_GPO3_PL_2 = 1083, + ZYNQMP_PM_RESET_GPO3_PL_3 = 1084, + ZYNQMP_PM_RESET_GPO3_PL_4 = 1085, + ZYNQMP_PM_RESET_GPO3_PL_5 = 1086, + ZYNQMP_PM_RESET_GPO3_PL_6 = 1087, + ZYNQMP_PM_RESET_GPO3_PL_7 = 1088, + ZYNQMP_PM_RESET_GPO3_PL_8 = 1089, + ZYNQMP_PM_RESET_GPO3_PL_9 = 1090, + ZYNQMP_PM_RESET_GPO3_PL_10 = 1091, + ZYNQMP_PM_RESET_GPO3_PL_11 = 1092, + ZYNQMP_PM_RESET_GPO3_PL_12 = 1093, + ZYNQMP_PM_RESET_GPO3_PL_13 = 1094, + ZYNQMP_PM_RESET_GPO3_PL_14 = 1095, + ZYNQMP_PM_RESET_GPO3_PL_15 = 1096, + ZYNQMP_PM_RESET_GPO3_PL_16 = 1097, + ZYNQMP_PM_RESET_GPO3_PL_17 = 1098, + ZYNQMP_PM_RESET_GPO3_PL_18 = 1099, + ZYNQMP_PM_RESET_GPO3_PL_19 = 1100, + ZYNQMP_PM_RESET_GPO3_PL_20 = 1101, + ZYNQMP_PM_RESET_GPO3_PL_21 = 1102, + ZYNQMP_PM_RESET_GPO3_PL_22 = 1103, + ZYNQMP_PM_RESET_GPO3_PL_23 = 1104, + ZYNQMP_PM_RESET_GPO3_PL_24 = 1105, + ZYNQMP_PM_RESET_GPO3_PL_25 = 1106, + ZYNQMP_PM_RESET_GPO3_PL_26 = 1107, + ZYNQMP_PM_RESET_GPO3_PL_27 = 1108, + ZYNQMP_PM_RESET_GPO3_PL_28 = 1109, + ZYNQMP_PM_RESET_GPO3_PL_29 = 1110, + ZYNQMP_PM_RESET_GPO3_PL_30 = 1111, + ZYNQMP_PM_RESET_GPO3_PL_31 = 1112, + ZYNQMP_PM_RESET_RPU_LS = 1113, + ZYNQMP_PM_RESET_PS_ONLY = 1114, + ZYNQMP_PM_RESET_PL = 1115, + ZYNQMP_PM_RESET_PS_PL0 = 1116, + ZYNQMP_PM_RESET_PS_PL1 = 1117, + ZYNQMP_PM_RESET_PS_PL2 = 1118, + ZYNQMP_PM_RESET_PS_PL3 = 1119, + ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3 +}; + enum pm_query_id { PM_QID_INVALID = 0, PM_QID_CLOCK_GET_NAME = 1, -- 2.32.0

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[PATCH] firmware: xilinx: Use explicit values for all enum values
by Michal Simek 06 Aug '21

06 Aug '21

Based on discussion at https://lore.kernel.org/r/20200318125003.GA2727094@kroah.com we got recommendation to use explicit values for all enum values. The patch is following this recommendation. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> Link: https://lore.kernel.org/r/daeb67ded45d8a8f6a96717d1fb9c84439dd2ae8.16123616… --- include/zynqmp_firmware.h | 93 +++++++++++++++++++++------------------ 1 file changed, 49 insertions(+), 44 deletions(-) diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index f6f82bf8828e..669af6765ce9 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -10,54 +10,59 @@ enum pm_api_id { PM_GET_API_VERSION = 1, - PM_SET_CONFIGURATION, - PM_GET_NODE_STATUS, - PM_GET_OPERATING_CHARACTERISTIC, - PM_REGISTER_NOTIFIER, - PM_REQUEST_SUSPEND, - PM_SELF_SUSPEND, - PM_FORCE_POWERDOWN, - PM_ABORT_SUSPEND, - PM_REQUEST_WAKEUP, - PM_SET_WAKEUP_SOURCE, - PM_SYSTEM_SHUTDOWN, - PM_REQUEST_NODE, - PM_RELEASE_NODE, - PM_SET_REQUIREMENT, - PM_SET_MAX_LATENCY, - PM_RESET_ASSERT, - PM_RESET_GET_STATUS, - PM_MMIO_WRITE, - PM_MMIO_READ, - PM_PM_INIT_FINALIZE, - PM_FPGA_LOAD, - PM_FPGA_GET_STATUS, - PM_GET_CHIPID, + PM_SET_CONFIGURATION = 2, + PM_GET_NODE_STATUS = 3, + PM_GET_OPERATING_CHARACTERISTIC = 4, + PM_REGISTER_NOTIFIER = 5, + /* API for suspending */ + PM_REQUEST_SUSPEND = 6, + PM_SELF_SUSPEND = 7, + PM_FORCE_POWERDOWN = 8, + PM_ABORT_SUSPEND = 9, + PM_REQUEST_WAKEUP = 10, + PM_SET_WAKEUP_SOURCE = 11, + PM_SYSTEM_SHUTDOWN = 12, + PM_REQUEST_NODE = 13, + PM_RELEASE_NODE = 14, + PM_SET_REQUIREMENT = 15, + PM_SET_MAX_LATENCY = 16, + /* Direct control API functions: */ + PM_RESET_ASSERT = 17, + PM_RESET_GET_STATUS = 18, + PM_MMIO_WRITE = 19, + PM_MMIO_READ = 20, + PM_PM_INIT_FINALIZE = 21, + PM_FPGA_LOAD = 22, + PM_FPGA_GET_STATUS = 23, + PM_GET_CHIPID = 24, + /* ID 25 is been used by U-boot to process secure boot images */ + /* Secure library generic API functions */ PM_SECURE_SHA = 26, - PM_SECURE_RSA, - PM_PINCTRL_REQUEST, - PM_PINCTRL_RELEASE, - PM_PINCTRL_GET_FUNCTION, - PM_PINCTRL_SET_FUNCTION, - PM_PINCTRL_CONFIG_PARAM_GET, - PM_PINCTRL_CONFIG_PARAM_SET, - PM_IOCTL, - PM_QUERY_DATA, - PM_CLOCK_ENABLE, - PM_CLOCK_DISABLE, - PM_CLOCK_GETSTATE, - PM_CLOCK_SETDIVIDER, - PM_CLOCK_GETDIVIDER, - PM_CLOCK_SETRATE, - PM_CLOCK_GETRATE, - PM_CLOCK_SETPARENT, - PM_CLOCK_GETPARENT, - PM_SECURE_IMAGE, + PM_SECURE_RSA = 27, + PM_PINCTRL_REQUEST = 28, + PM_PINCTRL_RELEASE = 29, + PM_PINCTRL_GET_FUNCTION = 30, + PM_PINCTRL_SET_FUNCTION = 31, + PM_PINCTRL_CONFIG_PARAM_GET = 32, + PM_PINCTRL_CONFIG_PARAM_SET = 33, + PM_IOCTL = 34, + PM_QUERY_DATA = 35, + PM_CLOCK_ENABLE = 36, + PM_CLOCK_DISABLE = 37, + PM_CLOCK_GETSTATE = 38, + PM_CLOCK_SETDIVIDER = 39, + PM_CLOCK_GETDIVIDER = 40, + PM_CLOCK_SETRATE = 41, + PM_CLOCK_GETRATE = 42, + PM_CLOCK_SETPARENT = 43, + PM_CLOCK_GETPARENT = 44, + PM_SECURE_IMAGE = 45, PM_FPGA_READ = 46, - PM_SECURE_AES, + PM_SECURE_AES = 47, PM_CLOCK_PLL_GETPARAM = 49, + /* PM_REGISTER_ACCESS API */ PM_REGISTER_ACCESS = 52, - PM_EFUSE_ACCESS, + PM_EFUSE_ACCESS = 53, PM_FEATURE_CHECK = 63, PM_API_MAX, }; -- 2.32.0

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[PATCH v2 0/4] xilinx: zynqmp: Add support for dfu_alt_info setup at runtime
by Michal Simek 06 Aug '21

06 Aug '21

Hi, this series is just for composing dfu_alt_info string for capsule update to work automatically based on current setup. QSPI/MMC FAT bootmodes are handled and supported. Other bootmodes are ignored for now. Thanks, Michal Changes in v2: - no need to free local buf variable Michal Simek (4): xilinx: zynqmp: Change multi_boot() to return value xilinx: zynqmp: use zynqmp_mmio_read() in multi_boot() xilinx: zynqmp: Config non zero SYS_SPI_U_BOOT_OFFS xilinx: zynqmp: Add support for runtime dfu_alt_info setup board/xilinx/zynqmp/zynqmp.c | 67 +++++++++++++++++++++++++--- configs/xilinx_zynqmp_virt_defconfig | 2 + 2 files changed, 63 insertions(+), 6 deletions(-) -- 2.32.0

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[PATCH] xilinx: zynqmp: Free allocated field for target variable
by Michal Simek 06 Aug '21

06 Aug '21

When env_set() is called there is no need to allocate memory for variable which is already saved that's why free it. Signed-off-by: Michal Simek <michal.simek(a)xilinx.com> --- board/xilinx/zynqmp/zynqmp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 38c910fa5bab..2cb97f42bec3 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -735,6 +735,7 @@ int board_late_init(void) env_targets ? env_targets : ""); env_set("boot_targets", new_targets); + free(new_targets); reset_reason(); -- 2.32.0

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[PATCH] video: Add simple driver for ST-Ericsson MCDE with pre-configured display
by Stephan Gerhold 06 Aug '21

06 Aug '21

The U-Boot port for ST-Ericsson Ux500 is currently only used on the "stemmy" board, where U-Boot runs after firmware that already sets up a boot splash screen. This means that the display is already on and we can just continue using it for U-Boot. Add a simple driver that simplifies this by reading the display configuration (e.g. screen size, bpp) from the hardware registers. It also checks the configured "source synchronization" - for some displays (usually DSI command mode displays) we need to explicitly trigger a software sync. This is done through the video_sync() callback that triggers the sync and wait for completion. Cc: Linus Walleij <linus.walleij(a)linaro.org> Signed-off-by: Stephan Gerhold <stephan(a)gerhold.net> --- drivers/video/Kconfig | 12 +++ drivers/video/Makefile | 1 + drivers/video/mcde_simple.c | 141 ++++++++++++++++++++++++++++++++++++ 3 files changed, 154 insertions(+) create mode 100644 drivers/video/mcde_simple.c diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index b69ffcae4b..e614a04aab 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -854,6 +854,18 @@ config VIDEO_DT_SIMPLEFB The video output is initialized by U-Boot, and kept by the kernel. +config VIDEO_MCDE_SIMPLE + bool "Simple driver for ST-Ericsson MCDE with preconfigured display" + depends on DM_VIDEO + help + Enables a simple display driver for ST-Ericsson MCDE + (Multichannel Display Engine), which reads the configuration from + the MCDE registers. + + This driver assumes that the display hardware has been initialized + before u-boot starts, and u-boot will simply render to the pre- + allocated frame buffer surface. + config OSD bool "Enable OSD support" depends on DM diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 933f06e9d8..8a70c9deb5 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -58,6 +58,7 @@ obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o +obj-$(CONFIG_VIDEO_MCDE_SIMPLE) += mcde_simple.o obj-${CONFIG_VIDEO_MESON} += meson/ obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_dsi.o obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o diff --git a/drivers/video/mcde_simple.c b/drivers/video/mcde_simple.c new file mode 100644 index 0000000000..0924ceee30 --- /dev/null +++ b/drivers/video/mcde_simple.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright (C) 2019 Stephan Gerhold */ + +#include <common.h> +#include <dm.h> +#include <log.h> +#include <video.h> +#include <asm/io.h> +#include <linux/bitfield.h> +#include <linux/iopoll.h> + +#define MCDE_EXTSRC0A0 0x200 +#define MCDE_EXTSRC0CONF 0x20C +#define MCDE_EXTSRC0CONF_BPP GENMASK(11, 8) +#define MCDE_OVL0CONF 0x404 +#define MCDE_OVL0CONF_PPL GENMASK(10, 0) +#define MCDE_OVL0CONF_LPF GENMASK(26, 16) +#define MCDE_CHNL0SYNCHMOD 0x608 +#define MCDE_CHNL0SYNCHMOD_SRC_SYNCH GENMASK(1, 0) +#define MCDE_CHNL0SYNCHSW 0x60C +#define MCDE_CHNL0SYNCHSW_SW_TRIG BIT(0) +#define MCDE_CRA0 0x800 +#define MCDE_CRA0_FLOEN BIT(0) + +#define MCDE_FLOW_COMPLETION_TIMEOUT 200000 /* us */ + +enum mcde_bpp { + MCDE_EXTSRC0CONF_BPP_1BPP_PAL, + MCDE_EXTSRC0CONF_BPP_2BPP_PAL, + MCDE_EXTSRC0CONF_BPP_4BPP_PAL, + MCDE_EXTSRC0CONF_BPP_8BPP_PAL, + MCDE_EXTSRC0CONF_BPP_RGB444, + MCDE_EXTSRC0CONF_BPP_ARGB4444, + MCDE_EXTSRC0CONF_BPP_IRGB1555, + MCDE_EXTSRC0CONF_BPP_RGB565, + MCDE_EXTSRC0CONF_BPP_RGB888, + MCDE_EXTSRC0CONF_BPP_XRGB8888, + MCDE_EXTSRC0CONF_BPP_ARGB8888, + MCDE_EXTSRC0CONF_BPP_YCBCR422, +}; + +enum mcde_src_synch { + MCDE_CHNL0SYNCHMOD_SRC_SYNCH_HARDWARE, + MCDE_CHNL0SYNCHMOD_SRC_SYNCH_NO_SYNCH, + MCDE_CHNL0SYNCHMOD_SRC_SYNCH_SOFTWARE, +}; + +struct mcde_simple_priv { + fdt_addr_t base; + enum mcde_src_synch src_synch; +}; + +static int mcde_simple_probe(struct udevice *dev) +{ + struct mcde_simple_priv *priv = dev_get_priv(dev); + struct video_uc_plat *plat = dev_get_uclass_plat(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + u32 val; + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->base = readl(priv->base + MCDE_EXTSRC0A0); + if (!plat->base) + return -ENODEV; + + val = readl(priv->base + MCDE_OVL0CONF); + uc_priv->xsize = FIELD_GET(MCDE_OVL0CONF_PPL, val); + uc_priv->ysize = FIELD_GET(MCDE_OVL0CONF_LPF, val); + uc_priv->rot = 0; + + val = readl(priv->base + MCDE_EXTSRC0CONF); + switch (FIELD_GET(MCDE_EXTSRC0CONF_BPP, val)) { + case MCDE_EXTSRC0CONF_BPP_RGB565: + uc_priv->bpix = VIDEO_BPP16; + break; + case MCDE_EXTSRC0CONF_BPP_XRGB8888: + case MCDE_EXTSRC0CONF_BPP_ARGB8888: + uc_priv->bpix = VIDEO_BPP32; + break; + default: + printf("unsupported format: %#x\n", val); + return -EINVAL; + } + + val = readl(priv->base + MCDE_CHNL0SYNCHMOD); + priv->src_synch = FIELD_GET(MCDE_CHNL0SYNCHMOD_SRC_SYNCH, val); + + plat->size = uc_priv->xsize * uc_priv->ysize * VNBYTES(uc_priv->bpix); + debug("MCDE base: %#lx, xsize: %d, ysize: %d, bpp: %d\n", + plat->base, uc_priv->xsize, uc_priv->ysize, VNBITS(uc_priv->bpix)); + + video_set_flush_dcache(dev, true); + return 0; +} + +static int mcde_simple_video_sync(struct udevice *dev) +{ + struct mcde_simple_priv *priv = dev_get_priv(dev); + unsigned int val; + + if (priv->src_synch != MCDE_CHNL0SYNCHMOD_SRC_SYNCH_SOFTWARE) + return 0; + + /* Enable flow */ + val = readl(priv->base + MCDE_CRA0); + val |= MCDE_CRA0_FLOEN; + writel(val, priv->base + MCDE_CRA0); + + /* Trigger a software sync */ + writel(MCDE_CHNL0SYNCHSW_SW_TRIG, priv->base + MCDE_CHNL0SYNCHSW); + + /* Disable flow */ + val = readl(priv->base + MCDE_CRA0); + val &= ~MCDE_CRA0_FLOEN; + writel(val, priv->base + MCDE_CRA0); + + /* Wait for completion */ + return readl_poll_timeout(priv->base + MCDE_CRA0, val, + !(val & MCDE_CRA0_FLOEN), + MCDE_FLOW_COMPLETION_TIMEOUT); +} + +static struct video_ops mcde_simple_ops = { + .video_sync = mcde_simple_video_sync, +}; + +static const struct udevice_id mcde_simple_ids[] = { + { .compatible = "ste,mcde" }, + { } +}; + +U_BOOT_DRIVER(mcde_simple) = { + .name = "mcde_simple", + .id = UCLASS_VIDEO, + .ops = &mcde_simple_ops, + .of_match = mcde_simple_ids, + .probe = mcde_simple_probe, + .priv_auto = sizeof(struct mcde_simple_priv), +}; -- 2.32.0

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[PATCH] video: Hitachi panel: Drop bogus dependency on CONFIG_VIDEO
by Andre Przywara 06 Aug '21

06 Aug '21

The Hitachi tx18d42vm LCD panel driver is really just initialising the device, using bitbanged SPI, during operation there is nothing to do. This makes the driver self contained, so drop the bogus dependency on the legacy CONFIG_VIDEO. This avoids the warning when building Chuwi_V7_CW0825_defconfig, since we switched to DM_VIDEO recently. Signed-off-by: Andre Przywara <andre.przywara(a)arm.com> --- drivers/video/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index b69ffcae4b2..173b9c99399 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -470,7 +470,6 @@ config VIDEO_LCD_TDO_TL070WSH30 config VIDEO_LCD_HITACHI_TX18D42VM bool "Hitachi tx18d42vm LVDS LCD panel support" - depends on VIDEO default n ---help--- Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a -- 2.17.6

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[PATCH v2 0/6] add measurement support
by Masahisa Kojima 06 Aug '21

06 Aug '21

This patch series add the support of measurement descibed in TCG PC Client PFP spec(Version 1.05 Revision 23). Eventlog generated with this patch series are tested on the aarch64 based machine(Socionext Developerbox) and fTPM running on OP-TEE. The eventlog result is almost same result as the one generated by edk2 running on the Devloperbox and Secure96. This patch series does not cover all measurement requirements described in TCG spec, the remaining items will be supported in the future. Major missing items in TCG PC Client PFP spec: 1) If the secure boot variables are updated after they are initially measured in PCR[7] and before ExitBootServices() has completed, the platform MAY be restarted OR the variables MUST be remeasured into PCR[7]. 2) SMBIOS structure measurement 3) "DeployedMode" and "AuditMode" measurement 4) EV_EFI_GPT_EVENT event 5) Measurement of U-boot itself. I assume U-boot measurement will be done by the former firmware such as trusted firmware. Masahisa Kojima (6): efi_loader: increase eventlog buffer size efi_loader: add secure boot variable measurement efi_loader: add boot variable measurement efi_loader: add ExitBootServices() measurement efi_loader: refactor efi_append_scrtm_version() efi_loader: add comment for efi_tcg2.h include/efi_loader.h | 5 + include/efi_tcg2.h | 71 ++++++++ include/tpm-v2.h | 18 +- lib/efi_loader/Kconfig | 2 +- lib/efi_loader/efi_boottime.c | 25 +++ lib/efi_loader/efi_tcg2.c | 331 +++++++++++++++++++++++++++++++++- 6 files changed, 444 insertions(+), 8 deletions(-) -- 2.17.1

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[PATCH 1/1] efi_loader: Uri() device path node
by Heinrich Schuchardt 06 Aug '21

06 Aug '21

iPXE used Uri() device path nodes. So we should support them in the device path to text protocol. Signed-off-by: Heinrich Schuchardt <xypron.glpk(a)gmx.de> --- include/efi_api.h | 6 ++++++ lib/efi_loader/efi_device_path_to_text.c | 13 +++++++++++++ 2 files changed, 19 insertions(+) diff --git a/include/efi_api.h b/include/efi_api.h index 18a1adf023..bfe33921aa 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -527,6 +527,7 @@ struct efi_device_path_acpi_path { # define DEVICE_PATH_SUB_TYPE_MSG_USB_CLASS 0x0f # define DEVICE_PATH_SUB_TYPE_MSG_SATA 0x12 # define DEVICE_PATH_SUB_TYPE_MSG_NVME 0x17 +# define DEVICE_PATH_SUB_TYPE_MSG_URI 0x18 # define DEVICE_PATH_SUB_TYPE_MSG_SD 0x1a # define DEVICE_PATH_SUB_TYPE_MSG_MMC 0x1d @@ -591,6 +592,11 @@ struct efi_device_path_nvme { u8 eui64[8]; } __packed; +struct efi_device_path_uri { + struct efi_device_path dp; + u8 uri[]; +} __packed; + #define DEVICE_PATH_TYPE_MEDIA_DEVICE 0x04 # define DEVICE_PATH_SUB_TYPE_HARD_DRIVE_PATH 0x01 # define DEVICE_PATH_SUB_TYPE_CDROM_PATH 0x02 diff --git a/lib/efi_loader/efi_device_path_to_text.c b/lib/efi_loader/efi_device_path_to_text.c index 675e80bcb8..d46327a1c9 100644 --- a/lib/efi_loader/efi_device_path_to_text.c +++ b/lib/efi_loader/efi_device_path_to_text.c @@ -190,6 +190,19 @@ static char *dp_msging(char *s, struct efi_device_path *dp) break; } + case DEVICE_PATH_SUB_TYPE_MSG_URI: { + struct efi_device_path_uri *udp = + (struct efi_device_path_uri *)dp; + int n; + + n = (int)udp->dp.length - sizeof(struct efi_device_path_uri); + + s += sprintf(s, "Uri("); + if (n > 0 && n < MAX_NODE_LEN - 6) + s += snprintf(s, n, "%s", (char *)udp->uri); + s += sprintf(s, ")"); + break; + } case DEVICE_PATH_SUB_TYPE_MSG_SD: case DEVICE_PATH_SUB_TYPE_MSG_MMC: { const char *typename = -- 2.30.2

1 0

tiny-printf: endless loop for %llu format
by Matwey V. Kornilov 05 Aug '21

05 Aug '21

Hi, I am trying to boot AM335x platform via TFTP and found another one issue related to tiny-printf: print_size() in lib/display_options.c relies on printf("%llu Bytes%s", size, s); and it surprisingly leads to infinite looping when tiny-printf is used in SPL. So, I am afraid that TFTP in SPL is currently broken for every board. -- With best regards, Matwey V. Kornilov

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