August 2021 - U-Boot

[PATCH] Revert "arm: bootm: Disable LMB reservation for command line and board info on arm64"
by Jan Kiszka 09 Aug '21

09 Aug '21

From: Jan Kiszka <jan.kiszka(a)siemens.com> This reverts commit 2359fa7a87848626bcbd3399e92c657595880cd7. While the goal is valid and there is surely unused memory in that area, we also have a lot of crucial things still located at the top-of-memory while running lmb_alloc_base. Such things are the page table (tlb_addr), relocated U-Boot and the active stack. Possibly more. So this patch was premature, we will need relocations of those things first if we want to use the range. Fixes booting on the IOT2050, but likely also on other boards. It got stuck on relocating the FDT - over the relocated U-Boot code. Signed-off-by: Jan Kiszka <jan.kiszka(a)siemens.com> --- Practically, void arch_lmb_reserve(struct lmb *lmb) { lmb_reserve(lmb, gd->relocaddr, gd->ram_top - gd->relocaddr); } worked as well for me - but it left the stack in danger. arch/arm/lib/bootm.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 23b99a541c..f60ee3a7e6 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -43,7 +43,6 @@ DECLARE_GLOBAL_DATA_PTR; static struct tag *params; -#ifndef CONFIG_ARM64 static ulong get_sp(void) { ulong ret; @@ -87,7 +86,6 @@ void arch_lmb_reserve(struct lmb *lmb) break; } } -#endif __weak void board_quiesce_devices(void) { -- 2.26.2

5 38

[PATCH v1 0/5] arm64: Add optimized memset/memcpy functions
by Stefan Roese 09 Aug '21

09 Aug '21

On an NXP LX2160 based platform it has been noticed, that the currently implemented memset/memcpy functions for aarch64 are suboptimal. Especially the memset() for clearing the NXP MC firmware memory is very expensive (time-wise). By using optimized functions, a speedup of ~ factor 6 has been measured. This patchset now adds the optimized functions ported from this repository: https://github.com/ARM-software/optimized-routines As these functions make use of opcodes that need the caches to be enabled, they can't be used in the very early boot stage, before the caches are enabled. Because of this, a simple memset() version is also added, in this case memset_simple(), and will be used in very few selected places. Please note that checkpatch.pl complains about some issue with this imported file: arch/arm/lib/asmdefs.h Since it's imported I did explicitly not make any changes here, to make potential future sync'ing easer. Thanks, Stefan Stefan Roese (5): lib/string: Add memset_simple() board_init: Use memset_simple() in board_init_f_init_reserve() arm64: cache_v8: Use memset_simple() in create_table() arm64: arch/arm/lib: Add optimized memset/memcpy functions arm64: Kconfig: Enable usage of optimized memset/memcpy arch/arm/Kconfig | 10 +- arch/arm/cpu/armv8/cache_v8.c | 2 +- arch/arm/lib/Makefile | 5 + arch/arm/lib/asmdefs.h | 98 ++++++++++++++ arch/arm/lib/memcpy-arm64.S | 241 ++++++++++++++++++++++++++++++++++ arch/arm/lib/memset-arm64.S | 116 ++++++++++++++++ common/init/board_init.c | 2 +- include/linux/string.h | 2 + lib/string.c | 10 ++ 9 files changed, 478 insertions(+), 8 deletions(-) create mode 100644 arch/arm/lib/asmdefs.h create mode 100644 arch/arm/lib/memcpy-arm64.S create mode 100644 arch/arm/lib/memset-arm64.S -- 2.32.0

5 16

[PATCH] lib: add crc16.o if CONFIG_MMC_SPI_CRC_ON for SPL build
by Andreas Schwab 09 Aug '21

09 Aug '21

CONFIG_MMC_SPI_CRC_ON needs the crc16 functions, but it was not included in an SPL build. For non-SPL builds, crc16.o is already added unconditionally. This also removes CONFIG_SPL_YMODEM_SUPPORT from the sifive board configs, which is only relevant for some ARM boards and was only set for its side effect of adding crc16.o. Signed-off-by: Andreas Schwab <schwab(a)suse.de> --- configs/sifive_unleashed_defconfig | 1 - configs/sifive_unmatched_defconfig | 1 - lib/Makefile | 1 + 3 files changed, 1 insertion(+), 2 deletions(-) diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig index fd686dfadc..d6448dbf5e 100644 --- a/configs/sifive_unleashed_defconfig +++ b/configs/sifive_unleashed_defconfig @@ -22,7 +22,6 @@ CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_CLK=y diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index 38b7acd536..d37c019cda 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -20,7 +20,6 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DM_RESET=y -CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_EEPROM=y CONFIG_CMD_MEMINFO=y CONFIG_CMD_PWM=y diff --git a/lib/Makefile b/lib/Makefile index 07c2ccd7cf..7ae2ccf537 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -87,6 +87,7 @@ endif ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o obj-$(CONFIG_$(SPL_TPL_)HASH_SUPPORT) += crc16.o +obj-$(CONFIG_MMC_SPI_CRC_ON) += crc16.o obj-y += net_utils.o endif obj-$(CONFIG_ADDR_MAP) += addr_map.o -- 2.32.0 -- Andreas Schwab, SUSE Labs, schwab(a)suse.de GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7 "And now for something completely different."

1 0

[PATCH 1/5] ARM: board: warp: Import dts files
by Peter Robinson 09 Aug '21

09 Aug '21

Import the i.MX6 based Warp dts files from Linux 5.12-rc1. Signed-off-by: Peter Robinson <pbrobinson(a)gmail.com> Cc: Fabio Estevam <fabio.estevam(a)nxp.com> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/dts/Makefile | 4 +- arch/arm/dts/imx6sl-warp.dts | 234 +++++++++++++++++++++++++++++++++++ 2 files changed, 237 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx6sl-warp.dts diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 116f75192f..1481a6ec46 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -734,7 +734,9 @@ dtb-y += \ endif -dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb +dtb-$(CONFIG_MX6SL) += \ + imx6sl-evk.dtb \ + imx6sl-warp.dtb dtb-$(CONFIG_MX6SLL) += imx6sll-evk.dtb diff --git a/arch/arm/dts/imx6sl-warp.dts b/arch/arm/dts/imx6sl-warp.dts new file mode 100644 index 0000000000..9d7c888489 --- /dev/null +++ b/arch/arm/dts/imx6sl-warp.dts @@ -0,0 +1,234 @@ +/* + * Copyright 2014, 2015 O.S. Systems Software LTDA. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "imx6sl.dtsi" + +/ { + model = "Revotics WaRP Board"; + compatible = "revotics,imx6sl-warp", "fsl,imx6sl"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + usdhc3_pwrseq: usdhc3_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */ + <&gpio4 7 GPIO_ACTIVE_LOW>, /* WL_HOSTWAKE */ + <&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */ + <&gpio3 27 GPIO_ACTIVE_LOW>, /* BT_HOSTWAKE */ + <&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */ + <&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */ + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + wakeup-source; + mmc-pwrseq = <&usdhc3_pwrseq>; + status = "okay"; +}; + +&iomuxc { + imx6sl-warp { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x41b0b1 + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x41b0b1 + >; + }; + + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x41b0b1 + MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x41b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SL_PAD_ECSPI1_SCLK__UART5_RX_DATA 0x41b0b1 + MX6SL_PAD_ECSPI1_MOSI__UART5_TX_DATA 0x41b0b1 + MX6SL_PAD_ECSPI1_MISO__UART5_RTS_B 0x4130b1 + MX6SL_PAD_ECSPI1_SS0__UART5_CTS_B 0x4130b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x410059 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x417059 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x417059 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x417059 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x417059 + MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x417059 + MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059 + MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059 + MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059 + MX6SL_PAD_SD2_RST__SD2_RESET 0x417059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170b9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100b9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170b9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170b9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170b9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170b9 + MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170b9 + MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9 + MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9 + MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9 + MX6SL_PAD_SD2_RST__SD2_RESET 0x4170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170f9 + MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100f9 + MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170f9 + MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170f9 + MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170f9 + MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170f9 + MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170f9 + MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9 + MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9 + MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9 + MX6SL_PAD_SD2_RST__SD2_RESET 0x4170f9 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x417059 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x410059 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x417059 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x417059 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x417059 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x417059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170b9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100b9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170b9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170b9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170b9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170f9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100f9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170f9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170f9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170f9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170f9 + >; + }; + }; +}; -- 2.31.1

5 13

[PATCH V5 00/44] imx: add i.MX8ULP support
by Peng Fan (OSS) 09 Aug '21

09 Aug '21

From: Peng Fan <peng.fan(a)nxp.com> V5: Rebased on latest master. The build break was introduced by Simon's SPL config change that drop the "_SUPPORT". So this patchset use new SPL config name in patch 44. V4: Fix checkpatch errors Fix some checkpatch warnings, there are still warnings such as pin header and dts exceed 100. Tom, Stefano, please see whether you are happy with this patchset. V3: Fix build error which break 8MN, pass buildman for i.MX. Select GPIO_EXTRA_HEADER for 8ULP to fix build break which caused by upstream change. Rebased Drop 7ULP, since already been picked up. V2: Rebased and test on new revision silicon with upower included. The i.MX 8ULP crossover applications processor family brings ultra-low power processing and advanced integrated security with EdgeLockTM secure enclave to the intelligent edge. It includes an uPower core for handling power related functions. This patchset is to add initial support for i.MX8ULP, with core soc functions, clock, dtsi, and evk board. Peng Fan (24): arm: imx: add i.MX8ULP basic Kconfig option arm: imx: add i.MX8ULP cpu type and helper arm: imx: sys_proto: move boot mode define to common header arm: imx8ulp: support print cpu info imx: imx8ulp: add get reset cause arm: imx: basic i.MX8ULP support arm: imx: parse-container: guard included header files arm: imx: move container Kconfig under mach-imx net: fec_mxc: support i.MX8ULP driver: serial: fsl_lpuart: support i.MX8ULP arm: imx8ulp: add clock support drivers: mmc: fsl_esdhc_imx: support i.MX8ULP arm: imx8ulp: disable wdog3 arm: imx8ulp: add rdc support arm: imx8ulp: add trdc release request arm: imx8ulp: release trdc and assign lpav from RTD to APD imx8ulp: unify rdc functions arm: imx8ulp: add dummy imx_get_mac_from_fuse arm: imx8ulp: add iomuxc support imx8ulp: soc: correct reset cause imx8ulp: move struct mu_type to common header imx8ulp: add upower api support arm: dts: add i.MX8ULP dtsi arm: imx: add i.MX8ULP EVK support Ye Li (20): arm: imx8: Move container parser and image to mach-imx common folder arm: imx8: Move container image header file to mach-imx arm: imx8ulp: add container support driver: misc: Add MU and S400 API to communicate with Sentinel pinctrl: Add pinctrl driver for imx8ulp arm: imx8ulp: soc: Change to use CMC1 to get bootcfg arm: imx8ulp: Enable full L2 cache in SPL arm: imx8ulp: Update the reset vector in u-boot drivers: misc: s400_api: Update S400_SUCCESS_IND to 0xd6 drivers: misc: imx8ulp: Add S400 API for image authentication drivers: misc: imx8ulp: Update S400 API for release RDC drivers: misc: s400_api: Update API for fuse read and write arm: imx8ulp: release and configure XRDC at early phase arm: imx8ulp: Probe the S400 MU device in arch init arm: iMX8ULP: Add boot device relevant functions arm: imx8ulp: Allocate DCNANO and MIPI_DSI to AD domain driver: misc: imx8ulp: Add fuse driver for imx8ulp imx8ulp: Use DGO_GP5 to get boot config imx8ulp: Add workaround for eMMC boot ddr: Add DDR driver for iMX8ULP arch/arm/Kconfig | 11 + arch/arm/Makefile | 4 +- arch/arm/dts/Makefile | 3 + arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 40 + arch/arm/dts/imx8ulp-evk.dts | 223 ++++ arch/arm/dts/imx8ulp-pinfunc.h | 978 ++++++++++++++ arch/arm/dts/imx8ulp.dtsi | 728 +++++++++++ arch/arm/include/asm/arch-imx/cpu.h | 4 + arch/arm/include/asm/arch-imx8ulp/cgc.h | 130 ++ arch/arm/include/asm/arch-imx8ulp/clock.h | 41 + arch/arm/include/asm/arch-imx8ulp/ddr.h | 38 + arch/arm/include/asm/arch-imx8ulp/gpio.h | 20 + arch/arm/include/asm/arch-imx8ulp/imx-regs.h | 162 +++ .../include/asm/arch-imx8ulp/imx8ulp-pins.h | 60 + arch/arm/include/asm/arch-imx8ulp/iomux.h | 82 ++ arch/arm/include/asm/arch-imx8ulp/mu_hal.h | 12 + arch/arm/include/asm/arch-imx8ulp/pcc.h | 139 ++ arch/arm/include/asm/arch-imx8ulp/rdc.h | 27 + arch/arm/include/asm/arch-imx8ulp/s400_api.h | 41 + arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 19 + arch/arm/include/asm/arch-imx8ulp/upower.h | 15 + arch/arm/include/asm/arch-mx7ulp/sys_proto.h | 9 - arch/arm/include/asm/global_data.h | 5 + .../asm/{arch-imx8 => mach-imx}/image.h | 2 + arch/arm/include/asm/mach-imx/sys_proto.h | 13 +- arch/arm/mach-imx/Kconfig | 15 +- arch/arm/mach-imx/Makefile | 5 + arch/arm/mach-imx/cmd_dek.c | 2 +- .../{imx8/image.c => image-container.c} | 51 +- arch/arm/mach-imx/imx8/Kconfig | 13 - arch/arm/mach-imx/imx8/Makefile | 3 - arch/arm/mach-imx/imx8/ahab.c | 2 +- arch/arm/mach-imx/imx8ulp/Kconfig | 23 + arch/arm/mach-imx/imx8ulp/Makefile | 11 + arch/arm/mach-imx/imx8ulp/cgc.c | 455 +++++++ arch/arm/mach-imx/imx8ulp/clock.c | 397 ++++++ arch/arm/mach-imx/imx8ulp/iomux.c | 58 + arch/arm/mach-imx/imx8ulp/lowlevel_init.S | 26 + arch/arm/mach-imx/imx8ulp/pcc.c | 449 +++++++ arch/arm/mach-imx/imx8ulp/rdc.c | 411 ++++++ arch/arm/mach-imx/imx8ulp/soc.c | 545 ++++++++ arch/arm/mach-imx/imx8ulp/upower/Makefile | 6 + arch/arm/mach-imx/imx8ulp/upower/upower_api.c | 486 +++++++ arch/arm/mach-imx/imx8ulp/upower/upower_api.h | 258 ++++ arch/arm/mach-imx/imx8ulp/upower/upower_hal.c | 180 +++ .../arm/mach-imx/{imx8 => }/parse-container.c | 4 +- arch/arm/mach-imx/spl_imx_romapi.c | 172 ++- board/freescale/imx8ulp_evk/Kconfig | 14 + board/freescale/imx8ulp_evk/MAINTAINERS | 6 + board/freescale/imx8ulp_evk/Makefile | 7 + board/freescale/imx8ulp_evk/ddr_init.c | 207 +++ board/freescale/imx8ulp_evk/imx8ulp_evk.c | 67 + board/freescale/imx8ulp_evk/lpddr4_timing.c | 1159 +++++++++++++++++ board/freescale/imx8ulp_evk/spl.c | 105 ++ configs/imx8ulp_evk_defconfig | 103 ++ drivers/Makefile | 1 + drivers/ddr/imx/Kconfig | 1 + drivers/ddr/imx/imx8ulp/Kconfig | 11 + drivers/ddr/imx/imx8ulp/Makefile | 9 + drivers/ddr/imx/imx8ulp/ddr_init.c | 217 +++ drivers/misc/Makefile | 1 + drivers/misc/imx8ulp/Makefile | 4 + drivers/misc/imx8ulp/fuse.c | 198 +++ drivers/misc/imx8ulp/imx8ulp_mu.c | 234 ++++ drivers/misc/imx8ulp/s400_api.c | 244 ++++ drivers/mmc/Kconfig | 2 +- drivers/mmc/fsl_esdhc_imx.c | 12 +- drivers/net/Kconfig | 2 +- drivers/net/fec_mxc.c | 2 +- drivers/pinctrl/nxp/Kconfig | 14 + drivers/pinctrl/nxp/Makefile | 1 + drivers/pinctrl/nxp/pinctrl-imx8ulp.c | 44 + include/configs/imx8ulp_evk.h | 107 ++ include/dt-bindings/clock/imx8ulp-clock.h | 247 ++++ include/fsl_lpuart.h | 2 +- 75 files changed, 9313 insertions(+), 86 deletions(-) create mode 100644 arch/arm/dts/imx8ulp-evk-u-boot.dtsi create mode 100644 arch/arm/dts/imx8ulp-evk.dts create mode 100644 arch/arm/dts/imx8ulp-pinfunc.h create mode 100644 arch/arm/dts/imx8ulp.dtsi create mode 100644 arch/arm/include/asm/arch-imx8ulp/cgc.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/clock.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/ddr.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/gpio.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/imx-regs.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/imx8ulp-pins.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/iomux.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/mu_hal.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/pcc.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/rdc.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/s400_api.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/sys_proto.h create mode 100644 arch/arm/include/asm/arch-imx8ulp/upower.h rename arch/arm/include/asm/{arch-imx8 => mach-imx}/image.h (95%) rename arch/arm/mach-imx/{imx8/image.c => image-container.c} (79%) create mode 100644 arch/arm/mach-imx/imx8ulp/Kconfig create mode 100644 arch/arm/mach-imx/imx8ulp/Makefile create mode 100644 arch/arm/mach-imx/imx8ulp/cgc.c create mode 100644 arch/arm/mach-imx/imx8ulp/clock.c create mode 100644 arch/arm/mach-imx/imx8ulp/iomux.c create mode 100644 arch/arm/mach-imx/imx8ulp/lowlevel_init.S create mode 100644 arch/arm/mach-imx/imx8ulp/pcc.c create mode 100644 arch/arm/mach-imx/imx8ulp/rdc.c create mode 100644 arch/arm/mach-imx/imx8ulp/soc.c create mode 100644 arch/arm/mach-imx/imx8ulp/upower/Makefile create mode 100644 arch/arm/mach-imx/imx8ulp/upower/upower_api.c create mode 100644 arch/arm/mach-imx/imx8ulp/upower/upower_api.h create mode 100644 arch/arm/mach-imx/imx8ulp/upower/upower_hal.c rename arch/arm/mach-imx/{imx8 => }/parse-container.c (98%) create mode 100644 board/freescale/imx8ulp_evk/Kconfig create mode 100644 board/freescale/imx8ulp_evk/MAINTAINERS create mode 100644 board/freescale/imx8ulp_evk/Makefile create mode 100644 board/freescale/imx8ulp_evk/ddr_init.c create mode 100644 board/freescale/imx8ulp_evk/imx8ulp_evk.c create mode 100644 board/freescale/imx8ulp_evk/lpddr4_timing.c create mode 100644 board/freescale/imx8ulp_evk/spl.c create mode 100644 configs/imx8ulp_evk_defconfig create mode 100644 drivers/ddr/imx/imx8ulp/Kconfig create mode 100644 drivers/ddr/imx/imx8ulp/Makefile create mode 100644 drivers/ddr/imx/imx8ulp/ddr_init.c create mode 100644 drivers/misc/imx8ulp/Makefile create mode 100644 drivers/misc/imx8ulp/fuse.c create mode 100644 drivers/misc/imx8ulp/imx8ulp_mu.c create mode 100644 drivers/misc/imx8ulp/s400_api.c create mode 100644 drivers/pinctrl/nxp/pinctrl-imx8ulp.c create mode 100644 include/configs/imx8ulp_evk.h create mode 100644 include/dt-bindings/clock/imx8ulp-clock.h -- 2.30.0

2 45

[v5 00/17] Add Intel N5X SoC support
by Siew Chin Lim 09 Aug '21

09 Aug '21

This is the 5th version of patchset to add Intel N5X SoC[1] support. Intel N5X SoC is with a 64-bit quad core ARM Cortex-A53 MPCore hard processor system (HPS). New IPs in N5X are clock manager and DDR subsystem, other IPs have minor changes compared to Agilex. Intel N5X SoC supports legacy boot without ATF for debugging purpose, ATF boot, and ATF boot with VAB enabled. [1]: https://www.intel.com/content/www/us/en/products/programmable/asic/easic-de… Patch status: Have changes: Patch 15 Other patches unchanged. Detail changelog can find in commit message. v4->v5: -------- Patch 15: - Sort the node name in alphanumeric order in socfpga_n5x_socdk-u-boot.dtsi - Remove duplicated qspi node from socfpga_n5x_socdk-u-boot.dtsi, It is defined in socfpga_n5x_socdk.dtsi History: -------- [v1] https://patchwork.ozlabs.org/project/uboot/cover/20210331143908.48211-1-ell… [v2] https://patchwork.ozlabs.org/project/uboot/cover/20210430073814.193576-1-el… [v3] https://patchwork.ozlabs.org/project/uboot/cover/20210613084852.30868-1-ell… [v4] https://patchwork.ozlabs.org/project/uboot/cover/20210712094921.16950-1-ell… Siew Chin Lim (14): arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux function arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h arm: socfpga: Add base address for Intel N5X device drivers: clk: Add clock driver for Intel N5X device arm: socfpga: Get clock manager base address for Intel N5X device drivers: clk: Add memory clock driver for Intel N5X device arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.h arm: socfpga: Add clock manager for Intel N5X device arm: socfpga: Changed misc_s10.c to misc_soc64.c arm: socfpga: Add SPL for Intel N5X device board: intel: Add socdk board support for Intel N5X device arm: dts: Add base dtsi and devkit dts for Intel N5X device include: configs: Add Intel N5X device CONFIGs arm: socfpga: Enable Intel N5X device build Tien Fong Chee (3): arm: socfpga: Add handoff data support for Intel N5X device ddr: socfpga: Enable memory test on memory size less than 1GB ddr: altera: Add SDRAM driver for Intel N5X device arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_n5x-u-boot.dtsi | 191 ++ arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 63 + arch/arm/dts/socfpga_n5x_socdk.dts | 127 ++ arch/arm/mach-socfpga/Kconfig | 21 +- arch/arm/mach-socfpga/Makefile | 32 +- arch/arm/mach-socfpga/board.c | 17 +- arch/arm/mach-socfpga/clock_manager_n5x.c | 80 + .../mach/{base_addr_s10.h => base_addr_soc64.h} | 11 +- arch/arm/mach-socfpga/include/mach/clock_manager.h | 3 + .../include/mach/clock_manager_agilex.h | 2 - .../include/mach/clock_manager_arria10.h | 1 - .../mach-socfpga/include/mach/clock_manager_gen5.h | 1 - .../mach-socfpga/include/mach/clock_manager_n5x.h | 12 + .../mach-socfpga/include/mach/clock_manager_s10.h | 1 - arch/arm/mach-socfpga/include/mach/firewall.h | 6 + arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 38 +- .../include/mach/system_manager_soc64.h | 10 +- arch/arm/mach-socfpga/misc.c | 3 + arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 +- arch/arm/mach-socfpga/spl_n5x.c | 94 + arch/arm/mach-socfpga/system_manager_soc64.c | 18 +- arch/arm/mach-socfpga/wrap_handoff_soc64.c | 132 +- board/intel/n5x-socdk/MAINTAINERS | 7 + board/intel/n5x-socdk/Makefile | 7 + board/intel/n5x-socdk/socfpga.c | 7 + configs/socfpga_agilex_atf_defconfig | 2 +- ...lex_atf_defconfig => socfpga_n5x_atf_defconfig} | 13 +- ..._agilex_atf_defconfig => socfpga_n5x_defconfig} | 28 +- ...lex_atf_defconfig => socfpga_n5x_vab_defconfig} | 14 +- configs/socfpga_stratix10_atf_defconfig | 2 +- drivers/clk/altera/Makefile | 4 +- drivers/clk/altera/clk-mem-n5x.c | 136 ++ drivers/clk/altera/clk-mem-n5x.h | 84 + drivers/clk/altera/clk-n5x.c | 489 +++++ drivers/clk/altera/clk-n5x.h | 217 ++ drivers/ddr/altera/Makefile | 3 +- drivers/ddr/altera/sdram_n5x.c | 2298 ++++++++++++++++++++ drivers/ddr/altera/sdram_soc64.c | 94 +- drivers/ddr/altera/sdram_soc64.h | 1 + include/configs/socfpga_n5x_socdk.h | 45 + include/configs/socfpga_soc64_common.h | 2 +- include/dt-bindings/clock/n5x-clock.h | 71 + 43 files changed, 4281 insertions(+), 119 deletions(-) create mode 100644 arch/arm/dts/socfpga_n5x-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_n5x_socdk.dts create mode 100644 arch/arm/mach-socfpga/clock_manager_n5x.c rename arch/arm/mach-socfpga/include/mach/{base_addr_s10.h => base_addr_soc64.h} (85%) create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h rename arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} (100%) create mode 100644 arch/arm/mach-socfpga/spl_n5x.c create mode 100644 board/intel/n5x-socdk/MAINTAINERS create mode 100644 board/intel/n5x-socdk/Makefile create mode 100644 board/intel/n5x-socdk/socfpga.c copy configs/{socfpga_agilex_atf_defconfig => socfpga_n5x_atf_defconfig} (83%) copy configs/{socfpga_agilex_atf_defconfig => socfpga_n5x_defconfig} (64%) copy configs/{socfpga_agilex_atf_defconfig => socfpga_n5x_vab_defconfig} (82%) create mode 100644 drivers/clk/altera/clk-mem-n5x.c create mode 100644 drivers/clk/altera/clk-mem-n5x.h create mode 100644 drivers/clk/altera/clk-n5x.c create mode 100644 drivers/clk/altera/clk-n5x.h create mode 100644 drivers/ddr/altera/sdram_n5x.c create mode 100644 include/configs/socfpga_n5x_socdk.h create mode 100644 include/dt-bindings/clock/n5x-clock.h -- 2.13.0

1 17

Re: [PATCH 05/12] mmc: nds32: ftsdc010: Convert to livetree
by Rick Chen 09 Aug '21

09 Aug '21

> From: U-Boot <u-boot-bounces(a)lists.denx.de> On Behalf Of Simon Glass > Sent: Saturday, August 07, 2021 9:24 PM > To: U-Boot Mailing List <u-boot(a)lists.denx.de> > Cc: Tom Rini <trini(a)konsulko.com>; Simon Glass <sjg(a)chromium.org>; Jaehoon Chung <jh80.chung(a)samsung.com>; Macpaul Lin <macpaul(a)andestech.com>; Peng Fan <peng.fan(a)nxp.com> > Subject: [PATCH 05/12] mmc: nds32: ftsdc010: Convert to livetree > > Use the livetree API for this driver. > > Signed-off-by: Simon Glass <sjg(a)chromium.org> > --- > > drivers/mmc/ftsdc010_mci.c | 22 +++++++--------------- > 1 file changed, 7 insertions(+), 15 deletions(-) Reviewed-by: Rick Chen <rick(a)andestech.com>

1 0

[PATCH] dm: migrate the dm_warn to use the log macro
by Patrick Delaunay 09 Aug '21

09 Aug '21

Migrate the dm_warn function to log macro with LOGC_DM category and LOGL_WARNING level. This macro allows filtering with log command and allows output on all log backend. Signed-off-by: Patrick Delaunay <patrick.delaunay(a)foss.st.com> --- drivers/core/util.c | 11 ----------- include/dm/util.h | 2 +- 2 files changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/core/util.c b/drivers/core/util.c index 91e93b0cf1..5be4ee79de 100644 --- a/drivers/core/util.c +++ b/drivers/core/util.c @@ -11,17 +11,6 @@ #include <linux/libfdt.h> #include <vsprintf.h> -#if CONFIG_IS_ENABLED(DM_WARN) -void dm_warn(const char *fmt, ...) -{ - va_list args; - - va_start(args, fmt); - vprintf(fmt, args); - va_end(args); -} -#endif - int list_count_items(struct list_head *head) { struct list_head *node; diff --git a/include/dm/util.h b/include/dm/util.h index 138893c935..c634e470e7 100644 --- a/include/dm/util.h +++ b/include/dm/util.h @@ -7,7 +7,7 @@ #define __DM_UTIL_H #if CONFIG_IS_ENABLED(DM_WARN) -void dm_warn(const char *fmt, ...); +#define dm_warn(fmt...) log(LOGC_DM, LOGL_WARNING, ##fmt) #else static inline void dm_warn(const char *fmt, ...) { -- 2.25.1

2 2

[PATCH] dm: core: Don't allow uclass use before ready
by Simon Glass 09 Aug '21

09 Aug '21

At present it is possible to call uclass_get() before driver model is inited. In fact this happens on x86 boards which use Intel FSPv1, since mrccache_get_region() tries to get the SPI flash device very early during init. This has always been undefined behaviour. Previously it generally worked, i.e. returned an error code without crashing, because gd->uclass_root_s is zeroed and the uclass can be added despite driver model not being ready, due to the way lists are implemented. With the change to use a gd->uclass_root pointer, this no-longer works. For example, it causes a hang on minnowmax. Fix this by adding a check that driver model is ready when uclass_get() is called. This function is called in the process of locating any device, so it is a good place to add the check. This fixes booting on minnowmax. Signed-off-by: Simon Glass <sjg(a)chromium.org> Fixes: 8a715530bb1 ("dm: core: Allow the uclass list to move") --- drivers/core/uclass.c | 3 +++ include/dm/uclass.h | 3 ++- test/dm/core.c | 1 + 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index 117d35ac49c..3146dfd0320 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -146,6 +146,9 @@ int uclass_get(enum uclass_id id, struct uclass **ucp) { struct uclass *uc; + /* Immediately fail if driver model is not set up */ + if (!gd->uclass_root) + return -EDEADLK; *ucp = NULL; uc = uclass_find(id); if (!uc) { diff --git a/include/dm/uclass.h b/include/dm/uclass.h index 2778818b528..da0c1bfadb1 100644 --- a/include/dm/uclass.h +++ b/include/dm/uclass.h @@ -159,7 +159,8 @@ void *uclass_get_priv(const struct uclass *uc); * * @key: ID to look up * @ucp: Returns pointer to uclass (there is only one per ID) - * @return 0 if OK, -ve on error + * @return 0 if OK, -EDEADLK if driver model is not yet inited, other -ve on + * other error */ int uclass_get(enum uclass_id key, struct uclass **ucp); diff --git a/test/dm/core.c b/test/dm/core.c index 48e66b73335..c9a7606666c 100644 --- a/test/dm/core.c +++ b/test/dm/core.c @@ -994,6 +994,7 @@ static int dm_test_uclass_before_ready(struct unit_test_state *uts) memset(&gd->uclass_root, '\0', sizeof(gd->uclass_root)); ut_asserteq_ptr(NULL, uclass_find(UCLASS_TEST)); + ut_asserteq(-EDEADLK, uclass_get(UCLASS_TEST, &uc)); return 0; } -- 2.32.0.554.ge1b32706d8-goog

1 1

[PATCH] patman: Avoid blank lines between tags
by Simon Glass 09 Aug '21

09 Aug '21

In some cases 'patman status' leaves a blank line between the sign-off and the tags it collects from patchwork. Fix this and add a test. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- tools/patman/func_test.py | 23 ++++++++++++++++++++++- tools/patman/patchstream.py | 7 ++++++- 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/tools/patman/func_test.py b/tools/patman/func_test.py index 9871bb580d0..2493e527f52 100644 --- a/tools/patman/func_test.py +++ b/tools/patman/func_test.py @@ -136,7 +136,7 @@ class TestFunctional(unittest.TestCase): Commit-changes: 2 - Changes only for this commit - Cover-changes: 4 +' Cover-changes: 4 - Some notes for the cover letter Cover-letter: @@ -1293,3 +1293,24 @@ Reviewed-by: %s self.assertEqual(terminal.PrintLine( '4 new responses available in patchwork (use -d to write them to a new branch)', None), next(lines)) + + def testInsertTags(self): + """Test inserting of review tags""" + msg = '''first line +second line.''' + tags = [ + 'Reviewed-by: Bin Meng <bmeng.cn(a)gmail.com>', + 'Tested-by: Bin Meng <bmeng.cn(a)gmail.com>' + ] + signoff = 'Signed-off-by: Simon Glass <sjg(a)chromium.com>' + tag_str = '\n'.join(tags) + + new_msg = patchstream.insert_tags(msg, tags) + self.assertEqual(msg + '\n\n' + tag_str, new_msg) + + new_msg = patchstream.insert_tags(msg + '\n', tags) + self.assertEqual(msg + '\n\n' + tag_str, new_msg) + + msg += '\n\n' + signoff + new_msg = patchstream.insert_tags(msg, tags) + self.assertEqual(msg + '\n' + tag_str, new_msg) diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py index b9602924273..2439fb18e42 100644 --- a/tools/patman/patchstream.py +++ b/tools/patman/patchstream.py @@ -662,6 +662,7 @@ def insert_tags(msg, tags_to_emit): out = [] done = False emit_tags = False + emit_blank = False for line in msg.splitlines(): if not done: signoff_match = RE_SIGNOFF.match(line) @@ -672,9 +673,13 @@ def insert_tags(msg, tags_to_emit): out += tags_to_emit emit_tags = False done = True + emit_blank = not (signoff_match or tag_match) + else: + emit_blank = line out.append(line) if not done: - out.append('') + if emit_blank: + out.append('') out += tags_to_emit return '\n'.join(out) -- 2.32.0.554.ge1b32706d8-goog

1 1